ONSEMI NB7N017MMNR2

NB7N017M
3.3V SiGe 8−Bit Dual
Modulus Programmable
Divider/Prescaler with CML
Outputs
The NB7N017M is a high speed 8–bit dual modulus
programmable divider/prescaler with 16 mA CML outputs capable
of switching at input frequencies greater than 3.5 GHz. The CML
output structure contains internal 50 W source termination resistor to
VCC. The device generates 400 mV output amplitude with 50 W
receiver resistor to VCC. This I/O structure enables easy
implementation of the NB7N017M in 50 W systems.
The differential inputs contain 50 W termination resistors to VT
pads and all differential inputs accept RSECL, ECL, LVDS,
LVCMOS, LVTTL, and CML.
Internally, the NB7N017M uses a > 3.5 GHz 8–bit programmable
down counter. A select pin, SEL, is used to select between two
words, Pa[0:7] and Pb[0:7], that are stored in REGa and REGb
respectively. Two parallel load pins, PLa and PLb, are used to load
the level triggered programming registers, REGa and REGb,
respectively. A differential clock enable, CE, pin is available.
The NB7N017M offers a differential output, TC. Terminal count
output, TC, goes high for one clock cycle when the counter has
reached the all zeros state. To reduce output phase noise, TC is
retimed with the rising edge triggered latches.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 3.5 GHz Typical
Differential CLK Clock Input
Differential CE Clock Enable Input
Differential SEL Word Select Input
50 W Internal Input and Output Termination Resistors
Differential TC Terminal Count Output
All Outputs 16 mA CML with 50 W Internal Source Termination
to VCC
All Single–Ended Control Pins CMOS and PECL/NECL
Compatible
Counter Programmed Using One of Two Single−Ended Words,
Pa[0:7] and Pb[0:7], Stored in REGa and REGb
REGa and REGb Implemented with Level Triggered Latch
Compatible with Existing 3.3 V LVEP, EP, and SG Devices
Ability to Program the Divider without Disturbing Current Settings
Positive CML Output Operating Range: VCC = 3.0 V to 3.465 V
with VEE = 0 V
Negative CML Output Operating Range: VCC = 0 V
with VEE = –3.0 V to –3.465 V
VBB Reference Voltage Output
CML Output Level: 400 mV Peak−Peak Output with 50 W Receiver
Resistor to VCC
Pb−Free Packages are Available*
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 2
1
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1
52
QFN−52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
52
1
NB7N
017M
AWLYYWWG
A
WL
YY
WW
G
= Assembly Site
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
*For additional information on our Pb−Free strategy
and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Publication Order Number:
NB7N017M/D
VTSEL
SEL
SEL
VTSEL
VTCLK
CLK
CLK
VTCLK
VBB
VTCE
CE
CE
VTCE
52
51
50
49
48
47
46
45
44
43
42
41
40
NB7N017M
Exposed Pad (EP)
VCC
1
39
VEE
PLa
2
38
PLb
Pa0
3
37
Pb0
Pa1
4
36
Pb1
Pa2
5
35
Pb2
VCC
6
34
VCC
Pa3
7
33
Pb3
VEE
8
32
VEE
Pa4
9
31
Pb4
Pa5
10
30
Pb5
Pa6
11
29
Pb6
Pa7
12
28
Pb7
NC
13
27
NC
24
25
26
NC
VEE
VEE
20
VCC
23
19
NC
VCC
18
NC
22
17
VCC
TC
16
MR
21
15
VEE
TC
14
VEE
NB7N017M
Figure 1. Pinout (Top View)
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NB7N017M
Table 1. PIN DESCRIPTION
Pin Name
I/O
Default
State
Single/Differential
(Notes 1 and 2)
Description
CLK
ECL, CML, LVCMOS,
LVDS, LVTTL Input
−
Differential
Clock
CE
ECL, CML, LVCMOS,
LVDS, LVTTL Input
−
Differential
Clock Enable
MR
CMOS, ECL Input
Low
Single
SEL
ECL, CML, LVCMOS,
LVDS, LVTTL Input
−
Differential
CMOS, ECL Input
Low
Single
CML Output
−
Differential
CMOS, ECL Input
High
Single
Power
−
−
Positive Supply
Negative Supply
PLa, PLb
TC
Pa[0:7], Pb[0:7]
VCC
VEE
Asynchronous Master Reset: Counter set to 0000 0000 to
reload at next CLK pulse, REGa and REGb = 1111 1111 and
TC = 1.
Divide Select
Parallel Load Counter Latch from Pa[0:7], Pb[0:7] (Level
Triggered)
Terminal Count, 16 mA CML output with 50 W Source
Termination to VCC (Note 5)
Counter Program Pins. CMOS and PECL/NECL compatible
Pa7 = MSB, Pb7 = MSB
Power
−
−
Termination
−
Differential
VBB
Output
−
−
CMOS/ECL Reference Voltage Output
NC
N/A
−
−
No Connect (Note 4)
EP
−
−
−
Exposed Pad (Note 3)
VTCLK, VTCLK,
VTSEL, VTSEL
VTCE, VTCE
ÑÑÑÑÑÑ
ÑÑÑÑÑÑÑ
ÑÑÑÑÑÑ
ÑÑÑÑÑÑÑ
50 W Internal Input Termination Resistor (Note 6)
1. All high speed inputs and outputs are differential to improve performance.
2. All single−ended inputs are CMOS and NECL/ECL compatible.
3. All VCC and VEE pins must be externally connected to external power supply voltage to guarantee proper device operation. The thermally
exposed pad (EP) on package bottom (see case drawing) must be attached to a heat−sinking conduit. Exposed pad is bonded to the lowest
voltage potential, VEE.
4. The NC pins are electrically connected to the die and must be left open.
5. CML outputs require 50 W receiver termination resistor to VCC for proper operation.
6. In the differential configuration when the input termination pins are connected to the common termination voltage, and if no signal is applied
then the device will be susceptible to self−oscillation.
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NB7N017M
Table 2. CE Truth Table
Table 3. SEL Truth Table
CE
Clock Status
LOW
HIGH
SEL
Clock Disabled
Clock Enabled
LOW
HIGH
Active Register
REGa
REGb
Table 4. Register Programming Values for Various Divide Ratios
Pa7/Pb7
Pa6/Pb6
Pa5/Pb5
Pa4/Pb4
Pa3/Pb3
Pa2/Pb2
Pa1/Pb1
Pa0/Pb0
Divide By
0
0
0
0
0
0
0
0
undefined
0
0
0
0
0
0
0
1
2
0
0
0
0
0
0
1
0
3
0
0
0
0
0
0
1
1
4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
1
1
1
1
1
0
1
254
1
1
1
1
1
1
1
0
255
1
1
1
1
1
1
1
1
256
Table 5. Function Table
MR
Pla
PLb
SEL
CE
CLK
Function
H
X
X
X
X
X
Master Reset (Counter programmed to 0000 0000, REGa and REGb programmed to 1111 1111 and
TC to 1)
L
H
L
X
X
X
REGa is transparent to Pa[0:7]
L
L
H
X
X
X
REGb is transparent Pb[0:7]
L
L
L
L
H
Z
Count; At TC pulse, load counter from REGa
L
L
L
H
H
Z
Count; At TC pulse, load counter from REGb
L
X
X
X
L
X
Hold
X − Don’t Care
H − HIGH
L − LOW
Z − Rising Edge
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NB7N017M
VCC
R1
R2
QINTERNAL
QINTERNAL
CLK
CLK
RT = 50 W
VTCLK
RT = 50 W
VTCLK
VEE
Figure 2. Input Structure
VCC
RT = 50 W
RT = 50 W
Q
Q
DINTERNAL
DINTERNAL
16 mA
VEE
Figure 3. Output Structure
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NB7N017M
CLK
CLK
CE
CE
CLK_INT
CLK_INT
GENERATOR
TC_INT
Counter_State [7:0]
8−BIT
COUNTER
DFF
MR
TC
GENERATOR
MUX_OUT[7:0]
SEL
SEL
MR
TCLD MUX
Pa_INT[7:0]
PLa
CLK_INT
MR
Pb_INT[7:0]
8−BIT REGa
8−BIT REGb
Pa[7:0]
PLb
Pb[7:0]
Figure 4. Block Diagram
Table 6. Interface Options
CLK INPUT interfacing options
CLK INPUT INTERFACING OPTIONS
CML
Connect VTCLK and VTCLK to VCC
LVDS
Connect VTCLK and VTCLK together
AC−COUPLED
Bias VTCLK and VTCLK Inputs within (VIHCMR)
Common Mode Range
RSECL, PECL, NECL
Standard ECL Termination Techniques or connect VTCLK and
VTCLK to VTT
LVTTL, LVCMOS
An Entered Voltage Should be Applied to the unused
Complementary Differential Input. Nominal Voltage is 1.5 V for
LVTTL and VCC/2 for LVCMOS Inputs.
Table 7. ATTRIBUTES
Characteristic
Value
Internal Input Pulldown Resistor (MR, PLa, PLb)
75 k to VEE
Internal Input Pullup Resistor (Pa[0:7], Pb[0:7])
75 k to VCC
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 7)
QFN−52
Flammability Rating Oxygen Index: 28 to 34
>500 V
>10 V
>2 kV
Pb Pkg
Pb−Free Pkg
Level 2
Level 2
UL 94 V−0 @ 0.125 in
Transistor Count
1914
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
7. For additional information, see Application Note AND8003/D.
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TC
TC
NB7N017M
Table 8. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
3.6
V
-3.6
V
3.6
-3.6
V
V
VCC
Positive Power Supply
VEE = 0 V
VEE
Negative Power Supply
VCC = 0 V
VI
Positive Input
Negative Input
VEE = 0 V
VCC = 0 V
VINPP
Differential Input Voltage
2.8 V
V
Iin
Input Current through RT (50 W Resistor)
Continuous
Surge
25
50
mA
Iout
Output Current
Continuous
Surge
25
50
mA
mA
IBB
VBB Sink/Source
$0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
(Note 8)
0 lfpm
500 lfpm
52 QFN
52 QFN
25 − 32
20 − 27
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
2S2P (Note 8)
52 QFN
4 − 15
°C/W
Tsol
Wave Solder
265
265
°C
|CLK − CLK|
VI ≤ VCC
VI ≥ VEE
VCC − VEE w 2.8 V
Pb
Pb−Free
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values
(not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage
may occur and reliability may be affected.
8. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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NB7N017M
Table 9. DC CHARACTERISTICS, POSITIVE CML OUTPUT VCC = 3.0 V to 3.465 V; VEE = 0 V (Note 11)
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
ICC
Positive Power Supply Current
170
200
230
170
200
230
170
200
230
mA
VOH
Output HIGH Voltage (Note 12)
VCC
−40
VCC
−10
VCC
VCC
−40
VCC
−10
VCC
VCC
−40
VCC
−10
VCC
mV
VOL
Output LOW Voltage (Note 12)
VCC
−400
VCC
−330
VCC
−400
VCC
−330
VCC
−400
VCC
−330
mV
Symbol
Characteristic
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 19, 21)
Vth
Input Threshold Reference Voltage
Range (Note 9)
VEE
+1125
VCC
−75
VEE
+1125
VCC
−75
VEE
+1125
VCC
−75
mV
VIH
Single−Ended Input HIGH Voltage
Vth +75
VCC
Vth +75
VCC
Vth +75
VCC
mV
VIL
Single−Ended Input LOW Voltage
VEE
Vth
−75
VEE
Vth
−75
VEE
Vth
−75
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 20, 22)
VIHD
Differential Input HIGH Voltage
VEE
+1200
VCC
VEE
+1200
VCC
VEE
+1200
VCC
mV
VILD
Differential Input LOW Voltage
VEE
VCC
−75
VEE
VCC
−75
VEE
VCC
−75
mV
VCMR
Input Common Mode Range
(Differential Cross−Point Voltage)
(Note 10)
VEE
+1200
VCC
−50
VEE
+1200
VCC
−50
VEE
+1200
VCC
−50
mV
VID
Differential Input Voltage
VEE
+100
VCC
VEE
+100
VCC
VEE
+100
VCC
mV
VBB
Output Voltage Reference @ −100 mA
1840
1970
2100
1840
1960
2100
1820
1970
2100
mV
RTIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
RTOUT
Internal Output Resistor
45
50
55
45
50
55
45
50
55
W
IIH
Input HIGH Current
CLK, CE, SEL
MR, PLa, PLb
Pa[0:7], Pb[0:7]
0
0
−50
7
30
−10
15
60
0
0
0
−50
7
30
−10
15
60
0
0
0
−50
7
30
−10
15
60
0
CLK, CE, SEL
MR, PLa, PLb
Pa[0:7], Pb[0:7]
−0.5
0
−50
20
−20
0.5
60
0
−0.5
0
−50
20
−20
0.5
60
0
−0.5
0
−50
20
−20
0.5
60
0
IIL
mA
mA
Input LOW Current
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
9. Vth is applied to the complementary input when operating in single−ended mode.
10. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the
differential input signal.
11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.165 V.
12. All loading with 50 W to VCC.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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NB7N017M
Table 10. DC CHARACTERISTICS, NEGATIVE CML OUTPUT VCC = 0 V; VEE = −3.465 V to −3.0 V (Note 16)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
ICC
Positive Power Supply Current
170
200
230
170
200
230
170
200
230
mA
VOH
Output HIGH Voltage (Note 17)
VCC
−40
VCC
−10
VCC
VCC
−40
VCC
−10
VCC
VCC
−40
VCC
−10
VCC
mV
VOL
Output LOW Voltage
(Note 17)
VCC
−400
VCC
−330
VCC
−400
VCC
−330
VCC
−400
VCC
−330
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 19, 21)
Vth
Input Threshold Reference Voltage
Range (Note 14)
VEE
+1125
VCC
−75
VEE
+1125
VCC
−75
VEE
+1125
VCC
−75
mV
VIH
Single−Ended Input HIGH Voltage
Vth
+75
VCC
Vth
+75
VCC
Vth
+75
VCC
mV
VIL
Single−Ended Input LOW Voltage
VEE
Vth
−75
VEE
Vth
−75
VEE
Vth
−75
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 20, 22)
VIHD
Differential Input HIGH Voltage
VEE
+1200
VCC
VEE
+1200
VCC
VEE
+1200
VCC
mV
VILD
Differential Input LOW Voltage
VEE
VCC
−75
VEE
VCC
−75
VEE
VCC
−75
mV
VCMR
Input Common Mode Range
(Differential Cross−Point Voltage)
(Note 15)
VEE
+1200
VCC
−50
VEE
+1200
VCC
−50
VEE
+1200
VCC
−50
mV
VID
Differential Input Voltage
VEE
+100
VCC
VEE
+100
VCC
VEE
+100
VCC
mV
VBB
Output Voltage
Reference @ −100 mA
−1460
−1330
−1200
−1460
−1330
−1200
−1460
−1330
−1200
mV
RTIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
RTOUT
Internal Output Resistor
45
50
55
45
50
55
45
50
55
W
IIH
Input HIGH Current
CLK, CE, SEL
MR, PLa, PLb
Pa[0:7], Pb[0:7]
0
0
−50
7
30
−10
15
60
0
0
0
−50
7
30
−10
15
60
0
0
0
−50
7
30
−10
15
60
0
CLK, CE, SEL
MR, PLa, PLb
Pa[0:7], Pb[0:7]
−0.5
0
−50
20
−20
0.5
60
0
−0.5
0
−50
20
−20
0.5
60
0
−0.5
0
−50
20
−20
0.5
60
0
IIL
mA
mA
Input LOW Current
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
14. Vth is applied to the complementary input when operating in single−ended mode.
15. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the
differential input signal.
16. Input and output parameters vary 1:1 with VCC.
17. All loading with 50 W to VCC.
18. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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NB7N017M
Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.465 V to −3.0 V or VCC = 3.0 V to 3.465 V; VEE = 0 V (Note 19)
−40°C
Symbol
Characteristic
Min
Typ
VOUTPP
Output Voltage Amplitude @ B 2 Mode
fin = 3.5 GHz
(See Figure 5)
300
400
tPLH,
tPHL
Propagation Delay to Output Differential
CLK to TC
MR to TC
tJITTER
RMS Random Clock Jitter fin = 3.5 GHz
(See Figure 5)
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 20)
100
tr
tf
Output Rise/Fall Times
(20% − 80%)
25
45
ts
Setup Time
(Figure 23)
Pa[7:0] to PLa
Pb[7:0] to PLb
CE to CLK
SEL to CLK
PLa to CLK
PLb to CLK
Pa[7:0] to CLK
Pb[7:0] to CLK
3750
4500
400
300
2500
3250
4750
3000
tH
Hold Time
(Figure 23)
PLa to Pa[7:0]
PLb to Pb[7:0]
CLK to CE
CLK to SEL
CLK to PLa
CLK to PLb
CLK to PLb[7:0]
CLK to PLb[7:0]
−1500
−1250
450
0
−1750
−2250
−2250
−2000
tSKEW
Minimum Pulse Width
tRR
Reset Recovery
Max
Min
Typ
300
400
85°C
Max
Min
Typ
300
400
Max
Unit
mV
ps
435
100
555
500
455
100
575
500
2.5
Device−to−Device (Note 21)
tPW
25°C
595
500
3.0
2500
100
65
25
45
2500
2000
30
120
2000
2750
3500
2500
3750
4500
400
300
2500
3250
4750
3000
−2700
−1900
40
−110
−1900
−2700
−3200
−2500
−1500
−1250
450
0
−1750
−2250
−2250
−2000
40
475
100
3.0
ps
2500
mV
65
ps
2500
100
65
25
45
2500
2000
30
120
2000
2750
3500
2500
3750
4500
400
300
2500
3250
4750
3000
2500
2000
30
120
2000
2750
3500
2500
ps
−2700
−1900
40
−110
−1900
−2700
−3200
−2500
−1500
−1250
450
0
−1750
−2250
−2250
−2000
−2700
−1900
40
−110
−1900
−2700
−3200
−2500
ps
75
40
75
40
75
ps
MR
250
85
250
85
250
85
ps
MR to CLK/CLK
3000
2500
3000
2500
3000
2500
ps
400
4
VOUTPP
300
3
200
2
100
1
RMS Jitter
0
JITTEROUT ps (RMS)
OUTPUT VOLTAGE AMPLITUDE (mV)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
19. Measured using a 400 mV source, 50% duty cycle clock source at fin = 1 GHz unless stated otherwise. All loading with 50 W to VCC. Input edge
rates 40 ps (20% − 80%).
20. VINPP (MAX) cannot exceed VCC − VEE.
21. Device−to−Device skew for identical transitions at identical VCC levels.
0
0
0.5
1
1.5
2
2.5
3
3.5
4
INPUT FREQUENCY (MHz)
Figure 5. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin)
@ Ambient Temperature (Typical)
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NB7N017M
Application Information
minimum input swing of 100 mV and the maximum input
swing of 450 mV. Within these conditions, the input
voltage can range from VCC to 1.2 V. Examples interfaces
are illustrated below in a 50 W environment (Z = 50 W).
All NB7N017M inputs can accept PECL, CML, LVTTL,
LVCMOS and LVDS signal levels. The limitations for
differential input signal (LVDS, PECL, or CML) are
VCC
50 W
VCC
50 W
Q
CLK
Z
7N017M
VCC VTCLK
VCC
VTCLK
Z
Q
50 W
7N017M
50 W
CLK
VEE
VEE
Figure 6. CML to CML Interface
VCC
VCC
50 W
PECL
Driver
VBIAS*
VBIAS*
50 W
Recommended RT Values
VCC
RT
5.0 V 290 W
2.5 V
VTCLK
VTCLK
50 W
7N017M
50 W
Z
RT
3.3 V 150 W
CLK
Z
VEE
80 W
CLK
RT
VEE
VEE
Figure 7. PECL to CML Receiver Interface
*VBIAS is within VCMR Range.
VCC
LVDS
Driver
VCC
CLK
Z
VTCLK
VTCLK
50 W
50 W
Z
CLK
VEE
VEE
Figure 8. LVDS to CML Receiver Interface
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11
7N017M
NB7N017M
VCC
VCC
CLK
Z
50 W
LVTTL/
LVCMOS
Driver
No Connect
VTCLK
7N017M
VTCLK
No Connect
50 W
VREF
Recommended VREF Values
CLK
VREF
VEE
LVCMOS VCC * VEE
2
LVTTL
1.5 V
VCC
Figure 9. LVCMOS/LVTTL to CML Receiver Interface
Table 12. OPERATION TABLE
MR
Pa
PLa
Pb
PLb
SEL
CE
CLK
CLK_INT
TC_INT
TC
1
XXXXXXXX
x
XXXXXXXX
X
X
X
X
X
X
X
0
00000101
H
00000100
H
X
H
L
H
H
H
0
00000101
H
00000100
H
X
H
L
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
L
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
L
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
X − Don’t Care
H − HIGH
L − LOW
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12
NB7N017M
Table 12. OPERATION TABLE
MR
Pa
PLa
Pb
PLb
SEL
CE
CLK
CLK_INT
TC_INT
TC
0
XXXXXXXX
L
XXXXXXXX
L
H
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
H
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
L
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
L
L
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
L
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
L
L
L
X
X
0
00000010
H
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
00000001
H
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
H
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
L
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
L
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
L
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
L
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
L
H
H
H
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
L
L
X
X
0
XXXXXXXX
L
XXXXXXXX
L
X
H
H
H
X
X
X − Don’t Care
H − HIGH
L − LOW
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13
NB7N017M
MR
Pa[7:0]
05
XX
02
XX
PLa
Pa_INT[7:0]
Pb[7:0]
05
04
02
XX
01
XX
PLb
Pb_INT[7:0]
04
SEL
CE
CLK
CLK_INT
TC_INT
TC
Figure 10. Device Timing Diagram for Table 12
MR
CLK
CE
CLK_INT
Figure 11. Timing Diagram for CE Input
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14
01
NB7N017M
MR
delay
CLK
PLa
Pa[7:0]
0B
d=12
d=12
d=12
TC[7:0]
Figure 12. Timing Diagram for PLa / PLb Inputs
(SEL is Low)
MR
delay
CLK
PLa
(hex)
Pa[7:0]
0B
d=256
d=12
d=256
d=12
TC[7:0]
Figure 13. Timing Diagram for PLa / PLb Inputs
(Before Critical Rising Edge of CLK)
(SEL is Low)
MR
delay
CLK
PLa
(hex)
Pa[7:0]
0B
d=256
d=256
d=256
d=256
d=12
TC[7:0]
Figure 14. Timing Diagram for PLa / PLb Inputs
(After Critical Rising Edge of CLK)
(SEL is Low)
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15
NB7N017M
MR
delay
CLK
SEL
Pa[7:0]
Pb[7:0]
PLa
PLb
03
02
d=4
d=4
d=4
d=3
d=3
TC[7:0]
Figure 15. Timing Diagram for SEL Input
(Before Critical Rising Edge of CLK)
MR
delay
CLK
SEL
Pa[7:0]
Pb[7:0]
PLa
PLb
03
02
d=4
d=4
d=4
d=4
d=3
TC[7:0]
Figure 16. Timing Diagram for SEL Input
(After Critical Rising Edge of CLK)
MR
CLK
Pa[7:0]
PLa
Pa_INT[7:0]
01
02
255
03
04
2
05
06
5
6
07
08
7
Pb/PLb have the same functionality as Pa/PLa
Pb[7:0]
PLb
Pb_INT[7:0]
103
201
255
255
201
10
151
27
151
27
43
176
43
MUX_OUT is the output of the internal MUX
SEL
MUX_INT[7:0]
255
2
5
151
27
Figure 17. Timing Diagram Relating PLa, PLb, Pa(0:7), Pb(0:7)
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16
43
NB7N017M
CLK
VINPP = VIH(CLK) − VIL(CLK)
CLK
TC
VOUTPP = VOH(TC) − VOL(TC)
TC
tPHL
tPLH
Figure 18. AC Reference Measurement
Vth
D
D
D
D
Vth
Figure 19. Differential Input Driven
Single−Ended
VCC
Vthmax
Figure 20. Differential Inputs Driven
Differentially
VCC
VCMmax
VIHmax
VILmax
Vth
Vthmin
GND
VIH
Vth
VIL
VCMR
VIHmin
VILmin
VCMmax
GND
Figure 21. Vth Diagram
VIHDmax
VILDmax
VID = VIHD − VILD
VIHDtyp
VILDtyp
VIHDmin
VILDmin
Figure 22. VCMR Diagram
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17
NB7N017M
CLK
Setup Time
+
−
ts
Hold Time −
+
th
Figure 23. Setup and Hold Time
VCC
NB7N017M
50 W
VCC
50 W
50 W
Receiver
Device
50 W
Q
D
Q
D
Figure 24. Typical Termination for 16 mA Output Drive and Device Evaluation
ORDERING INFORMATION
Package
Shipping†
QFN−52
260 Units / Tray
NB7N017MMNG
QFN−52
(Pb−Free)
260 Units / Tray
NB7N017MMNR2
QFN−52
2000 / Tape & Reel
QFN−52
(Pb−Free)
2000 / Tape & Reel
Device
NB7N017MMN
NB7N017MMNR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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18
NB7N017M
PACKAGE DIMENSIONS
52 PIN QFN 8x8
CASE 485M−01
ISSUE A
D
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION:
MILLIMETERS
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED
BETWEEN 0.25 AND 0.30 MM FROM
TERMINAL.
4. COPLANARITY APPLIES TO THE
EXPOSED PAD AS WELL AS THE
TERMINALS.
B
E
DIM
A
A1
A2
A3
b
D
D2
E
E2
e
K
L
2X
0.15 C
2X
0.15 C
A2
0.10 C
A
0.08 C
A3
A1
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.60
0.80
0.20 REF
0.18
0.30
8.00 BSC
6.50
6.80
8.00 BSC
6.50
6.80
0.50 BSC
0.20
−−−
0.30
0.50
REF
SEATING PLANE
C
D2
14
26
27
13
52 X
L
E2
39
1
52 X
K
52
40
e
52 X
b
NOTE 3
0.10 C A B
0.05 C
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
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damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
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NB7N017M/D