ONSEMI NB7L216MNR2

NB7L216
2.5V/3.3V, 12Gb/s Multi
Level Clock/Data Input to
RSECL, High Gain
Receiver/Buffer/Translator
with Internal Termination
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MARKING DIAGRAM*
Description
The NB7L216 is a differential receiver/driver with high gain output
targeted for high frequency applications. The device is functionally
equivalent to the NBSG16 but with much higher gain output. This
highly versatile device provides 35 dB of gain up to 7 GHz.
Inputs incorporate internal 50 W termination resistors and accept
Negative ECL (NECL), Positive ECL (PECL), LVTTL, LVCMOS,
CML, or LVDS. Outputs are Reduced Swing ECL (RSECL), 400 mV.
The VBB pin is an internally generated voltage supply available to
this device only. VBB is used as a reference voltage for single−ended
NECL or PECL inputs. For all single−ended input conditions, the
unused complementary differential input should be connected to VBB
as a switching reference voltage. VBB may also rebias AC coupled
inputs. When used, decouple VBB via a 0.01 mF capacitor and limit
current sourcing or sinking to 0.5 mA. When not used, VBB output
should be left open.
Application notes, models and support documentation are available
at www.onsemi.com.
16
1
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VTD
50 W
Features
•
•
•
•
•
High Gain of 35 dB from DC to 7 GHz Typical
High IIP3: 0 dBm Typical
20 mV Minimum Input Voltage Swing
Maximum Input Clock Frequency up to 8.5 GHz
Maximum Input Data Rate up to 12 Gb/s Typical
<0.5 ps of RMS Clock Jitter
<9 ps of Data Dependent Jitter
120 ps Typical Propagation Delay
30 ps Typical Rise and Fall Times
RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V
with VEE = 0 V
RSNECL Output with RSNECL or NECL Inputs with Operating
Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
RSECL Output Level (400 mV Peak−to−Peak Output),
50 W Internal Input Termination Resistors (Temperature−Coefficient
of < 6.38 mW/°C)
VBB – ECL Reference Voltage Output
Pb−Free Packages are Available
D
Q
D
Q
50 W
VTD
Figure 1. Functional Block Diagram
VOLTAGE (60 mV/div)
•
•
•
•
•
•
•
•
•
•
NB7L
216
ALYWG
G
QFN−16
MN SUFFIX
CASE 485G
Device DDJ = 3 ps
TIME (17 ps/div)
Figure 2. Typical Output Waveform at
12 Gb/s with PRBS 223−1 (VINPP = 400 mV,
Input Signal DDJ = 12 ps)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 2
1
Publication Order Number:
NB7L216/D
NB7L216
VEE
16
VTD
1
D
2
VBB
VEE VEE Exposed Pad (EP)
15
14
13
12 VCC
11 Q
NB7L216
D
3
10 Q
VTD
4
9
5
6
VEE
7
VCC
8
VEE VEE VEE
Figure 3. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTD
−
2
D
LVPECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted differential input. Note 1.
3
D
LVPECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted differential input. Note 1.
4
VTD
−
Internal 50 W termination pin. See Table 7. Note 1.
Internal 50 W termination pin. See Table 7. Note 1
15
VBB
−
Internally generated ECL reference voltage supply.
5, 6, 7, 8, 13, 14
VEE
−
Negative supply voltage. All VEE pins must be externally connected to power
supply to guarantee proper operation.
9, 12
VCC
−
Positive supply voltage. All VCC pins must be externally connected to power
supply to guarantee proper operation
10
Q
RSECL Output
Noninverted differential output. Typically receiver terminated with 50 W resistor
to VTT = VCC − 2.0 V.
11
Q
RSECL Output
Inverted differential output. Typically receiver terminated with 50 W resistor to
VTT = VCC − 2.0 V.
−
EP
−
Exposed pad (EP). Thermally exposed pad on the package bottom must be
attached to a heat sinking conduit. It is recommended to connect the EP to the
lower potential, VEE.
1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage and if no signal
is applied on D/D input then the device will be susceptible to self−oscillation.
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2
NB7L216
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Value
Human Body Model
Machine Model
Charged Device Model
> 500 kV
> 10 V
> 4 kV
Moisture Sensitivity (Note 2)
QFN−16
Flammability Rating
Oxygen Index: 28 to 34
Pb Pkg
Pb−Free Pkg
Level 1
Level 1
UL 94 V−0 @ 0.125 in
Transistor Count
164
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test.
2. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS (Note 3)
Rating
Unit
VCC
Positive Power Supply
Parameter
VEE = 0 V
3.6
V
VEE
Negative Power Supply
VCC = 0 V
−3.6
V
VI
Positive Input
Negative Input
VEE = 0 V
VCC = 0 V
3.6
−3.6
V
V
VINPP
Differential Input Voltage
2.8
V
IIN
Input Current Through RT (50 W Resistor)
Static
Surge
45
80
mA
mA
IOUT
Output Current
Continuous
Surge
25
50
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
(Note 4)
0 lfpm
500 lfpm
QFN−16
QFN−16
42
35
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
1S2P (Note 4)
QFN−16
4
°C/W
Tsol
Wave Solder
265
265
°C
Symbol
Condition 1
Condition 2
VI = VCC
VI = VEE
|D − D|
Pb
Pb−Free
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
3. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
4. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB7L216
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS VCC = 2.375 V to 3.465 V, VEE = 0 V
−40 5C
Symbol
Characteristic
Min
25 5C
Typ
Max
27
35
Min
85 5C
Typ
Max
27
35
Min
Typ
Max
Unit
27
35
mA
IEE
Power Supply Current (VTD/VTD
open)
VOH
Output HIGH Voltage
(Note 5 and 6)
VCC
−1040
VCC
−980
VCC
−940
VCC
−1000
VCC
−950
VCC
−900
VCC
–950
VCC
−900
VCC
−850
mV
VOL
Output LOW Voltage
(Note 5 and 6)
VCC
−1520
VCC
−1430
VCC
−1320
VCC
−1470
VCC
−1370
VCC
−1270
VCC
–1440
VCC
−1340
VCC
−1240
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 14 and 16)
VTH
Input Threshold Reference Voltage
Range (Note 7 and 8)
1100
VCC
−10
1100
VCC
−10
1100
VCC
−10
mV
VIH
Single−ended Input HIGH Voltage
(Note 8)
Vth
+10
VCC
Vth
+ 10
VCC
Vth
+10
VCC
mV
VIL
Single−ended Input LOW Voltage
(Note 8)
VEE
Vth
−10
VEE
Vth
−10
VEE
Vth
−10
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 15 and 17)
VIHD
Differential Input HIGH Voltage
(Note 9)
1105
VCC
1105
VCC
1105
VCC
mV
VILD
Differential Input LOW Voltage
(Note 9)
VEE
VCC
−10
VEE
VCC
−10
VEE
VCC
−10
mV
VCMR
Input Common Mode Range
(Differential Configuration,
Note 9 and 10)
1100
VCC
−5
1100
VCC
–5
1100
VCC
–5
mV
VID
Differential Input Voltage
(VIHD − VILD)
10
2500
10
2500
10
2500
mV
VIO
Input Offset Voltage (Note 11)
−5
0
+5
−5
0
+5
−5
0
+5
mV
VBB
Internally Generated Reference
Voltage Supply
(Only 3 V – 3.6 V Supply Load with
−100 mA)
VCC
−1425
VCC
−1345
VCC
−1265
VCC
−1425
VCC
−1345
VCC
−1265
VCC
−1425
VCC
−1345
VCC
−1265
mV
IIH
Input HIGH Current
D/Db (VTD/VTD Open)
0
20
100
0
20
100
0
20
100
mA
IIL
Input LOW Current
D/Db (VTD/VTD Open)
−25
10
75
−25
10
75
−25
10
75
mA
RTIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
RT_Coef
Internal Input Termination Resistor
Temperature Coefficient
6.38
6.38
6.38
mW/°C
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values
are applied individually under normal operating conditions and not valid simultaneously.
5. Outputs evaluated with 50 W resistors to VTT = VCC − 2.0 V for proper operation.
6. Input and output parameters vary 1:1 with VCC.
7. VTH is applied to the complementary input when operating in single−ended mode.
8. VIH, VIL and VTH parameters must be complied simultaneously.
9. VIHD, VILD and VCMR parameters must be complied simultaneously.
10. VCMR min varies 1:1 with VEE, VCMR max varies 1:1 with VCC.
11. Typical standard deviation of input offset voltage is 1.76 mV.
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NB7L216
Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.465 V, VEE = 0 V; (Note 12)
−40°C
Typ
25°C
Max
Min
Typ
85°C
Symbol
Characteristic
Min
VOUTPP
Output Voltage Amplitude (@ VINPPmin)fin ≤ 7.0 GHz
(See Figure 4)
fin ≤ 8.5 GHz
275
100
380
250
275
100
380
250
275
100
380
250
mV
fDATA
Maximum Operating Data Rate
10
12
10
12
10
12
Gb/s
|S21|
Power Gain DC to 7 GHz
35
35
35
dB
|S11|
Input Return Loss @ 7 GHz
−10
−10
−10
dB
|S22|
Output Return Loss @ 7 GHz
−5
−5
−5
dB
|S12|
Reverse Isolation (Differential Configuration)
−25
−25
−25
dB
IIP3
Input Third Order Intercept
tPLH,
tPHL
Propagation Delay to Output Differential @ 1 GHz
tSKEW
Duty Cycle Skew (Note 12)
Device to Device Skew (Note 17)
tJITTER
RMS Random Clock Jitter
fin v 8.5 GHz
(Note 15)
Peak−to−Peak Data Dependent Jitter (Note 16)
fDATA = 3.5 Gb/s
fDATA = 5.0 Gb/s
fDATA = 10 Gb/s
fDATA = 12 Gb/s
0
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 14 and Figure 12)
tr
tf
Output Rise/Fall Times @ 0.5 GHz
(20% − 80%)
60
Min
Typ
0
120
180
2
5
180
10
20
2
5
0.1
0.5
1
3
4
4
7
9
9
9
2500
30
45
60
Max
0
120
20
Q, Q
Max
dBm
120
180
ps
10
20
2
5
10
20
ps
0.1
0.5
0.1
0.5
ps
1
3
4
4
7
9
9
9
1
3
4
4
7
9
9
9
20
2500
30
60
Unit
20
45
2500
mV
45
ps
30
500
OUTPUT VOLTAGE AMPLITUDE (mV)
OUTPUT VOLTAGE AMPLITUDE (mV)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values
are applied individually under normal operating conditions and not valid simultaneously.
12. Measured by forcing VINPPmin from a 50% duty cycle clock source. All loading with an external RL = 50 W to VTT =VCC − 2.0 V. Input edge
rates 40 ps (20% − 80%).
13. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz.
14. VINPP (MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode.
15. Additive RMS jitter with 50% duty cycle clock signal.
16. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 223−1.
17. Device to device skew is measured between outputs under identical transition @ 1 GHz.
450
−40°C
400
350
85°C
300
25°C
250
200
150
100
50
0
0
2
4
6
7
8
9
10
INPUT CLOCK FREQUENCY (GHz)
11
12
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fIN) and Temperature
(VINPP = 400 mV, VCC = 3.3 V and VEE = 0 V)
500
450
400
−40°C
350
300
85°C
250
25°C
200
150
100
50
0
0
2
4
6
7
8
9
10
INPUT CLOCK FREQUENCY (GHz)
11
12
Figure 5. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fIN) and Temperature
(VINPP = 20 mV, VCC = 3.3 V and VEE = 0 V)
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VOLTAGE (60 mV/div)
VOLTAGE (60 mV/div)
NB7L216
Device DDJ = 1 ps
Device DDJ =1 ps
TIME (66 ps/div)
TIME (54 ps/div)
Figure 7. Typical Output Waveform at 3.5 Gb/s with
PRBS 223−1 (VINPP = 400 mV, Input Signal DDJ = 12 ps)
VOLTAGE (60 mV/div)
VOLTAGE (60 mV/div)
Figure 6. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV, Input Signal DDJ = 12 ps)
Device DDJ =2 ps
Device DDJ = 3 ps
TIME (37 ps/div)
TIME (21 ps/div)
Figure 8. Typical Output Waveform at 5 Gb/s with PRBS
223−1 (VINPP = 400 mV, Input Signal DDJ = 12 ps)
Figure 9. Typical Output Waveform at 10 Gb/s with
PRBS 223−1 (VINPP = 400 mV, Input Signal DDJ = 12 ps)
0
40
35
−10
25
GAIN (dB)
GAIN (dB)
30
20
15
S22
−20
S11
−30
10
−40
5
0
−50
0
2
4
6
8
10
12
14
16
0
FREQUENCY (GHz)
Figure 10. Small Signal Gain – S21 Magnitude*
2
4
6
8
10
FREQUENCY (GHz)
12
14
Figure 11. Input and Output Reflection – S11
and S22 Magnitude*
*TA = +25°C, VCC = 3.3 V, VEE=0 V, PIN = −44 dBm,ZS = ZL = 50 W, input and output matching network is not included.
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16
NB7L216
Table 6. TYPICAL DEVICE S−PARAMETERS
S11
S21
S12
S22
Frequency
(Hz)
dbS11
|S11|
íS11
dbS21
|S21|
íS21
dbS12
|S12|
íS12
dbS22
|S22|
íS22
4.97E+08
−45.2
0.005
−88.5
37.2
72.799
−33.2
−72.3
0.001
−139.1
−2.5
0.749
157.4
1.02E+09
−30.4
0.030
−134.7
37.3
73.145
−68.4
−45.8
0.005
129.8
−2.9
0.714
154.3
1.51E+09
−36.2
0.015
−146.5
37.1
71.433
−105.4
−43.3
0.007
98.5
−2.9
0.717
132.8
2.00E+09
−27.4
0.042
25.7
37.4
74.061
−139.0
−37.1
0.014
91.8
−3.5
0.666
107.1
2.52E+09
−12.3
0.244
−27.7
36.2
64.810
−179.5
−29.9
0.032
54.4
−4.4
0.599
92.1
3.01E+09
−10.6
0.295
−83.8
36.9
70.102
144.5
−26.1
0.050
9.4
−6.3
0.485
77.3
3.50E+09
−19.0
0.112
−22.1
35.4
58.933
99.9
−28.3
0.038
25.9
−5.0
0.566
67.9
4.02E+09
−10.6
0.294
−120.3
35.6
60.437
73.8
−24.8
0.058
−32.6
−7.6
0.417
54.2
4.51E+09
−10.7
0.291
167.4
36.0
62.843
41.1
−22.5
0.075
−68.3
−13.9
0.201
70.2
4.99E+09
−9.0
0.354
87.1
35.1
56.576
14.2
−25.2
0.055
−107.2
−8.7
0.367
81.2
5.48E+09
−10.6
0.294
62.7
36.4
65.812
−16.1
−24.3
0.061
−121.4
−8.0
0.398
50.4
6.01E+09
−9.3
0.341
108.2
35.8
61.327
−72.8
−24.5
0.060
−125.7
−8.0
0.397
−0.9
6.49E+09
−9.4
0.340
59.4
36.2
64.212
−119.4
−21.9
0.080
−152.4
−12.5
0.237
−27.2
6.98E+09
−17.5
0.133
25.5
34.3
52.039
−141.5
−22.7
0.073
177.5
−7.4
0.428
−32.2
7.51E+09
−25.6
0.053
107.9
33.2
45.861
164.6
−24.4
0.060
165.7
−7.0
0.445
−37.9
7.99E+09
−13.7
0.206
146.5
25.2
18.093
133.6
−21.5
0.084
152.8
−7.6
0.416
−54.7
8.52E+09
−6.7
0.462
117.9
22.6
13.434
116.2
−19.4
0.107
120.7
−12.1
0.249
−73.7
9.00E+09
−5.2
0.552
106.2
19.4
9.336
102.0
−19.0
0.112
109.9
−12.2
0.246
−62.5
9.49E+09
−3.7
0.652
71.1
19.0
8.937
61.1
−19.4
0.107
62.0
−11.5
0.267
−100.2
1.00E+10
−9.7
0.326
46.2
18.7
8.595
18.6
−24.0
0.063
50.6
−10.4
0.301
−117.0
1.05E+10
−11.0
0.283
35.8
14.5
5.298
−13.3
−25.9
0.051
12.9
−10.8
0.288
−172.0
1.10E+10
−8.3
0.384
7.2
12.9
4.408
−9.6
−29.4
0.034
21.1
−13.4
0.213
74.0
1.15E+10
−5.9
0.506
−0.4
12.7
4.339
−33.7
−21.4
0.085
36.3
−21.4
0.085
−148.6
1.20E+10
−9.0
0.356
−23.8
12.9
4.395
−63.4
−19.4
0.107
−9.5
−13.4
0.214
159.5
1.25E+10
−15.6
0.166
−46.9
10.5
3.360
−97.8
−21.0
0.089
−39.0
−12.4
0.239
169.2
1.30E+10
−15.1
0.175
−83.0
9.9
3.121
−119.7
−24.0
0.063
−39.9
−11.3
0.272
171.6
1.35E+10
−12.0
0.250
−96.5
8.7
2.728
−148.9
−22.0
0.079
−39.1
−14.9
0.181
177.8
1.40E+10
−11.5
0.265
−105.9
7.3
2.314
−167.1
−18.6
0.118
−74.2
−18.4
0.120
140.3
1.45E+10
−17.0
0.140
−97.8
5.4
1.856
167.6
−20.1
0.099
−107.0
−15.7
0.163
98.2
1.50E+10
−23.4
0.068
−108.9
4.6
1.695
145.0
−20.2
0.098
−128.1
−11.2
0.274
96.1
NOTE:
TA = +25°C, VCC=3.3V, VEE = 0 V, PIN = −44 dBm, ZS = ZL = 50 W, input and output matching network is not included.
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NB7L216
D
VINPP = VIH(D) − VIL(D)
D
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 12. AC Reference Measurement
Zo = 50 W
Q
D
Receiver
Device
Driver
Device
Zo = 50 W
Q
D
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 13. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
D
D
D
D
Vth
Vth
Figure 14. Differential Input Driven
Single−Ended
VCC
VCC
Vthmax
Vth
VIHmax
VILmax
D
Vthmin
GND
Figure 15. Differential Inputs Driven
Differentially
VIHDmax
VCMmax
VIH
Vth
VIL
VCMR
D
D
VIHmin
VILmin
NOTE:
VCMmax
GND
VILDmax
VID = VIHD − VILD
VIHDtyp
VILDtyp
VIHDmin
VILDmin
VEE v VIN v VCC; VIH > VIL
Figure 16. Vth Diagram
Figure 17. VCMR Diagram
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8
NB7L216
APPLICATION INFORMATION
All NB7L216 inputs can accept PECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential
input signal (LVDS, PECL, or CML) are minimum input swing of 75 mV and the maximum input swing of 2500 mV. Within
these conditions, the input voltage can range from VCC to 1.2 V. Examples interfaces are illustrated below in a 50 W
environment (Z = 50 W). For output termination and interface, refer to application note AND8020/D.
Table 7. INTERFACING OPTIONS
Interfacing Options
Connections
CML
Connect VTD and VTD to VCC (See Figure 18)
LVDS
Connect VTD and VTD Together (See Figure 20)
AC−COUPLED
RSECL, PECL, NECL
LVTTL, LVCMOS
Bias VTD and VTD Inputs within Common Mode Range (VCMR) (See Figure 19)
Standard ECL Termination Techniques (See Figure 13)
An External Voltage (VTHR) should be Applied to the Unused Complementary Differential Input. Nominal
VTHR is 1.5 V for LVTTL and VCC / 2 for LVCMOS Inputs. This Voltage must be within the
VTHR Specification. (See Figure 21)
VCC
VCC
50 W
50 W
Q
Z = 50 W
CML
Driver
D
VCC
Z = 50 W
VCC
Q
VTD
50 W
VTD
50 W
NB7L216
D
VEE
VEE
Figure 18. CML to NB7L216 Interface
VCC
VCC
Z = 50 W
D
VBias*
PECL
Driver
Z = 50 W
Recommended RT Values
VCC
C
VBias*
C
VTD
50 W
NB7L216
VTD
50 W
RT
RT
5.0 V 290 W
D
RT
3.3 V 150 W
2.5 V 80 W
VEE
VEE
VEE
*VBias must be within common mode range limits (VCMR)
Figure 19. PECL to NB7L216 Interface
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9
NB7L216
VCC
VCC
Z = 50 W
D
50 W
VTD
LVDS
Driver
NB7L216
VTD
Z = 50 W
50 W
D
VEE
VEE
Figure 20. LVDS to NB7L216 Interface
VCC
VCC
Z = 50 W
D
LVTTL/
LVCMOS
Driver
No Connect*
VTD
50 W
NB7L216
No Connect
VREF
VTD
50 W
Recommended VREF Values
VREF
D
LVCMOS VCC − VEE
2
VEE
*or 60 pF to GND
VCC
Figure 21. LVCMOS/LVTTL to NB7L216 Interface
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10
LVTTL
1.5 V
NB7L216
ORDERING INFORMATION
Package
Shipping †
QFN−16
123 Units / Rail
NB7L216MNG
QFN−16
(Pb−Free)
123 Units / Rail
NB7L216MNR2
QFN−16
3000 / Tape & Reel
QFN−16
(Pb−Free)
3000 / Tape & Reel
Device
NB7L216MN
NB7L216MNR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
NB7L216
PACKAGE DIMENSIONS
16 PIN QFN
CASE 485G−01
ISSUE B
D
PIN 1
LOCATION
A
B
ÇÇÇ
ÇÇÇ
ÇÇÇ
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
0.15 C
TOP VIEW
0.15 C
(A3)
0.10 C
A
16 X
0.08 C
SIDE VIEW
SEATING
PLANE
A1
C
SOLDERING FOOTPRINT*
D2
16X
0.575
0.022
e
L
5
NOTE 5
EXPOSED PAD
8
4
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.20
−−−
0.30
0.50
3.25
0.128
0.30
0.012
EXPOSED PAD
9
E2
16X
K
12
1
16
16X
1.50
0.059
3.25
0.128
13
b
0.10 C A B
0.05 C
e
BOTTOM VIEW
NOTE 3
0.50
0.02
0.30
0.012
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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For additional information, please contact your local
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NB7L216/D