NMF3000, NMF3010 Dual−Stage, Differential Lines Filter with ESD Protection The NMF3000 and the NMF3010 are a dual−stage, differential line ESD and filtering protection scheme for input signals into portable devices. The NMF3000 is the first stage and is located at or very near to the interface to the outside world. It provides the high−level ESD protection as well as the initial filtering of incoming audio signals. The NMF3010 is the second stage and provides additional signal filtering. This second stage can be placed some distance away from the first stage to allow for effective filtering across extended distances. http://onsemi.com MARKING DIAGRAMS A1 NMF 3000 ALYW A1 Features • Dual Filtering Lines for 2−Channels or Differential Transmission • Separate Power and Analog Grounds for ESD Protection and 9 Bump Flip−Chip CASE 499AE Filtering Circuitry • VCC Input Pin on First Stage to Set Microphone DC Bias • IEC 61000−4−2 Grade ±15 kV Contact ESD Protection on the Inputs, VCC, and Between Power and Analog Grounds • IEC 61000−4−2 Level 1 ESD protection on All Other Pin−to−Pin • Combinations These are Pb−Free Devices* ÈÈ ÈÈ A1 A1 6 Bump Flip−Chip CASE 499AF A L Y W Ç Ç NIO ALYW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. VCC NMF3000FCT1G NMF3010FCT1G Microphone Incoming Audio Signals C 1st Stage 2nd Stage Audio Amplifier C Figure 1. System Diagram *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2004 March, 2004 − Rev. 1 1 Publication Order Number: NMF3000/D NMF3000, NMF3010 FUNCTIONAL BLOCK DIAGRAMS VCC 15 kV Contact ESD Protection PGND LOW PASS FILTERING IN OUT 15 kV Contact ESD Protection PGND IEC Level 1 Contact ESD Protection 15 kV Contact ESD Protection AGND PGND Figure 2. First Stage: NMF3000FCT1G LOW PASS FILTERING IN OUT 15 kV Contact ESD Protection PGND IEC Level 1 Contact ESD Protection 15 kV Contact ESD Protection AGND Figure 3. Second Stage: NMF3010FCT1G http://onsemi.com 2 PGND NMF3000, NMF3010 PINOUTS AND PIN DESCRIPTIONS 1 2 3 A1 Markers A OP Vcc IP IP Vcc OP B PGND PGND PGND PGND PGND PGND C ON AGND IN IN AGND ON Top View Bumps Down Bottom View Bumps Up Figure 4. Pinout Diagrams for First Stage: NMF3000FCT1G PINOUT FUNCTIONS FOR FIRST STAGE Pin Type A1 Output P A2 VCC Description Positive Side Signal Output DC Power Connection A3 Input P Positive Side Signal Input B1, B2, B3 PGND Power Ground C1 Output N C2 AGND Analog Ground C3 Input N Negative Side Signal Input Negative Side Signal Output http://onsemi.com 3 NMF3000, NMF3010 PINOUTS AND PIN DESCRIPTIONS 1 3 2 A1 Markers A OP PGND IP IP PGND OP B ON AGND IN IN AGND ON Top View Bumps Down Bottom View Bumps Up Figure 5. Pinout Diagrams for Second Stage: NMF3010FCT1G PINOUT FUNCTIONS FOR SECOND STAGE Pin Type Description A1 Output P A2 PGND Power Ground A3 Input P Positive Side Signal Input B1 Output N Positive Side Signal Output Negative Side Signal Output B2 AGND Analog Ground B3 Input N Negative Side Signal Input http://onsemi.com 4 NMF3000, NMF3010 MAXIMUM RATINGS Rating Symbol Value Units TA −40 to 85 °C Moisture Sensitivity MSL Level 1 Storage Temperature Range Tstg −55 to 150 °C Supply Voltage VCC 0 to 11 V Operating Ambient Temperature Range Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. ELECTRICAL CHARACTERISTICS (VCC = 0 V to 10 V, TA = −40°C to 85°C, All Typical Values Measured at 25°C) Conditions Parameter Symbol Min VCC 0 Typ Max Units 10 V Supply Voltage First stage only Attenuation @ 800 MHz, 50 Environment 52 95 dB Attenuation @ 1.9 GHz, 50 Environment 52 70 dB B2B Diode Breakdown Voltage IR = 1.0 mA, Pin to PGND, AGND to PGND Standoff Voltage B2B BV ± 12 V VRM Leakage Current V = VRM, for each stage 10 IRM Power Dissipation V 500 nA 100 mW NMF3000FCT1G DC Series Resistance Input to output on first stage RI/O 997 1050 1103 NMF3010FCT1G DC Series Resistance Input to output on second stage RI/O 950 1000 1050 Input Capacitance per Line f = 1.0 MHz, for each stage when capacitor has 2.0 V across its terminals. CLINE 900 1000 1100 pF Bias Resistance per Line First Stage Only RBIAS1 950 1000 1050 Crosstalk 50 Source and Load CT −25 Noise Idle−channel or Self−noise of the Network 6.0 nV/√Hz Distortion Anywhere in the Bandwidth 20 Hz to 20 kHz 0.01 % dB 1. Specifications apply to devices as a pair, as shown in the system diagram, unless otherwise noted as ‘for each stage’. ESD CHARACTERISTICS Pin Level Type Min Units NMF3000FCT1G: A2, C2, A3, C3 to PGND NMF3010FCT1G: B2, B3, A3 to PGND 4+ IEC 61000−4−2 Contact 15 kV NMF3000FCT1G: A2, C2, A3, C3 to PGND NMF3010FCT1G: B2, B3, A3 to PGND 4 IEC 61000−4−2 Air 15 kV NMF3000FCT1G: All Pins Pairwise NMF3010FCT1G: All Pins Pairwise 1 IEC 61000−4−2 Contact 2.0 kV NMF3000FCT1G: All Pins Pairwise NMF3010FCT1G: All Pins Pairwise 1 IEC 61000−4−2 Air 2.0 kV COMPONENT MATCHING Component Resistors Capacitors Description Amount of Relative Variation between Symmetrical Resistors / Capacitors on the same Device http://onsemi.com 5 Max Unit 2.0 % 2.0 % NMF3000, NMF3010 −70 dB @ 1.9 GHz −95 dB @ 800 MHz Figure 6. Typical S21 of NMF3000FCT1G & NMF3010FCT1G in a 50 Environment 2 Lines = Positive and Negative Sides http://onsemi.com 6 NMF3000, NMF3010 DAISY CHAIN SPECIFICATIONS 1.5 mm 3 2 1 1.5 mm A B 500 m Trace Width: 30 m C Bottom View Bumps Up Figure 7. First Stage: NMF3000FCT1G 1.5 mm 3 2 1 1.0 mm A Trace Width: 30 m B 500 m Bottom View Bumps Up Figure 8. Second Stage: NMF3010FCT1G http://onsemi.com 7 NMF3000, NMF3010 DEVICE ORDERING INFORMATION Package Type Shipping† NMF3000FCT1G 9−Bump Flip−Chip 3000 / Tape and Reel NMF3010FCT1G 6−Bump Flip−Chip 3000 / Tape and Reel ENGTDDSY3x3FCT1G 9−Bump Flip−Chip 500 / Tape and Reel ENGTDDSY2x3FCT1G 6−Bump Flip−Chip 500 / Tape and Reel Device Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. http://onsemi.com 8 NMF3000, NMF3010 PACKAGE DIMENSIONS 4X Ç 0.10 C TERMINAL A1 LOCATOR FLIP−CHIP−9 CASE 499AE ISSUE A A B D E DIM A A1 A2 D E b e D1 E1 TOP VIEW A 0.10 C C 0.05 C A2 A1 SIDE VIEW NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. MILLIMETERS MIN MAX −−− 0.700 0.210 0.270 0.380 0.430 1.489 BSC 1.489 BSC 0.290 0.340 0.500 BSC 1.000 BSC 1.000 BSC SEATING PLANE D1 e C B e E1 A 9X b 1 2 3 0.05 C A B 0.03 C 4X 0.10 C TERMINAL A1 LOCATOR BOTTOM VIEW D ÈÈ A FLIP−CHIP−6 CASE 499AF ISSUE A B E MILLIMETERS DIM MIN MAX A −−− 0.700 A1 0.210 0.270 A2 0.380 0.430 D 1.489 BSC E 0.989 BSC b 0.290 0.340 e 0.500 BSC D1 1.000 BSC TOP VIEW A2 A1 0.10 C C A 0.05 C SIDE VIEW NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. SEATING PLANE D1 e B 6X b 0.05 C A B 0.03 C A 1 2 3 e BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 9 NMF3000, NMF3010 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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