SEMICONDUCTOR TECHNICAL DATA ÷ ÷ The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The MC100EL39 is pin and functionally equivalent to the MC100LVEL39 but is specified for operation at the standard 100K ECL voltage supply. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended LVECL or, if positive power supplies are used, LVPECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device (see Interfacing section of the ECLinPS Data Book DL140/D). If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the LVEL39 under single-ended input conditions, as a result, this pin can only source/sink up to 0.5mA of current. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple LVEL39s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one LVEL39, the MR pin need not be exercised as the internal divider design ensures synchronization between the ÷2/4 and the ÷4/6 outputs of a single device. • • • • • • 50ps Output-to-Output Skew 20 1 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 PIN DESCRIPTION PIN FUNCTION CLK EN MR VBB Q0, Q1 Q2, Q3 DIVSEL Diff Clock Inputs Sync Enable Master Reset Reference Output Diff ÷2/4 Outputs Diff ÷4/6 Outputs Frequency Select Input FUNCTION TABLE CLK EN MR Z ZZ X L H X L L H FUNCTION Synchronous Enable/Disable Master Reset for Synchronization 75kΩ Internal Input Pulldown Resistors >2000V ESD Protection Z = Low-to-High Transition ZZ = High-to-Low Transition Low Voltage VEE Range of –3.0 to –3.8V DIVSELa Pinout: 20-Lead SOIC (Top View) VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE 20 19 18 17 16 15 14 13 12 11 0 1 DIVSELb 0 1 1 VCC 2 3 4 EN DIVSELb CLK 5 6 7 8 CLK VBB MR VCC 9 10 NC DIVSELa 3/96 Motorola, Inc. 1996 4–1 Divide Hold Q0–3 Reset Q0–3 REV 2 Q0, Q1 OUTPUTS Divide by 2 Divide by 4 Q2, Q3 OUTPUTS Divide by 4 Divide by 6 MC100LVEL39 MC100EL39 LOGIC DIAGRAM DIVSELa Q0 CLK ÷2/4 CLK R Q0 Q1 Q1 Q2 EN ÷4/6 Q2 R Q3 MR Q3 DIVSELb CLK Q (÷2) Q (÷4) Q (÷6) Figure 1. Timing Diagrams MC100LVEL39 DC CHARACTERISTICS (VEE = –3.8V to –3.0; VCC = GND) –40°C Symbol Characteristic IEE Power Supply Current VBB Output Reference Voltage IIH Input High Current Min 0°C Typ Max 50 59 –1.38 –1.26 Min 25°C Typ Max 50 59 –1.38 –1.26 150 Min 85°C Typ Max 50 59 –1.38 –1.26 150 Min Typ Max Unit 54 61 mA –1.38 150 –1.26 V 150 µΑ Max Unit MC100LVEL39 AC CHARACTERISTICS (VEE = –3.8V to –3.0; VCC = GND) –40°C Symbol Characteristic fMAX Maximum Toggle Frequency tPLH tPHL Propagation Delay to Output tSKEW Within-Device Skew1 Min Typ 0°C Max 1000 CLK → Q (Diff) CLK → Q (S.E.) MR → Q 760 710 600 Min Typ 25°C Max 1000 960 1010 900 780 730 600 Min Typ 85°C Max 1000 980 1030 900 800 750 610 Min Typ 1000 1000 1050 910 850 800 630 MHz 1050 1100 930 ps ps Q0 – Q3 50 50 50 50 Part-to-Part Q0 – Q3 (Diff) 200 200 200 200 tS Setup Time EN → CLK DIVSEL → CLK 250 400 250 400 250 400 250 400 ps tH Hold Time CLK → EN CLK → Div_Sel 100 150 100 150 100 150 100 150 ps MOTOROLA 4–2 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100LVEL39 MC100EL39 MC100LVEL39 (continued) AC CHARACTERISTICS (VEE = –3.8V to –3.0; VCC = GND) –40°C Symbol Characteristic Min VPP Minimum Input Swing CLK 250 VCMR Common Mode Range3 VPP < 500mV VPP ≥ 500mV –2.0 –1.8 Typ 0°C Max Min Typ 25°C Max 250 Min Typ 85°C Max 250 Min Typ Max 250 Unit mV V tRR Reset Recovery Time tPW Minimum Pulse Width CLK MR 500 700 tr, tf Output Rise/Fall Times Q (20% – 80%) 280 –0.4 –0.4 –2.1 –1.9 –0.4 –0.4 100 –0.4 –0.4 100 500 700 550 –2.1 –1.9 550 –0.4 –0.4 100 500 700 280 –2.1 –1.9 100 500 700 280 550 ps ps 280 550 ps 1. Skew is measured between outputs under identical transitions. 2. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV. 3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR(min) will be fixed at 3.3V – |VCMR(min)|. MC100EL39 DC CHARACTERISTICS (VEE = –4.2V to –5.46; VCC = GND) –40°C Symbol Characteristic IEE Power Supply Current VBB Output Reference Voltage IIH Input High Current Min Typ 0°C Max 50 –1.38 Min 59 Typ 50 –1.26 –1.38 25°C Max 59 –1.26 150 Min Typ 50 –1.38 85°C Max 59 –1.26 150 Min Typ 54 –1.38 150 Max Unit 61 mA –1.26 V 150 µΑ Max Unit MC100EL39 AC CHARACTERISTICS (VEE = –4.2V to –5.46; VCC = GND) –40°C Symbol Characteristic fMAX Maximum Toggle Frequency tPLH tPHL Propagation Delay to Output tSKEW Within-Device Skew1 Min Typ 0°C Max 1000 CLK → Q (Diff) CLK → Q (S.E.) MR → Q 760 710 600 Min Typ 25°C Max 1000 960 1010 900 780 730 600 Min Typ 85°C Max 1000 980 1030 900 800 750 610 Min Typ 1000 1000 1050 910 850 800 630 MHz 1050 1100 930 ps ps Q0 – Q3 50 50 50 50 Part-to-Part Q0 – Q3 (Diff) 200 200 200 200 tS Setup Time EN → CLK DIVSEL → CLK 250 400 250 400 250 400 250 400 ps tH Hold Time CLK → EN CLK → Div_Sel 100 150 100 150 100 150 100 150 ps VPP Minimum Input Swing CLK 250 250 250 250 mV VCMR Common Mode Range3 VPP < 500mV VPP ≥ 500mV –3.2 –3.0 tRR Reset Recovery Time tPW Minimum Pulse Width CLK MR 500 700 tr, tf Output Rise/Fall Times Q (20% – 80%) 280 V –0.4 –0.4 –3.3 –3.1 100 –0.4 –0.4 100 500 700 550 –3.3 –3.1 280 –0.4 –0.4 100 500 700 550 –3.3 –3.1 280 –0.4 –0.4 100 500 700 550 280 ps ps 550 ps 1. Skew is measured between outputs under identical transitions. 2. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV. 3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = –4.5V. Note for PECL operation, the VCMR(min) will be fixed at 5.0V – |VCMR(min)|. ECLinPS and ECLinPS Lite DL140 — Rev 3 4–3 MOTOROLA MC100LVEL39 MC100EL39 OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D–04 ISSUE E –A – 20 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 1 –B – P 10 PL A B 0.010 (0.25) M B M 10 D 20 PL 0.010 (0.25) J M T S S F R X 45° C –T G K 18 PL SEATING – PLANE M DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0° 7° 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0° 7° 0.395 0.415 0.010 0.029 Motorola reserves the right to make changes without further notice to any products herein. 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