SEMICONDUCTOR TECHNICAL DATA The MC100LVEL/100EL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14 but is designed to operate in ECL or PECL mode for a voltage supply range of –3.0V to –3.8V ( or 3.0V to 3.8V). If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the LVEL14 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current. The LVEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. • • • • • • 50ps Output-to-Output Skew Synchronous Enable/Disable Multiplexed Clock Input 75kΩ Internal Input Pulldown Resistors >2000V ESD Protection VEE Range of –3.0V to –5.5V EN VCC NC 20 19 18 17 SCLK CLK 16 15 1 1 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 PIN DESCRIPTION LOGIC DIAGRAM AND PINOUT ASSIGNMENT VCC 20 CLK VBB SEL VEE 14 13 12 11 0 D Q PIN FUNCTION CLK SCLK EN SEL VBB Q0–4 Diff Clock Inputs Scan Clock Input Sync Enable Clock Select Input Reference Output Diff Clock Outputs FUNCTION TABLE CLK SCLK SEL EN Q L H X X X X X L H X L L H H X L L L L H L H L H L* * On next negative transition of CLK or SCLK 1 2 3 4 5 6 7 8 9 10 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 7/95 Motorola, Inc. 1996 4–1 REV 1 MC100LVEL14 MC100EL14 ABSOLUTE MAXIMUM RATINGS1 Symbol Characteristic Rating Unit VEE Power Supply (VCC = 0V) –8.0 to 0 VDC VI Input Voltage (VCC = 0V) 0 to –6.0 VDC Iout Output Current 50 100 mA TA Operating Temperature Range –40 to +85 °C Continuous Surge VEE Operating Range1,2 –5.7 to –4.2 1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet. 2. Parametric values specified at: 100EL Series: –4.20V to –5.50V 10EL Series: –4.94V to –5.50V V DC CHARACTERISTICS (VEE = VEE(min) – VEE(max); VCC = GND1) –40°C Symbol Characteristic 0°C to 85°C Min Typ Max Min Typ Max Unit Condition VOH Output HIGH Voltage –1085 –1005 –880 –1025 –955 –880 mV VIN = VIH(max) VOL Output LOW Voltage –1830 –1695 –1555 –1810 –1705 –1620 mV or VIL(min) VOHA Output HIGH Voltage –1095 — — –1035 — — mV VIN = VIH(max) VOLA Output LOW Voltage — — –1555 — — –1610 mV or VIL(min) VIH Input HIGH Voltage –1165 — –880 –1165 — –880 mV VIL Input LOW Voltage –1810 — –1475 –1810 — –1475 mV IIL Input LOW Current –300 0.5 — — –300 0.5 — — µA CLK Others VIN = VIL(max) 1. This table replaces the three tables traditionally seen in ECL 100K data books. The same DC parameter values at VEE = –4.5V now apply across the full VEE range of –3.0V to –5.5V. Outputs are terminated through a 50Ω resistor to –2.0V except where otherwise specified on the individual data sheets. MOTOROLA 4–2 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100LVEL14 MC100EL14 MC100LVEL14 AC/DC CHARACTERISTICS (VEE = –3.8V to –3.0V; VCC = GND) –40°C Symbol IEE Characteristic Min Power Supply Current 100LVEL 100EL 100LVEL 100EL 0°C Typ Max 32 32 40 40 Min 25°C Typ Max 32 32 40 40 Min 85°C Typ Max 32 32 40 40 Min Typ Max 34 34 42 42 Unit mA VBB Output Ref Voltage IIH Input High Current tPLH tPHL Prop Delay tSKEW Part-to-Part Skew Within-Device Skew1 tS Setup Time EN 0 0 0 0 ps tH Hold Time EN 0 0 0 0 ps VPP Minimum Input Swing CLK 150 150 150 150 mV VCMR Common Mode Range2 VPP < 500mV VPP ≥ 500mV –2.0 –1.8 –0.4 –0.4 –2.1 –1.9 –0.4 –0.4 –2.1 –1.9 –0.4 –0.4 –2.1 –1.9 –0.4 –0.4 tr tf Output Rise/Fall Times Q (20% – 80%) 230 500 230 500 230 500 230 500 CLK to Q (Diff) CLK to Q (SE) SCLK to Q –1.43 –1.38 –1.30 –1.26 –1.38 –1.38 –1.27 –1.26 150 520 470 470 720 770 770 –1.35 –1.38 –1.25 –1.31 –1.26 –1.38 150 550 500 500 750 800 800 200 50 150 580 530 530 680 680 680 200 50 780 830 830 630 580 580 200 50 –1.19 –1.26 V 150 µΑ 830 880 880 ps 200 50 ps V ps 1. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions. 2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR(min) will be fixed at 3.3V – |VCMR(min)|. MC100EL14 AC/DC CHARACTERISTICS (VEE = –4.2V to –5.5V; VCC = GND) –40°C Symbol IEE Characteristic Min Power Supply Current 100LVEL 100EL 100LVEL 100EL 0°C Typ Max 32 32 40 40 Min 25°C Typ Max 32 32 40 40 Min 85°C Typ Max 32 32 40 40 Min Typ Max 34 34 42 42 Unit mA VBB Output Ref Voltage IIH Input High Current tPLH tPHL Prop Delay tSKEW Part-to-Part Skew Within-Device Skew1 tS Setup Time EN 0 0 0 0 ps tH Hold Time EN 0 0 0 0 ps VPP Minimum Input Swing CLK 150 150 150 150 mV VCMR Common Mode Range2 VPP < 500mV VPP ≥ 500mV –3.2 –3.0 –0.4 –0.4 –3.3 –3.1 –0.4 –0.4 –3.3 –3.1 –0.4 –0.4 –3.3 –3.1 –0.4 –0.4 tr tf Output Rise/Fall Times Q (20% – 80%) 230 500 230 500 230 500 230 500 CLK to Q (Diff) CLK to Q (SE) SCLK to Q –1.43 –1.38 –1.30 –1.26 –1.38 –1.38 –1.27 –1.26 150 520 470 470 720 770 770 –1.35 –1.38 –1.25 –1.31 –1.26 –1.38 150 550 500 500 750 800 800 200 50 150 580 530 530 200 50 680 680 680 780 830 830 630 580 580 200 50 –1.19 –1.26 V 150 µΑ 830 880 880 ps 200 50 ps V ps 1. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions. 2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = –4.5V. Note for PECL operation, the VCMR(min) will be fixed at 5.0V – |VCMR(min)|. ECLinPS and ECLinPS Lite DL140 — Rev 3 4–3 MOTOROLA MC100LVEL14 MC100EL14 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E -A20 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 -B- P 10 PL 0.010 (0.25) 1 M B M 10 D 20 PL 0.010 (0.25) J M T A S B S F R X 45° C -TG K 18 PL SEATING PLANE M DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0° 7° 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0° 7° 0.395 0.415 0.010 0.029 Motorola reserves the right to make changes without further notice to any products herein. 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