MC10H352 Quad CMOS to PECL* Translator Description The MC10H352 is a quad translator for interfacing data between a CMOS logic section and the PECL section of digital systems when only a +5.0 Vdc power supply is available. The MC10H352 has CMOS compatible inputs and PECL complementary open−emitter outputs that allow use as an inverting/non−inverting translator or as a differential line driver. When the common strobe input is at a low logic level, it forces all true outputs to the PECL low logic state (≈ +3.2 V) and all inverting outputs to the PECL high logic state (≈ +4.1 V). The MC10H352 can also be used with the MC10H350 to transmit and receive CMOS information differentially via balanced twisted pair lines. http://onsemi.com MARKING DIAGRAMS* 20 MC10H352P AWLYYWWG PDIP−20 P SUFFIX CASE 738 1 Features • • • • • Single +5.0 V Power Supply All VCC Pins Isolated On Chip Differentially Drive Balanced Lines tpd = 1.3 nsec Typical Pb−Free Packages are Available* 1 20 10H352G AWLYYWW 20 1 PLLC−20 FN SUFFIX CASE 775 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 February, 2006 − Rev. 7 1 Publication Order Number: MC10H352/D MC10H352 B IN 7 A IN 8 D IN 12 C IN 14 COMMON 9 STROBE B OUT 1 20 ECL VCC B OUT 2 19 C OUT N.C. 3 18 C OUT A OUT 4 17 D OUT A OUT 5 16 D OUT VCC 6 15 VCC 2 1 B OUT 2 B OUT 5 4 A OUT A OUT 16 D OUT 17 D OUT 19 C OUT B IN 7 14 C IN 18 C OUT A IN COMMON STROBE 8 13 N.C. 9 12 D IN 10 11 CMOS VCC VCC (+5.0 VDC) = PINS 6, 11, 15, 20 GND = PIN 10 GND Figure 1. Logic Diagram Pin assignment is for Dual−in−Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). Figure 2. Pin Assignment Table 1. MAXIMUM RATINGS Symbol Rating Unit Power Supply 0 to +7.0 Vdc VI Input Voltage (VCC = 5.0 V) 0 to VCC Vdc Iout Output Current 50 100 mA TA Operating Temperature Range 0 to +75 °C Tstg Storage Temperature Range −55 to +150 −55 to +165 °C VCC Characteristic Continuous Surge Plastic Ceramic Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. http://onsemi.com 2 MC10H352 Table 2. ELECTRICAL CHARACTERISTICS (VCC = VCC1 = VCC2 = 5.0 V ± 5.0%) (Note 1) 0° Symbol ECL TTL IR IF V(BR)in VI Characteristic Min 25° Max Power Supply Current Min 75° Max Min Max Unit 50 45 50 mA 20 15 20 mA Reverse Current Pins 7, 8, 12, 14 Pin 9 25 100 20 80 25 100 Forward Current Pins 7, 8, 12, 14 Pin 9 −0.8 −3.2 −0.6 −2.4 −0.8 −3.2 Input Voltage Breakdown mA mA 5.5 5.5 Input Clamp Voltage (Iin = −18 mA) 5.5 −1.5 Vdc −1.5 −1.5 Vdc VOH High Output Voltage (Note 2) 3.98 4.16 4.02 4.19 4.08 4.27 Vdc VOL Low Output Voltage (Note 2) 3.05 3.37 3.05 3.37 3.05 3.37 Vdc VIH High Input Voltage 3.15 VIL Low Input Voltage 3.15 3.15 1.5 Vdc 1.5 1.5 Vdc *Positive Emitter Coupled Logic 1. Each MECL 10H™ series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. Outputs are terminated through a 50 W resistor to VCC − 2.0 Vdc. 2. With VCC at 5.0 V. VOH/VOL change 1:1 with VCC. Table 3. AC PARAMETERS 0° Symbol 25° 75° Characteristic Min Max Min Max Min Max Unit Propagation Delay (Note 3) 0.4 1.9 0.4 2.0 0.4 2.1 ns tr Rise Time (20% to 80%) 0.4 1.9 0.4 2.0 0.4 2.1 ns tf Fall Time (80% to 20%) 0.4 1.9 0.4 2.0 0.4 2.1 ns Maximum Operating Frequency 150 tpd fmax 150 150 MHz NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Propagation delay is measured on this circuit from VCC/2 on the input waveform to the 50% point on the output waveform. http://onsemi.com 3 MC10H352 ORDERING INFORMATION Package Shipping † MC10H352FN PLLC−20 46 Units / Rail MC10H352FNG PLLC−20 (Pb−Free) 46 Units / Rail MC10H352FNR2 PLLC−20 500 / Tape & Reel MC10H352FNR2G PLLC−20 (Pb−Free) 500 / Tape & Reel MC10H352P PDIP−20 18 Unit / Rail MC10H352PG PDIP−20 (Pb−Free) 18 Unit / Rail Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 MC10H352 PACKAGE DIMENSIONS 20 LEAD PLLC CASE 775−02 ISSUE E 0.007 (0.180) M T L−M B Y BRK −N− U N S 0.007 (0.180) M T L−M S S N S D −L− −M− Z W 20 D 1 V 0.007 (0.180) M T L−M S N S R 0.007 (0.180) M T L−M S N S Z T L−M S N H J 0.007 (0.180) M T L−M S −T− VIEW S SEATING PLANE F 0.007 (0.180) M T L−M S VIEW S N S N S K 0.004 (0.100) G S S K1 E G1 0.010 (0.250) S T L−M S VIEW D−D A C 0.010 (0.250) G1 X NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSIONS IN INCHES. 3. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 4. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM −T−, SEATING PLANE. 5. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 6. DIMENSIONS IN THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). http://onsemi.com 5 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 −−− 0.025 −−− 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 −−− 0.020 2_ 10 _ 0.310 0.330 0.040 −−− MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 −−− 0.64 −−− 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 −−− 0.50 2_ 10 _ 7.88 8.38 1.02 −−− N S MC10H352 PACKAGE DIMENSIONS PDIP−20 P SUFFIX PLASTIC DIP PACKAGE CASE 738−03 ISSUE E −A− 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C −T− K SEATING PLANE G M N E F D J 0.25 (0.010) 20 PL 0.25 (0.010) 20 PL M T A M T B M M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 MECL 10H is a trademark of Motorola, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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