MTD10N10EL TMOS E−FET Power Field Effect Transistor DPAK for Surface Mount N−Channel Enhancement−Mode Silicon Gate This advanced TMOS E−FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain−to−source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. http://onsemi.com RDS(ON) TYP VDSS ID MAX 0.22 Ω 100 V 10 A N−Channel D Features • Avalanche Energy Specified • Source−to−Drain Diode Recovery Time Comparable to a Discrete G Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature • Surface Mount Package Available in 16 mm, 13−inch/2500 S MARKING DIAGRAM & PIN ASSIGNMENTS Unit Tape & Reel, Add T4 Suffix to Part Number Drain−to−Source Voltage Symbol Value Unit VDSS 100 Vdc Drain−to−Gate Voltage (RGS = 1.0 MΩ) VDGR 100 Vdc Gate−to−Source Voltage — Continuous — Non−Repetitive (tp ≤ 10 ms) VGS VGSM ±15 ±20 Vdc Vpk ID ID 10 6.0 35 Adc PD 40 0.32 1.75 Watts W/°C Watts TJ, Tstg −55 to 150 °C Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 µs) Total Power Dissipation @ TC = 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 2) Operating and Storage Temperature Range IDM 3 DPAK CASE 369C (Surface Mount) Style 2 ORDERING INFORMATION Package Shipping† MTD10N10EL DPAK 75 Units/Rail MTD10N10ELT4 DPAK 2500 Tape & Reel Device EAS mJ Thermal Resistance — Junction to Case — Junction to Ambient (Note 1) — Junction to Ambient (Note 2) RθJC RθJA RθJA 3.13 100 71.4 °C/W TL 260 °C 50 2 1 Drain 3 Gate Source 10N10EL=Device Code Y = Year WW = Work Week Apk Single Pulse Drain−to−Source Avalanche Energy — Starting TJ = 25°C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 10 Apk, L = 1.0 mH, RG =25 Ω) Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds 1 2 YWW 10N 10EL Parameter 4 Drain 4 MAXIMUM RATINGS (TC = 25°C unless otherwise noted) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1. When surface mounted to an FR4 board using minimum recommended pad size. 2. When surface mounted to an FR4 board using 0.5 sq in pad size. Semiconductor Components Industries, LLC, 2004 March, 2004 − Rev. 1 1 Publication Order Number: MTD10N10EL/D MTD10N10EL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 100 — — 115 — — — — — — 10 100 — — 100 1.0 — 1.45 4.0 2.0 — mV/°C — 0.17 0.22 Ohm — — 1.85 — 2.6 2.3 gFS 2.5 7.9 — mhos Ciss — 741 1040 pF Coss — 175 250 Crss — 18.9 40 td(on) — 11 20 tr — 74 150 td(off) — 17 30 tf — 38 80 QT — 9.3 15 Q1 — 2.56 — Q2 — 4.4 — Q3 — 4.66 — — — 0.98 0.898 1.6 — trr — 124.7 — ta — 86 — tb — 38.7 — QRR — 0.539 — — 4.5 — — 7.5 — OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C µAdc nAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (VGS = 5.0 Vdc, ID = 5.0 Adc) RDS(on) Drain−to−Source On−Voltage (VGS = 5.0 Vdc, ID = 10 Adc) (VGS = 5.0 Vdc, ID = 5.0 Adc, TJ = 125°C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc) Vdc Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 50 Vdc, ID = 10 Adc, VGS = 5.0 5 0 Vdc, Vdc RG = 9.1 Ω) Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 80 Vdc, ID = 10 Adc, VGS = 5.0 Vdc) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (Note 3) (IS = 10 Adc, VGS = 0 Vdc) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (S Figure (See Fi 14) (IS = 10 Adc, VGS = 0 Vdc, dIS/dt = 100 A/µs) Reverse Recovery Stored Charge VSD Vdc ns µC INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25″ from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS 3. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 nH nH MTD10N10EL TYPICAL ELECTRICAL CHARACTERISTICS 20 7V VGS = 10 V TJ = 25°C VDS ≥ 5 V 5V ID , DRAIN CURRENT (AMPS) ID , DRAIN CURRENT (AMPS) 20 4.5 V 15 4V 10 3.5 V 5 3V −55°C 15 25°C TJ = 100°C 10 5 2V 0 0 1 2 3 0 5 4 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.35 Figure 2. Transfer Characteristics RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) Figure 1. On−Region Characteristics VGS = 10 V 100°C 0.25 TJ = 25°C 0.15 −55°C 0.05 0 5 10 15 2 3 4 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 20 0.25 TJ = 25°C VGS = 5 V 0.2 10 V 0.15 0.1 5 0 ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current and Temperature 15 Figure 4. On−Resistance versus Drain Current and Gate Voltage 2 100 VGS = 5 V ID = 5 A VGS = 0 V TJ = 125°C 1.5 I DSS , LEAKAGE (nA) R DS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 10 ID, DRAIN CURRENT (AMPS) 1 0.5 0 − 50 − 25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 10 100°C 1 150 0 20 40 60 80 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 3 1 MTD10N10EL POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 1800 1600 VDS = 0 V VGS = 0 V TJ = 25°C Ciss C, CAPACITANCE (pF) 1400 1200 1000 800 Ciss Crss 600 400 Coss 200 0 10 Crss 5 0 VGS 5 10 15 20 25 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 QT 75 VGS 8 60 45 0 Q2 Q1 4 VDS Q3 0 2 4 30 TJ = 25°C ID = 10 A 6 8 15 0 10 1000 t, TIME (ns) 90 12 VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) MTD10N10EL TJ = 25°C ID = 10 A VDS = 100 V VGS = 5 V 100 tr tf td(off) td(on) 10 1 1 10 1 RG, GATE RESISTANCE (OHMS) QG, TOTAL GATE CHARGE (nC) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS I S , SOURCE CURRENT (AMPS) 10 VGS = 0 V TJ = 25°C 8 6 4 2 0 0.5 0.6 0.7 0.8 0.9 1.0 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance−General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RθJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. http://onsemi.com 5 MTD10N10EL SAFE OPERATING AREA VGS = 20 V SINGLE PULSE TC = 25°C 10 µs 10 100 µs 1 ms 10 ms 1 dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 1 10 50 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 100 ID = 10A 40 30 20 10 0 100 25 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area 1 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.0 D = 0.5 0.2 0.1 0.1 P(pk) 0.05 0.02 0.01 t1 SINGLE PULSE 0.01 0.00001 RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RθJC(t) t2 DUTY CYCLE, D = t1/t2 0.0001 0.001 0.01 0.1 1.0 t, TIME (ms) Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 6 10 MTD10N10EL PACKAGE DIMENSIONS DPAK CASE 369C−01 ISSUE O −T− C B V SEATING PLANE E R 4 Z A S 1 2 DIM A B C D E F G H J K L R S U V Z 3 U K F J L H D G 2 PL 0.13 (0.005) M T INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− MTD10N10EL E−FET is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 8 For additional information, please contact your local Sales Representative. MTD10N10EL/D