MTD5P06V Preferred Device Power MOSFET 5 Amps, 60 Volts P−Channel DPAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Specified • IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com V(BR)DSS RDS(on) TYP ID MAX 60 V 340 m 5.0 A P−Channel D MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Symbol Value Unit VDSS 60 Vdc Drain−to−Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc Gate−to−Source Voltage − Continuous − Non−repetitive (tp ≤ 10 ms) VGS VGSM ± 15 ± 25 Vdc Vpk ID ID 5 4 18 Adc 40 0.27 2.1 Watts W/°C W/ C Watts TJ, Tstg −55 to 175 °C EAS 125 mJ Total Power Dissipation @ 25°C 25°C Derate above 25 C Total Power Dissipation @ TA = 25°C (Note 2.) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 5 Apk, L = 10 mH, RG = 25 Ω) Thermal Resistance − Junction to Case − Junction to Ambient (Note 1.) − Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds S IDM PD 3.75 100 71.4 TL 260 4 Drain 4 Apk 1 2 3 DPAK CASE 369C Style 2 2 1 3 Drain Gate Source 4 °C/W RθJC RθJA RθJA MARKING DIAGRAMS YWW 5P06V Drain Current − Continuous @ 25°C Drain Current − Continuous @ 100°C Drain Current − Single Pulse (tp ≤ 10 µs) G °C 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2. When surface mounted to an FR−4 board using the 0.5 sq.in. drain pad size. 4 Drain 1 YWW 5P06V Rating Drain−to−Source Voltage 2 3 DPAK CASE 369D Style 2 5P06V Y WW Device Code = Year = Work Week 1 2 3 Gate Drain Source ORDERING INFORMATION Device Package Shipping DPAK 75 Units/Rail NTD5P06V−1 DPAK Straight Lead 75 Units/Rail NTD5P06VT4 DPAK 2500 Tape & Reel NTD5P06V Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2003 November, 2003 − Rev. 3 1 Publication Order Number: MTD5P06V/D MTD5P06V ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 − − 61.2 − − − − − − 10 100 − − 100 2.0 − 2.8 4.7 4.0 − mV/°C − 0.34 0.45 Ohm − − − − 2.7 2.6 1.5 3.6 − Ciss − 367 510 Coss − 140 200 Crss − 29 60 td(on) − 11 20 tr − 26 50 td(off) − 17 30 OFF CHARACTERISTICS Drain−Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C µAdc nAdc ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 2.5 Adc) RDS(on) Drain−Source On−Voltage (VGS = 10 Vdc, ID = 5 Adc) (VGS = 10 Vdc, ID = 2.5 Adc, TJ = 150°C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc) Vdc Vdc gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 4.) Turn−On Delay Time (VDD = 30 Vdc, ID = 5 Adc, VGS = 10 Vdc, Vdc RG = 9.1 Ω) Rise Time Turn−Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 5 Adc, VGS = 10 Vdc) tf − 19 40 QT − 12 20 Q1 − 3.0 − Q2 − 5.0 − Q3 − 5.0 − − − 1.72 1.34 3.5 − trr − 97 − ta − 73 − tb − 24 − QRR − 0.42 − − 4.5 − − 7.5 − ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 5 Adc, VGS = 0 Vdc) (IS = 5 Adc, VGS = 0 Vdc, TJ = 150°C) Reverse Recovery Time (IS = 5 Adc Adc, VGS = 0 Vdc, Vdc dIS/dt = 100 A/µs) Reverse Recovery Stored Charge VSD Vdc ns µC INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25″ from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS 3. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 nH nH MTD5P06V TYPICAL ELECTRICAL CHARACTERISTICS I D , DRAIN CURRENT (AMPS) VGS = 10V 8 10 8V 9V 7V TJ = 25°C 6V 6 4 5V 2 1 2 3 4 5 6 8 7 100°C 7 6 5 4 3 2 2 4 5 6 7 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics VGS = 10 V TJ = 100°C 0.45 0.4 25°C 0.35 0.3 8 0.4 TJ = 25°C VGS = 10 V 0.35 0.5 15 V 0.3 0.25 − 55°C 0.25 0.2 1 2 3 4 5 6 7 ID, DRAIN CURRENT (AMPS) 8 9 10 0.2 1 Figure 3. On−Resistance versus Drain Current and Temperature 3 4 5 7 6 ID, DRAIN CURRENT (AMPS) 8 9 10 100 1.8 1.6 2 Figure 4. On−Resistance versus Drain Current and Gate Voltage VGS = 0 V VGS = 10 V ID = 2.5 A 1.4 I DSS , LEAKAGE (nA) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 3 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.6 0.55 25°C 8 0 9 R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) 0 TJ = −55°C 1 4V 0 VDS ≥ 10 V 9 I D , DRAIN CURRENT (AMPS) 10 1.2 1 0.8 0.6 TJ = 125°C 10 0.4 0.2 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 1 175 0 Figure 5. On−Resistance Variation with Temperature 50 10 20 30 40 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 3 60 MTD5P06V POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 1000 VDS = 0 V Ciss 900 TJ = 25°C C, CAPACITANCE (pF) 800 700 600 Crss 500 Ciss 400 300 Coss 200 100 0 Crss VGS = 0 V 10 0 5 VGS 5 10 15 20 25 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 60 9 VGS QT 54 48 8 7 Q2 Q1 42 6 36 5 30 4 24 3 18 2 VDS 1 0 TJ = 25°C ID = 5 A Q3 0 2 4 6 10 8 12 12 6 0 14 100 TJ = 25°C ID = 5 A VDD = 30 V VGS = 10 V t, TIME (ns) 10 VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) MTD5P06V tr td(off) tf 10 td(on) 1 1 10 Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance 100 DRAIN−TO−SOURCE DIODE CHARACTERISTICS 5 TJ = 25°C VGS = 0 V I S , SOURCE CURRENT (AMPS) 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance−General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RθJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. http://onsemi.com 5 MTD5P06V SAFE OPERATING AREA 140 VGS = 20 V SINGLE PULSE TC = 25°C EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 100 10 100 µs 1 ms 1 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 dc 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) ID = 5 A 120 100 80 60 40 20 0 100 25 50 75 100 125 150 175 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 P(pk) 0.1 0.05 0.02 t1 0.01 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.01 1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 t, TIME (s) Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 6 RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RθJC(t) 1.0E+00 1.0E+01 MTD5P06V PACKAGE DIMENSIONS DPAK CASE 369C−01 ISSUE O −T− C B V SEATING PLANE E R 4 Z A S 1 2 DIM A B C D E F G H J K L R S U V Z 3 U K F J L H D G 2 PL 0.13 (0.005) M T INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− MTD5P06V PACKAGE DIMENSIONS DPAK CASE 369D−01 ISSUE O C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F H D G 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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