Revised October 2001 74LCXH162374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold and 26Ω Series Resistors in Outputs General Description Features The LCXH162374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. ■ 5V tolerant control inputs and outputs The LCXH162374 is designed for low voltage (2.5V or 3.3V) VCC applications. The LCXH162374 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 26Ω series resistor in the output helps reduce output overshoot and undershoot. ■ Implements patented noise/EMI reduction circuitry The LCXH162374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. ■ Equivalent 26Ω series resistors on output ■ 2.3V–3.6V VCC specifications provided ■ 7.0 ns tPD max (VCC = 3.3V), 20 µA ICC max ■ Power down high impedance inputs and outputs ■ ±12 mA output drive (VCC = 3.0V) ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human body model > 2000V Machine model > 200V ■ Bushold on inputs eliminates the need for external pull-up/pull-down resistors ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Code: Package Number Order Number 74LCXH162374GX (Note 1) BGA54A (Preliminary) Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 74LCXH162374MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBES] 74LCXH162374MEX (Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 74LCXH162374MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBES] 74LCXH162374MTX (Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] Note 1: BGA package available in Tape and Reel only. Note 2: Use this order number to receive devices in Tape and Reel. Logic Symbol GTO is a trademark of Fairchild Semiconductor Corporation. © 2001 Fairchild Semiconductor Corporation DS500446 www.fairchildsemi.com 74LCXH162374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold and 26Ω Series Resistors in Outputs February 2001 74LCXH162374 Connection Diagrams Pin Descriptions Pin Assignment for SSOP and TSSOP Pin Names Description OEn Output Enable Input (Active LOW) CPn Clock Pulse Input I0–I15 Inputs (Bushold) O0–O15 Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A O0 NC OE1 CP1 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 I12 G O12 O11 VCC VCC I11 H O14 O13 NC NC I13 I14 J O15 NC OE2 CP2 NC I15 Truth Tables Inputs CP1 Pin Assignment for FBGA Outputs OE1 I0–I7 O0–O7 L H H L L L L L X O0 X H X Z Inputs CP2 (Top Thru View) Outputs OE2 I8–I15 O8–O15 L H H L L L L L X O0 X H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of CP www.fairchildsemi.com 2 the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops. The LCXH162374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store Logic Diagrams Byte 1 (0:7) Byte 2 (8:15) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74LCXH162374 Functional Description 74LCXH162374 Absolute Maximum Ratings(Note 3) Symbol Parameter Value Supply Voltage VI DC Input Voltage Units V −0.5 to VCC + 0.5 I0 - I15 OEn, LEn VO Conditions −0.5 to +7.0 VCC V −0.5V to 7.0V −0.5 to +7.0 DC Output Voltage 3-STATE −0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 4) IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND +50 VO > VCC V mA mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions (Note 5) Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage IOH/IOL Output Current in IOH/IOL TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Min Max Operating 2.0 3.6 Data Retention 1.5 3.6 0 VCC HIGH or LOW State 0 VCC 3-STATE 0 5.5 VCC = 3.0V − 3.6V ±12 VCC = 2.7V − 3.0V ±8 VCC = 2.3V − 2.7V ±4 Units V V V mA −40 85 °C 0 10 ns/V Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: Floating or unused control inputs must be HIGH or LOW. DC Electrical Characteristics Symbol VIH VIL VOH VOL II Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage IOH = −100 µA HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current www.fairchildsemi.com VCC TA = −40°C to +85°C (V) Min 2.3 − 2.7 1.7 2.7 − 3.6 2.0 V 2.3 − 2.7 0.7 2.7 − 3.6 0.8 2.3 − 3.6 V VCC − 0.2 IOH = −4 mA 2.3 1.8 IOH = −4mA 2.7 2.2 IOH = −6 mA 3.0 2.4 IOH = −8 mA 2.7 2.0 IOH = −12 mA 3.0 2.0 IOL = 100 µA V 2.3 − 3.6 0.2 IOL = 4 mA 2.3 0.6 IOL = 4 mA 2.7 0.4 IOL = 6 mA 3.0 0.55 IOL = 8 mA 2.7 0.6 IOL = 12 mA 3.0 0.8 Data VI = VCC or GND 2.3 − 3.6 ±5.0 Control 0V ≤ VI ≤ 5.5V 2.3 − 3.6 ±5.0 4 Units Max V µA Symbol (Continued) Parameter TA = −40°C to +85°C VCC Conditions (V) II(HOLD) Bushold Input Minimum VIN = 0.7V Drive Hold Current VIN = 1.7V (Note 7) Current to Change State (Note 8) (Note 8) 3-STATE Output Leakage VO = VCC or GND IOFF Power-Off Leakage Current VO = VCC 300 −300 ICC Quiescent Supply Current µA 450 −450 2.3 − 3.6 ±5.0 µA 0 10 µA VI = VCC or GND 2.3 − 3.6 20 3.6V ≤ VO ≤ 5.5V (Note 6) 2.3 − 3.6 ±20 VIH = V CC −0.6V 2.3 − 3.6 500 VI = VIH or VIL Increase in ICC per Input −75 3.6 IOZ µA 75 2.7 (Note 7) ∆ICC −45 3.0 VIN = 2.0V Bushold Input Over-Drive Units Max 45 2.3 VIN = 0.8V II(OD) Min µA µA Note 6: Outputs disabled or 3-STATE only. Note 7: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 8: An external driver must sink at least the specified current to switch from HIGH-to-LOW. AC Electrical Characteristics TA = −40° to +85°C, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V CL = 50 pF CL = 50 pF CL = 30 pF Min Max Min Max Min Max 7.0 1.5 7.3 1.5 8.4 Units fMAX Maximum Clock Frequency 170 tPHL Propagation Delay 1.5 tPLH CP to On 1.5 7.0 1.5 7.3 1.5 8.4 tPZL Output Enable time 1.5 6.9 1.5 7.1 1.5 9.0 1.5 6.9 1.5 7.1 1.5 9.0 Output Disable Time 1.5 6.0 1.5 6.2 1.5 7.2 1.5 6.0 1.5 6.2 1.5 7.2 tS Setup Time 2.5 2.5 3.0 ns tH Hold Time 1.5 1.5 2.0 ns tW Pulse Width 3.0 3.0 3.5 ns tOSHL Output to Output Skew (Note 9) tPZH tPLZ tPHZ MHz 1.0 tOSLH 1.0 ns ns ns ns Note 9: Skew is defined as the absolute value of the differences between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. 5 www.fairchildsemi.com 74LCXH162374 DC Electrical Characteristics 74LCXH162374 Dynamic Switching Characteristics Symbol VCC TA = 25°C (V) Typical CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.35 CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 0.25 CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.35 CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 −0.25 Parameter VOLP Quiet Output Dynamic Peak VOL VOLV Quiet Output Dynamic Valley VOL Conditions Units V V Capacitance Typical Units CIN Symbol Input Capacitance Parameter VCC = Open, VI = 0V or VCC 7 pF COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 20 pF www.fairchildsemi.com Conditions 6 74LCXH162374 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V, and 2.7V VCC x 2 at VCC = 2.5 ± 0.2V tPZH, tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol VCC 3.3V ± 0.3V 2.7V 2.5V ± 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL + 0.3V VOL + 0.3V VOL + 0.15V Vy VOH − 0.3V VOH − 0.3V VOH − 0.15V 7 www.fairchildsemi.com 74LCXH162374 Schematic Diagram Generic for LCXH Family (with Bushold) www.fairchildsemi.com 8 74LCXH162374 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary 9 www.fairchildsemi.com 74LCXH162374 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A www.fairchildsemi.com 10 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 11 www.fairchildsemi.com 74LCXH162374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold and 26Ω Series Resistors in Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)