Revised November 2000 74LVT574 • 74LVTH574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The LVT574 and LVTH574 are high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. ■ Input and output interface capability to systems at 5V VCC The LVTH574 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. ■ Live insertion/extraction permitted These octal flip-flops are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT574 and LVTH574 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH574), also available without bushold feature (74LVT574). ■ Power Up/Down high impedance provides glitch-free bus loading ■ Outputs source/sink −32 mA/+64 mA ■ Functionally compatible with the 74 series 574 ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V Ordering Code: Order Number Package Number 74LVT574WM Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74LVT574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVT574MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74LVT574MTC MTC20 74LVTH574WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74LVTH574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH574MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74LVTH574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS012451 www.fairchildsemi.com 74LVT574 • 74LVTH574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs March 1999 74LVT574 • 74LVTH574 Connection Diagram Pin Descriptions Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input OE 3-STATE Output Enable Input O0–O7 3-STATE Outputs Truth Table Inputs OE On L H L L X L L Oo X X H Z Dn H L CP Outputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition Oo = Previous Oo before HIGH to LOW of CP Functional Description Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The LVT574 and LVTH574 consist of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Symbol Parameter Value Conditions Units VCC Supply Voltage −0.5 to +4.6 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Output in 3-STATE −0.5 to +7.0 Output in HIGH or LOW State (Note 2) V V V IIK DC Input Diode Current −50 VI < GND mA IOK DC Output Diode Current −50 VO < GND mA IO DC Output Current 64 VO > VCC Output at HIGH State 128 VO > VCC Output at LOW State mA ICC DC Supply Current per Supply Pin ±64 mA IGND DC Ground Current per Ground Pin ±128 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VI Input Voltage IOH HIGH-Level Output Current IOL LOW-Level Output Current TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Min Max Units 2.7 3.6 V 0 5.5 V −32 mA 64 mA −40 85 °C 0 10 ns/V Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 2: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol VCC (V) Parameter T A = −40°C to +85°C Min Typ Max Units Conditions (Note 3) −1.2 VIK Input Clamp Diode Voltage VIH Input HIGH Voltage VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC − 0.2 2.7 2.4 3.0 2.0 VOL II(HOLD) 2.7 2.7–3.6 Output LOW Voltage Bushold Input Minimum Drive 0.8 (Note 4) Current to Change State II Input Current IOFF Power Off Leakage Current IPU/PD Power Up/Down 3-STATE Output Current VO ≥ VCC − 0.1V V IOH = −8 mA IOH = −32 mA IOL = 100 µA 2.7 0.5 IOL = 24 mA 3.0 0.4 3.0 0.5 IOL = 32 mA 3.0 0.55 IOL = 64 mA 3.0 75 V µA 500 µA −500 Data Pins V 0.2 3.0 Control Pins II = −18 mA VO ≤ 0.1V or IOH = −100 µA −75 Bushold Input Over-Drive V V 2.7 (Note 4) II(OD) 2.0 3.6 10 3.6 ±1 −5 3.6 ±100 VI = 0.8V VI = 2.0V (Note 5) (Note 6) VI = 5.5V µA VI = 0V or VCC VI = 0V VI = VCC 1 0 IOL = 16 mA µA 0–1.5V ±100 µA 0V ≤ VI or VO ≤ 5.5V VO = 0.5V to 3.0V VI = GND or VCC IOZL 3-STATE Output Leakage Current 3.6 −5 µA VO = 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 µA VO = 3.0V 3 www.fairchildsemi.com 74LVT574 • 74LVTH574 Absolute Maximum Ratings(Note 1) 74LVT574 • 74LVTH574 DC Electrical Characteristics Symbol Parameter (Continued) VCC (V) T A = −40°C to +85°C Min Typ Max Units Conditions (Note 3) IOZH+ 3-STATE Output Leakage Current 3.6 10 µA VCC < VO ≤ 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs High ICCL Power Supply Current 3.6 5 mA Outputs Low ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ+ Power Supply Current 3.6 0.19 mA VCC ≤ VO ≤ 5.5V, ∆ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC − 0.6V Outputs Disabled Other Inputs at VCC or GND (Note 7) Note 3: All typical values are at VCC = 3.3V, TA = 25°C. Note 4: Applies to bushold versions only (74LVTH574). Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol Parameter (Note 8) TA = 25°C VCC (V) Min Typ Max Conditions Units CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 9) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.8 V (Note 9) Note 8: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA = −40°C to +85°C CL = 50 pF, RL = 500Ω Symbol VCC = 3.3V ± 0.3V Parameter Min Typ (Note 10) VCC = 2.7V Max Min Max fMAX Maximum Clock Frequency 150 tPHL Propagation Delay 1.8 4.6 1.8 5.3 tPLH CP to On 1.8 4.5 1.8 5.3 tPZL Output Enable Time tPZH tPLZ Output Disable Time tPHZ Units 150 MHz 1.5 5.2 1.5 6.1 1.5 4.8 1.5 5.9 2.0 4.4 2.0 4.4 2.0 4.8 2.0 5.1 ns ns ns tS Setup Time 2.0 2.4 tH Hold Time 0.3 0.0 ns tW Pulse Width 3.3 3.3 ns tOSHL Output to Output Skew (Note 11) tOSLH ns 1.0 1.0 1.0 1.0 ns Note 10: All typical values are at VCC = 3.3V, TA = 25°C. Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Capacitance (Note 12) Typical Units CIN Symbol Input Capacitance Parameter VCC = Open, VI = 0V or VCC Conditions 4 pF COUT Output Capacitance VCC = 3.0V, VO = 0V or VCC 6 pF Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. www.fairchildsemi.com 4 74LVT574 • 74LVTH574 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com 74LVT574 • 74LVTH574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74LVT574 • 74LVTH574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 7 www.fairchildsemi.com 74LVT574 • 74LVTH574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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