VICOR VIV0007TFJ

VIV0007TFJ
®
US
C
S
C
NRTL
US
VTM
DC to DC
Voltage Transformer
TM
FEATURES
• 50 Vdc to 1.56 Vdc 115 A Voltage Transformer
TM
- Operating from standard 48 V or 24 V PRM regulators
• 130 A rated with reduced case temperature at 30°C
• High efficiency (>91.5%) reduces system power
consumption
• High density (103 A/in2)
• “Full Chip” V• I Chip package enables surface mount,
low impedance interconnect to system board
• Contains built-in protection features:
-
Overvoltage Lockout
Overcurrent
Short Circuit
Over Temperature
• Provides enable / disable control, internal temperature
monitoring, current monitoring
• ZVS / ZCS resonant Sine Amplitude Converter topology
• Less than 50ºC temperature rise at full load
DESCRIPTION
The V• I Chip Voltage Transformer is a high efficiency (>91.5%)
Sine Amplitude Converter (SAC)TM operating from a 26 to 55 Vdc
primary bus to deliver an isolated output. The Sine Amplitude
Converter offers a low AC impedance beyond the bandwidth of
most downstream regulators, which means that capacitance
normally at the load can be located at the input to the Sine
Amplitude Converter. Since the K factor of the VIV0007TFJ is
1/32, that capacitance value can be reduced by a factor of
1024, resulting in savings of board area, materials and total
system cost.
The VIV0007TFJ is provided in a V• I Chip package compatible
with standard pick-and-place and surface mount assembly
processes. The co-molded V•I Chip package provides enhanced
thermal management due to large thermal interface area and
superior thermal conductivity. With high conversion efficiency
the VIV0007TFJ increases overall system efficiency and lowers
operating costs compared to conventional approaches.
The VIV0007TFJ enables the utilization of Factorized Power
ArchitectureTM providing efficiency and size benefits by lowering
conversion and distribution losses and promoting high density
point of load conversion.
in typical applications
TYPICAL APPLICATION
VIN = 26 to 55 V
IOUT = 115 A (NOM)
• High End Computing Systems
• Automated Test Equipment
• High Density Power Supplies
VOUT = 0.81 to 1.71 V (NO LOAD)
K = 1/32
PART NUMBER
DESCRIPTION
VIV0007TFJ
-40°C to 125°C TJ
Regulator
VC
SG
OS
CD
PR
PC
TM
IL
Voltage Transformer
PC
IM
VC
TM
VTM
PRM
+In
+Out
-In
-Out
+In
+Out
-In
-Out
VIN
L
O
A
D
Factorized Power Architecture
(See Application Note AN:024)
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1
7/2009
Page 1 of 18
v i c o r p o w e r. c o m
VIV0007TFJ
PRELIMINARY DATASHEET
1.0 ABSOLUTE MAXIMUM VOLTAGE RATINGS
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent
damage to the device.
MIN
MAX
UNIT
MIN
MAX
UNIT
+ IN to - IN . . . . . . . . . . . . . . . . . . . . . . .
-1.0
60
VDC
IM to - IN.................................................
PC to - IN . . . . . . . . . . . . . . . . . . . . . . . .
-0.3
20
VDC
+ IN / - IN to + OUT / - OUT (hipot)........
TM to -IN . . . . . . . . . . . . . . . . . . . . . . . .
-0.3
7.0
VDC
+ IN / - IN to + OUT / - OUT (working)...
VC to - IN . . . . . . . . . . . . . . . . . . . . . . . .
11.5
16.5
VDC
+ OUT to - OUT.......................................
0
-1.0
3.15
VDC
100
VDC
60
VDC
5.5
VDC
2.0 ELECTRICAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40°C < TJ < 125°C (T-Grade); All other specifications are at TJ = 25ºC unless otherwise noted.
ATTRIBUTE
SYMBOL
Input Voltage Range
VIN
VIN Slew Rate
MIN
TYP
26
0
VIN_UV
No Load Power Dissipation
PNL
DC Input Current
Transfer Ratio
Output Voltage
IIN_DC
K
VOUT
Output Current (Average)
IOUT_AVG
Output Current (Peak)
Output Power (Average)
IOUT_PK
POUT_AVG
ηAMB
Efficiency (Ambient)
ηHOT
η20%
Efficiency (Hot)
Efficiency (Over Load Range)
Output Resistance (Cold)
Output Resistance (Ambient)
Output Resistance (Hot)
Switching Frequency
Output Ripple Frequency
ROUT_COLD
ROUT_AMB
ROUT_HOT
FSW
FSW_RP
Output Voltage Ripple
VOUT_PP
Output Inductance (Parasitic)
LOUT_PAR
Output Capacitance (Internal)
COUT_INT
PROTECTION
OVLO
Overvoltage Lockout
Response Time
Output Overcurrent Trip
Short Circuit Protection Trip Current
Output Overcurrent Response
Time Constant
Short Circuit Protection Response Time
Module latched shutdown,
No external VC applied, IOUT = 115A
VIN = 50 V
VIN = 26 V to 55 V
VIN = 50 V, TC = 25ºC
VIN = 26 V to 55 V, TC = 25ºC
K = VOUT / VIN, IOUT = 0 A
VOUT = VIN • K - IOUT • ROUT, Section 11
30°C < Tc < 100°C,
IOUT_MAX = - (3/14) * TC + 136.43
TC = 30ºC
TPEAK <10 ms, IOUT_AVG ≤ 115 A
IOUT_AVG ≤ 115 A
VIN = 50 V, IOUT = 115 A
VIN = 26 V to 55 V, IOUT = 115 A
VIN = 50 V, IOUT = 57.5 A
VIN = 50 V, IOUT = 130 A
VIN = 50 V, Tc = 100°C, IOUT = 115 A
23 A < IOUT < 115 A
TC = -40°C, IOUT = 115 A
TC = 25°C, IOUT = 115 A
TC = 100°C, IOUT = 115 A
18
26
V
4.59
7.3
8.3
5.5
6.3
4.5
Module latched shutdown
TOVLO
Effective internal RC filter
IOCP
ISCP
115
130
200
185
55.1
Effective internal RC filter (Integrative).
TSCP
From detection to cessation
of switching (Instantaneous)
125
VDC
W
A
V/V
V
A
A
W
90.4
%
91.5
90.1
89.9
0.855
1.01
1.175
1.56
3.12
1.1
1.16
1.45
1.65
3.3
%
%
mΩ
mΩ
mΩ
MHz
MHz
170
200
mV
150
pH
360
µF
56.9
59.4
0.2
138
250
TOCP
TJ_OTP
1/32
89.3
81.7
90.3
88.9
88.3
80
0.55
0.8
0.9
1.48
2.96
UNIT
V/µs
2
COUT = 0 F, IOUT = 115 A, VIN = 50 V,
20 MHz BW, Section 12
Frequency up to 30 MHz,
Simulated J-lead model
VIN_OVLO+
MAX
55
55
1
dVIN /dt
VIN UV Turn Off
Thermal Shutdown Setpoint
CONDITIONS / NOTES
No external VC applied
VC applied
178
V
µs
250
A
A
6.5
ms
1
µs
130
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
135
ºC
Rev. 1.1
7/2009
Page 2 of 18
v i c o r p o w e r. c o m
VIV0007TFJ
PRELIMINARY DATASHEET
3.0 SIGNAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40°C < TJ < 125°C (T-Grade); All other specifications are at TJ = 25°C unless otherwise noted.
• Used to wake up powertrain circuit.
• A minimum of 11.5 V must be applied indefinitely for VIN < 26 V
to ensure normal operation.
• VC slew rate must be within range for a succesful start.
SIGNAL TYPE
STATE
ATTRIBUTE
External VC Voltage
VTM CONTROL : VC
• PRM VC can be used as valid wake-up signal source.
• VC voltage may be continuously applied;
there will be no VC current drawn when VIN > 26 V.
SYMBOL
VVC_EXT
Steady
VC Current Draw
ANALOG
INPUT
Start Up
Transitional
VC Slew Rate
IVC
dVC/dt
VC Inrush Current
IINR_VC
VC to PC Delay
TVC_PC
Internal VC Capacitance
CVC_INT
CONDITIONS / NOTES
Required for startup, and operation
below 26 V. See Section 7.
VC = 11.5 V, VIN = 0 V
VC = 11.5 V, VIN > 26 V
Fault mode. VC > 11.5 V
Required for proper startup;
0 ºC < TC < 100 ºC
Required for proper startup;
-40 ºC < TC < 100 ºC
VC = 16.5 V, dVC/dt = 0.25 V/µs
VC = 11.5 V to PC high, VIN = 0 V,
dVC/dt = 0.25 V/µs
VC = 0 V
MIN
TYP
MAX UNIT
11.5
0
115
0
60
16.5
V
150
0
mA
0.001
0.25
0.0025
0.25
V/µs
75
250
mA
125
µs
1
µF
PRIMARY CONTROL : PC
• The PC pin enables and disables the VTM.
• Module will shutdown when pulled low with an impedance
When held below 2.0 V, the VTM will be disabled.
less than 850 Ω.
• PC pin outputs 5 V during normal operation. PC pin is equal to 2.5 V
• In an array of VTMs, connect PC pin to synchronize startup.
during fault mode given VIN > 26 V and VC > 11.5 V.
• PC pin can't sink current and will not disable other module
• After successful start-up and under no fault condition, PC can be used as
during fault mode.
a 5 V regulated voltage source with a 2 mA maximum current.
SIGNAL TYPE
STATE
Steady
ANALOG
OUTPUT
Start Up
Enable
Disable
DIGITAL
INPUT / OUPUT
Transitional
ATTRIBUTE
PC Voltage
PC Source Current
PC Resistance (Internal)
PC Source Current
PC Capacitance (Internal)
PC Resistance (External)
PC Voltage
PC Voltage (Disable)
PC Pull Down Current
PC Disable Time
PC Fault Response Time
SYMBOL
CONDITIONS / NOTES
VPC
IPC_OP
RPC_INT
IPC_EN
CPC_INT
RPC_EXT
VPC_EN
VPC_DIS
IPC_PD
TPC_DIS_T
TFR_PC
Internal pull down resistor
MIN
TYP
4.7
5
50
50
150
100
60
2
2.5
Section 7
MAX UNIT
5.3
2
400
300
1000
3
2
5.1
5
100
From fault to PC = 2.0 V
V
mA
kΩ
µA
pF
kΩ
V
V
mA
µs
µs
TEMPERATURE MONITOR : TM
• The TM pin monitors the internal temperature of the VTM controller IC
• The TM pin has a room temperature setpoint of 3 V
within an accuracy of ±5°C.
and approximate gain of 10 mV/°C.
• Can be used as a "Power Good" flag to verify that the VTM is operating.
SIGNAL TYPE
STATE
ANALOG
OUTPUT
Steady
Disable
DIGITAL OUTPUT
(FAULT FLAG)
Transitional
ATTRIBUTE
TM Voltage
TM Source Current
TM Gain
SYMBOL
VTM_AMB
ITM
ATM
TM Voltage Ripple
VTM_PP
TM Voltage
TM Resistance (Internal)
TM Capacitance (External)
TM Fault Response Time
VTM_DIS
RTM_INT
CTM_EXT
TFR_TM
CONDITIONS / NOTES
TJ controller = 27°C
MIN
TYP
2.95
3
MAX UNIT
3.05
100
V
µA
mV/°C
200
mV
50
50
V
kΩ
pF
µs
10
CTM = 0 F, VIN = 50 V,
IOUT = 50 A
Internal pull down resistor
From fault to TM = 1.5 V
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
120
25
0
40
10
Rev. 1.1
7/2009
Page 3 of 18
v i c o r p o w e r. c o m
VIV0007TFJ
PRELIMINARY DATASHEET
3.0 SIGNAL CHARACTERISTICS (CONT.)
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40°C < TJ < 125°C (T-Grade); All other specifications are at TJ = 25°C unless otherwise noted.
CURRENT MONITOR : IM
• The IM pin voltage varies between 0.2 V and 1.97 V representing the
output current within ±25% under all operating line temperature
conditions between 50% and 100%.
SIGNAL TYPE
STATE
ANALOG
OUTPUT
ATTRIBUTE
SYMBOL
IM Voltage (No Load)
IM Voltage (50%)
IM Voltage (Full Load)
IM Gain
IM Resistance (External)
Steady
• The IM pin provides a DC analog voltage proportional to
the output current of the VTM.
VIM_NL
VIM_50%
VIM_FL
A IM
RIM_EXT
CONDITIONS / NOTES
TJ = 25ºC, VIN = 50 V, IOUT = 0 A
TJ = 25ºC, VIN = 50 V, IOUT = 57.5 A
TJ = 25ºC, VIN = 50 V, IOUT = 115 A
TJ = 25ºC, VIN = 50 V, IOUT > 57.5 A
MIN
TYP
MAX
UNIT
0.2
0.25
0.95
1.97
18
0.3
V
V
V
mV/A
MΩ
2.5
4.0 TIMING DIAGRAM
IOUT
6
7
ISCP
IOCP
1
2 3
VC
4
5
d
8
g
b
VVC-EXT
a
VOVLO
Vin
NL
≥ 26 V
c
e
Vout
TM
VTM-amb
PC
f
5V
3V
a: VC slew rate (dVC/dt)
b: Minimum VC pulse rate (see section 5)
c: TOVLO
d: TOCP
e: PC disable time (TPC-dis)
f: VC to PC delay
g: TSCP
1. Initiated VC pulse
2. Controller start
3. VIN ramp up
4. VIN = VOVLO
5. VIN ramp down no VC pulse
6. Overcurrent
7. Start up on short circuit
8. PC driven low
Caution:
The module is not designed to start in this sequence.
Notes:
– Timing and voltage is not to scale
– Error pulse width is load dependent
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1
7/2009
Page 4 of 18
v i c o r p o w e r. c o m
VIV0007TFJ
PRELIMINARY DATASHEET
5.0 APPLICATION CHARACTERISTICS
The following values, typical of an application environment, are collected at TJ = 25ºC unless otherwise noted. See associated figures
for general trend data.
ATTRIBUTE
SYMBOL
No Load Power Dissipation
Efficiency (Ambient)
Efficiency (Hot)
Output Resistance (Ambient)
Output Resistance (Hot)
Output Resistance (Cold)
PNL
ηAMB
ηHOT
ROUT_AMB
ROUT_HOT
ROUT_COLD
Output Voltage Ripple
VOUT_PP
VOUT Transient (Positive)
VOUT_TRAN+
VOUT Transient (Negative)
VOUT_TRAN-
CONDITIONS / NOTES
TYP
UNIT
VIN = 49 V, PC enabled
VIN = 49 V, IOUT = 115 A
VIN = 49 V, IOUT = 115 A
VIN = 49 V
VIN = 49 V
VIN = 49 V
COUT = 0 F, IOUT = 115 A, VIN = 50 V,
20 MHz BW, Section 12
IOUT_STEP = 0 A TO 130A, VIN = 50 V,
ISLEW >10 A /us
IOUT_STEP = 130 A to 0 A, VIN = 50 V
ISLEW > 10 A /us
3.8
90.4
89.4
1.03
1.21
0.89
W
%
%
mΩ
mΩ
mΩ
167
mV
120
mV
160
mV
115 A Load Efficiency vs. TCASE
94
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
92
Efficiency (%)
90
88
86
84
82
80
78
26
29
32
36
39
42
45
49
52
-40
55
-20
Input Voltage (V)
-40°C
TCASE:
25°C
100°C
40
60
80
100
26 V
49 V
55 V
Figure 2 – Full load efficiency vs. temperature
Efficiency & Power Dissipation -40°C Case
Efficiency & Power Dissipation 25°C Case
94
86
82
24
20
16
12
8
4
0
78
PD
74
70
66
0
26
52
78
104
η
90
Efficiency (%)
η
90
Power Dissipation (W)
94
86
82
26 V
49 V
55 V
24
20
16
12
8
4
0
78
74
PD
70
66
0
130
26
52
78
104
130
Load Current (A)
Load Current [A]
VIN:
20
Case Temperature (°C)
VIN :
Figure 1 – No load power dissipation vs. VIN
Efficiency (%)
0
Power Dissipation (W)
Power Dissipation (W)
No Load Power Dissipation vs. Line Voltage
26 V
Figure 3 – Efficiency and power dissipation at –40°C
49 V
55 V
VIN:
26 V
49 V
55 V
26 V
49 V
55 V
Figure 4 – Efficiency and power dissipation at 25°C
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1
7/2009
Page 5 of 18
v i c o r p o w e r. c o m
VIV0007TFJ
PRELIMINARY DATASHEET
Efficiency & Power Dissipation 100°C Case
ROUT vs. TCASE at VIN = 49 V
1.25
Efficiency (%)
86
82
24
20
16
12
8
4
0
78
74
PD
70
66
0
23
46
69
92
1.20
1.15
ROUT (mΩ)
η
90
Power Dissipation (W)
94
1.10
1.05
1.00
0.95
0.90
0.85
-40
115
-20
Load Current (A)
26 V
VIN:
49 V
55 V
0
20
40
60
80
100
Case Temperature (ºC)
26 V
49 V
I OUT :
55 V
11.5 A
115 A
57.5 A
Figure 6 – ROUT vs. temperature
Figure 5 – Efficiency and power dissipation at 100°C
Output Voltage Ripple vs. Load
190
VRIPPLE (mV PK-PK)
170
150
130
110
90
70
50
30
10
11.5
23
34.5
46
57.5
69
80.5
92
103.5 115
Load Current (A)
VIN:
Figure 7 – Full load ripple, 100 µF CIN; No external COUT.
Board mounted module, scope setting : 20 MHz analog BW, digital
filter 1.5 bits -3 dB @ 12 MHz
50 V
55 V
Figure 8 – VRIPPLE vs. IOUT ; VIN, No external COUT.
Board mounted module, scope setting : 20 MHz analog BW, digital
filter 1.5 bits -3 dB @ 12 MHz
Safe Operating Area
140
220
200
Maximum Load Current vs. TCASE
135
130
180
160
140
120
Limited by Power
<10 ms , 200 A Maximum Current
< 30°C TCASE 130 A Maximum Current Region
100
80
60
40
Limited by ROUT
115 A Maximum Current Region
IOUT_MAX (A)
Output Current (A)
26 V
125
120
115
110
105
100
95
20
0
90
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Output Voltage (V)
Figure 9 – Safe operating area
1.4
1.6
1.8
2.0
2.2
-40
-20
0
20
40
60
80
100
Case Temperature (°C)
Figure 10 – Maximum load current using IOUT_MAX = - (3/14) * TC +
136.43. Junction temperature less than 125°C
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1
7/2009
Page 6 of 18
v i c o r p o w e r. c o m
VIV0007TFJ
PRELIMINARY DATASHEET
IM Voltage vs. Load 25°C Case
2.25
2.25
2.00
2.00
1.75
1.75
1.50
1.50
IM (V)
IM (V)
IM Voltage vs. Load at VIN = 49 V
2.50
1.25
1.00
1.00
0.75
0.75
0.50
0.50
0.25
0.25
0.00
1.25
0.00
12
23
35
46
58
69
81
92
104
115
12
23
Load Current (A)
TCASE :
-40°C
25°C
35
46
58
69
81
92
104
115
Load Current (A)
100°C
VIN:
26 V
49 V
55 V
Figure 12 – IM voltage vs. load
Figure 11 – IM voltage vs. load
IM Voltage at 115 A Load vs. TCASE
2.50
IM (V)
2.25
2.00
1.75
1.50
-40
-20
0
20
40
60
80
100
Case Temperature (ºC)
VIN:
26 V
49 V
55 V
Figure 13 – Full load IM voltage vs. TCASE
Figure 14 – Start up from application of VIN: VC pre-applied
Figure 15 – 0 A– 130 A transient response:
CIN = 100 µF, no external COUT
Figure 16 – 130 A – 0 A transient response:
CIN = 100 µF, no external COUT
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1
7/2009
Page 7 of 18
v i c o r p o w e r. c o m
VIV0007TFJ
PRELIMINARY DATASHEET
6.0 GENERAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40ºC < TJ < 125ºC (T-Grade); All Other specifications are at TJ = 25°C unless otherwise noted.
ATTRIBUTE
SYMBOL
MECHANICAL
Length
Width
Height
Volume
Weight
Lead Finish
L
W
H
Vol
W
CONDITIONS / NOTES
TYP
MAX
UNIT
32.25 / 1.27
21.75 / 0.86
6.48 / 0.255
32.5 / 1.28
22.0 / 0.87
6.73 / 0.265
4.82 / 0.29
0.512 / 14.5
32.75 / 1.29
22.25 / 0.88
6.98 / 0.275
mm/in
mm/in
mm/in
cm3/in3
oz/g
No heat sink
Nickel
Palladium
Gold
THERMAL
Operating Temperature
Thermal Capacity
MIN
TJ
0.51
0.02
0.003
-40
Supported by J-lead only
TST
MSL
ESDHBM
ESD Withstand
ESDCDM
225°C Reflow
Human Body Model,
"JEDEC JESD 22-A114C.01"
Charged Device Model,
"JEDEC JESD 22-C101D"
5
-40
5
1000
MTBF
Agency Approvals / Standards
°C
Ws/°C
6
lbs
125
°C
VDC
400
SOLDERING
Peak Temperature During Reflow
Peak Time Above 183°C
Peak Heating Rate During Reflow
Peak Cooling Rate Post Reflow
1.5
2.5
VIN_OUT
VHIPOT
CIN_OUT
RIN_OUT
Unpowered Unit
MIL HDBK 217 Plus, 25ºC,
Ground Benign
Telcordia Issue 2, Method I
cTUVus
cULus
CE Mark
RoHS 6 of 6
100
0.018
10
µm
125
9
ASSEMBLY
Peak Compressive Force
Applied to Case (Z-axis)
Storage Temperature
Moisture Sensitivity Level
SAFETY
Working Voltage (IN – OUT)
Isolation Voltage (hipot)
Isolation Capacitance
Isolation Resistance
2.03
0.15
0.051
0.02
4.6
225
150
2
3
°C
s
°C/s
°C/s
60
VDC
VDC
µF
MΩ
0.022
MHrs
7.19
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1
7/2009
Page 8 of 18
v i c o r p o w e r. c o m
VIV0007TFJ
7.0 USING THE CONTROL SIGNALS VC, PC, TM, IM
VTM Control (VC) pin is an input pin which powers the
internal VCC circuitry within the specified voltage range of 26
V to 55 V. This voltage is required in order for the VTM to start,
and must be applied as long as the input is below 26 V. In order
to ensure a proper start, the slew rate of the applied voltage
must be within the specified range. VC must be applied first to
activate the controller prior to the input. When the input
voltage is applied, the VTM output voltage will track the input
allowing for a soft-start. If the VC voltage is removed prior to
the input reaching 26 V, the VTM may shut down.
Some additional notes on using the VC pin:
• In most applications, the VTM will be powered by an
upstream PRM, in which case the PRM will provide a typical
10 ms VC pulse during startup. In these applications the VC
pins of the PRM and VTM should be tied together.
• The fault response of the VTM is latching. A positive edge on
VC, or toggling PC if VC is continuously applied, is required
in order to restart the unit.
• The VTM is designed for continuous operation
with VC applied.
Primary Control (PC) pin can be used to accomplish the
following functions:
• Delayed start: Upon the application of VC, the PC pin will
source a constant 100 µA current to the internal RC
network. Adding an external capacitor will allow further
delay in reaching the 2.5 V threshold for module start.
• Auxiliary voltage source: Once enabled in regular
operational conditions (no fault), each VTM PC provides a
regulated 5 V, 2 mA voltage source.
• Output disable: PC pin can be actively pulled down in order
to disable the module. Pull down impedance shall be lower
than 850 Ω.
• Fault detection flag: The PC 5 V voltage source is internally
turned off as soon as a fault is detected. It is important to
notice that PC doesn’t have current sink capability. Therefore,
in an array, PC line will not be capable of disabling
neighboring modules if a fault is detected.
• Fault reset: PC may be toggled to restart the unit if VC
is continuously applied.
PRELIMINARY DATASHEET
Temperature Monitor (TM) pin provides a voltage
proportional to the absolute temperature of the converter
control IC.
It can be used to accomplish the following functions:
• Monitor the control IC temperature: The temperature in
Kelvin is equal to the voltage on the TM pin scaled
by 100. (i.e. 3.0 V = 300 K = 27ºC). If a heat sink is applied,
TM can be used to thermally protect the system.
• Fault detection flag: The TM voltage source is internally
turned off as soon as a fault is detected. For system
monitoring purposes (microcontroller interface) faults are
detected on falling edges of TM signal.
Current Monitor (IM) pin provides a voltage proportional to
the output current of the VTM. The voltage will vary between
0.25 V and 1.97 V over the output current range of the VTM
(See Figures 11–13). The accuracy of the IM pin will be within
25% under all line and temperature conditions between 50%
and 100% load. The accuracy of the pin can be improved
using a predictive algorithm based on the input voltage and
internal temperature.
8.0 THERMAL CONSIDERATIONS
V• I Chip products are multi-chip modules whose temperature
distribution varies greatly for each part number as well as with
the input / output conditions, thermal management and
environmental conditions. Maintaining the top of the
VIV0007TFJ case to less than 100ºC will keep all junctions
within the V• I Chip below 125ºC for most applications.
The percent of total heat dissipated through the top surface
versus through the J-lead is entirely dependent on the
particular mechanical and thermal environment. The heat
dissipated through the top surface is typically 60%. The heat
dissipated through the J-lead onto the PCB board surface is
typically 40%. Use 100% top surface dissipation when
designing for a conservative cooling solution.
It is not recommended to use a V• I Chip for an extended
period of time at full load without proper heatsinking.
9.0 FUSE SELECTION
In order to provide flexibility in configuring power systems
V• I Chip products are not internally fused. Input line fusing of
V• I Chip products is recommended at system level to provide
thermal protection in case of catastrophic failure.
The fuse shall be selected by closely matching system
requirements with the following characteristics:
• Current rating (usually greater than maximum VTM current)
• Maximum voltage rating (usually greater than the maximum
possible input voltage)
• Ambient temperature
• Nominal melting I2t
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1
7/2009
Page 9 of 18
v i c o r p o w e r. c o m
v i c o r p o w e r. c o m
PC
CIN
1000 pF
2.5 V
PC Pull-Up
& Source
-VIN
VC
+VIN
100 A
150 K
1.5 K
5V
2 mA
2.5 V
Enable
10.5 V
18 V
Regulator
Supply
Enable
VIN
OVLO
UVLO
Adaptive
Soft Start
Enable
Modulator
Enable
Fault Logic
Gate Drive
Supply
Primary
Gate
Drive
Cr
VREF
(127°C)
Over
Temperature
Protection
Overcurrent
Protection
VREF
VREF
Lr
Primary Stage &
Resonant Tank
Single Ended
Primary
Current Sensing
Q2
Q1
Temperature
Dependent
Voltage Source
Secondary
Gate Drive
Power
Transformer
Slow Current
Limit
Fast
Current
Limit
C2
C1
Q3
40 K
1K
Q4
0.01 F
3 VMAX
240 AMAX
Synchronous
Rectification
TM
IM
Right
J-lead
-VOUT
COUT
+VOUT
+VOUT
COUT
-VOUT
Left
J-lead
VIV0007TFJ
PRELIMINARY DATASHEET
10.0 VTM BLOCK DIAGRAM
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1
7/2009
Page 10 of 18
VIV0007TFJ
PRELIMINARY DATASHEET
11.0 SINE AMPLITUDE CONVERTER POINT OF LOAD CONVERSION
The Sine Amplitude Converter (SAC) uses a high frequency
resonant tank to move energy from input to output. The
resonant tank formed by Cr and leakage inductance Lr in the
power transformer windings as shown in the VTM Block
Diagram (See Section 10). The resonant LC tank, operated at
high frequency, is amplitude modulated as function of input
voltage and output current. A small amount of capacitance
embedded in the input and output stages of the module is
sufficient for full functionality and is key to achieving power
density.
The VIV0007TFJ SAC can be simplified into the following
model:
122 pH
OUT
IIOUT
LLININ==3.7
nH
5 nH
ROUT
R
OUT
+
1.01 mΩ
R
RCIN
CIN
6.3 mΩ
VININ
V
LOUT = 150 pH
CCININ
V• I
1/32 • IOUT
+
+
–
900 nF
IIQQ
0.09 A
RCOUT
R
COUT
98 mΩ
+
58 µΩ
1/32 • VIN
CCOUT
OUT
360 µF
VOUT
V
OUT
–
K
–
–
Figure 17 – V•I Chip AC model
At no load:
VOUT = VIN • K
(1)
IQ = 0 A, Eq. (3) now becomes Eq. (2) and is essentially load
independent. A resistor R is now placed in series with VIN as
shown in Figure 18.
K represents the “turns ratio” of the SAC.
Rearranging Eq (1):
R
V
K = OUT
VIN
(2)
VVin
IN
+
–
SAC
SAC
= 1/32
1/32
KK =
Vout
V
OUT
In the presence of load, VOUT is represented by:
VOUT = VIN • K – IOUT • ROUT
(3)
The relationship between VIN and VOUT becomes:
and IOUT is represented by:
IOUT =
IIN – IQ
K
Figure 18 – K = 1/32 Sine Amplitude Converter with series
input resistor
(4)
ROUT represents the impedance of the SAC, and is a function of
the RDSON of the input MOSFETs and the winding resistance of
the Power transformer. IQ represents the quiescent current of
the SAC control and gate drive circuitry.
The use of DC voltage transformation provides additional
interesting attributes. Assuming for the moment that ROUT and
VOUT = (VIN – IIN • R) • K
(5)
Substituting the simplified version of Eq. (4)
(IQ is assumed = 0 A) into Eq. (5) yields:
VOUT = VIN • K – IOUT • R • K2
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
(6)
Rev. 1.1
7/2009
Page 11 of 18
v i c o r p o w e r. c o m
VIV0007TFJ
This is similar in form to Eq. (3), where ROUT is used to
represent the characteristic impedance of the SAC. However, in
this case a real R on the input side of the SAC is effectively
scaled by K2 with respect to the output.
Assuming that R = 1 Ω, the effective R as seen from the secondary
side is 0.98 mΩ, with K = 1/32 as shown in Figure 18.
A similar exercise should be performed with the additon of a
capacitor, or shunt impedance, at the input to the SAC. A
switch in series with VIN is added to the circuit. This is depicted
in Figure 19.
S
VVin
IN
+
–
C
SAC
SAC
K = 1/32
K = 1/32
VVout
OUT
Figure 19 – Sine Amplitude Converter with input capacitor
A change in VIN with the switch closed would result in a
change in capacitor current according to the following
equation:
IC(t) = C
dVIN
dt
PRELIMINARY DATASHEET
Low impedance is a key requirement for powering a high
current, low voltage load efficiently. A switching regulation
stage should have minimal impedance, while simultaneously
providing appropriate filtering for any switched current. The
use of a SAC between the regulation stage and the point of
load provides a dual benefit, scaling down series impedance
leading back to the source and scaling up shunt capacitance
(or energy storage) as a function of its K factor squared.
However, these benefits are not useful if the series impedance
of the SAC is too high. The impedance of the SAC must be low
well beyond the crossover frequency of the system.
A solution for keeping the impedance of the SAC low involves
switching at a high frequency. This enables magnetic
components to be small since magnetizing currents remain
low. Small magnetics mean small path lengths for turns. Use of
low loss core material at high frequencies reduces core losses
as well.
The two main terms of power loss in the VTM module are:
- No load power dissipation (PNL): defined as the power
used to power up the module with an enabled power
train at no load.
- Resistive loss (ROUT): refers to the power loss across
the VTM modeled as pure resistive impedance.
PDISSIPATED = PNL + PROUT
(7)
(10)
Therefore,
POUT = PIN – PDISSIPATED = PIN – PNL – PROUT
Assume that with the capacitor charged to VIN, the switch is
opened and the capacitor is discharged through the idealized
SAC. In this case,
IC = IOUT • K
(11)
The above relations can be combined to calculate the overall
module efficiency:
(8)
η =
(9)
=
POUT = PIN – PNL – PROUT
PIN
PIN
(12)
Substituting Eq. (1) and (8) into Eq. (7) reveals:
IOUT =
C
K2
•
dVOUT
dt
Writing the equation in terms of the output has yielded a K2
scaling factor for C, this time in the denominator of the
equation. For a K factor less than unity, this results in an
effectively larger capacitance on the output when expressed in
terms of the input. With a K=1/32 as shown in Figure 19,
C=1 µF would effectively appear as C=1024 µF when viewed
from the output.
VIN • IIN – PNL – (IOUT)2 • ROUT
VIN • IIN
= 1–
(
)
PNL + (IOUT)2 • ROUT
VIN • IIN
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1
7/2009
Page 12 of 18
v i c o r p o w e r. c o m
VIV0007TFJ
12.0 INPUT AND OUTPUT FILTER DESIGN
A major advantage of a SAC system versus a conventional
PWM converter is that the former does not require large
functional filters. The resonant LC tank, operated at extreme
high frequency, is amplitude modulated as a function of input
voltage and output current and efficiently transfers charge
through the isolation transformer. A small amount of
capacitance embedded in the input and output stages of the
module is sufficient for full functionality and is key to achieving
high power density.
This paradigm shift requires system design to carefully evaluate
external filters in order to:
1.Guarantee low source impedance.
To take full advantage of the VTM dynamic response, the
impedance presented to its input terminals must be low
from DC to approximately 5 MHz. The connection of the
V•I Chip to its power source should be implemented with
minimal distribution inductance. If the interconnect
inductance exceeds 100 nH, the input should be bypassed
with a RC damper to retain low source impedance and
stable operation. A single electrolytic or equivalent low-Q
capacitor may be used in place of the series RC bypass.
2.Further reduce input and/or output voltage ripple without
sacrificing dynamic response.
Given the wide bandwidth of the VTM, the source
response is generally the limiting factor in the overall
system response. Anomalies in the response of the source
will appear at the output of the VTM multiplied by its
K factor.
3.Protect the module from overvoltage transients imposed
by the system that would exceed maximum ratings and
cause failures.
The V•I Chip input/output voltage ranges shall not be
exceeded. An internal overvoltage lockout function
prevents operation outside of the normal operating input
range. Even during this condition, the powertrain is
exposed to the applied voltage and power MOSFETs must
withstand it. A criterion for protection is the maximum
amount of energy that the input or output switches can
tolerate if avalanched.
PRELIMINARY DATASHEET
13.0 CAPACITIVE FILTERING CONSIDERATIONS
FOR A SINE AMPLITUDE CONVERTER
It is important to consider the impact of adding input and
output capacitance to a Sine Amplitude Converter on the
system as a whole. Both the capacitance value, and the
effective impedance of the capacitor must be considered.
A Sine Amplitude Converter has a DC ROUT value which has
already been discussed in section 11. The AC ROUT of the SAC
contains several terms:
• Resonant tank impedance
• Input lead inductance and internal capacitance
• Output lead inductance and internal capacitance
The values of these terms are shown in the behavioral model in
section 11. It is important to note on which side of the
transformer these impedances appear and how they reflect
across the transformer given the K factor.
The overall AC impedance varies from model to model but for
most models it is dominated by DC ROUT value from DC to
beyond 500 KHz. The behavioral model in section 11 should be
used to approximate the AC impedance of the specific model.
Any capacitors placed at the output of the VTM reflect back to
the input of the VTM by the square of the K factor (Eq. 9) with
the impedance of the VTM appearing in series. It is very
important to keep this in mind when using a PRM to power
the VTM. Most PRMs have a limit on the maximum amount of
capacitance that can be applied to the output. This capacitance
includes both the PRM output capacitance and the VTM
output capacitance reflected back to the input. In PRM remote
sense applications, it is important to consider the reflected
value of VTM output capacitance when designing and
compensating the PRM control loop.
Capacitance placed at the input of the VTM appear to the load
reflected by the K factor, with the impedance of the VTM in
series. In step-down VTM ratios, the effective capacitance is
increased by the K factor. The effective ESR of the capacitor is
decreased by the square of the K factor, but the impedance of
the VTM appears in series. Still, in most step-down VTMs an
electrolytic capacitor placed at the input of the VTM will have a
lower effective impedance compared to an electrolytic
capacitor placed at the output. This is important to consider
when placing capacitors at the output of the VTM. Even
though the capacitor may be placed at the output, the majority
of the AC current will be sourced from the lower impedance,
which in most cases will be the VTM. This should be studied
carefully in any system design using a VTM. In most cases, it
should be clear that electrolytic output capacitors are not
necessary to design a stable, well-bypassed system.
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1
7/2009
Page 13 of 18
v i c o r p o w e r. c o m
VIV0007TFJ
14.0 CURRENT SHARING
The SAC topology bases its performance on efficient transfer
of energy through a transformer without the need of closed
loop control. For this reason, the transfer characteristic can be
approximated by an ideal transformer with some resistive drop
and positive temperature coefficient.
This type of characteristic is close to the impedance
characteristic of a DC power distribution system, both in
behavior (AC dynamic) and absolute value (DC dynamic).
When connected in an array with the same K factor, the VTM
module will inherently share the load current with parallel
units, according to the equivalent impedance divider that the
system implements from the power source to the point of load.
It is important to notice that, when successfully started, VTMs
are capable of bi-directional operation. Reverse power transfer
is enabled if the VTM input falls within its operating range and
the VTM is otherwise enabled. In parallel arrays, because of
ROUT, circulating currents are never experienced due to energy
conservation law.
Some general recommendations to achieve matched array
impedances:
• Dedicate common copper planes within the PCB to
deliver and return the current to the modules.
• Provide the PCB layout as symmetric as possible.
• Apply same input / output filters (if present) to each unit.
For further details see AN:016 Using BCM™ Bus Converters in
High Power Arrays.
PRELIMINARY DATASHEET
15.0 REVERSE INRUSH CURRENT PROTECTION
The VIV0007TFJ provides reverse inrush protection which
prevents reverse current flow until the input voltage is high
enough to first establish current flow in the forward direction.
In the event that there is a DC voltage present on the output
before the VTM is powered up, this feature protects sensitive
loads from excessive dV/dT during power up as shown in
Figure 21.
If a voltage is present at the output of the VTM which satisfies
the condition VOUT > VIN • K after a successful power up the
energy will be transferred from secondary to primary. The input
to output ratio of the VTM will be maintained. The VTM will
continue to operate in reverse as long as the input and output
voltages are within the specified range. The VIV0007TFJ has not
been qualified for continuous reverse operation.
PC
IM
VC
TM
R
R
VTM
VIN
+In
+Out
+
_
-In
A
B
CD
Supply
-Out
E
F
G
H
VC
VIN
Supply
VIN
VIN
ZIN_EQ1
VTM1
ZOUT_EQ1
VOUT
VOUT
RO_1
VOUT
Supply
ZIN_EQ2
VTM2
ZOUT_EQ2
TM
RO_2
+
–
DC
Load
PC
A: VOUT supply > 0 V
ZIN_EQn
VTMn
RO_n
ZOUT_EQn
B: VC to -IN > 11.5 V controller wakes-up, PC & TM pulled
high, reverse inrush protection blocks VOUT supplying VIN
C: VIN supply ramps up
Figure 20 – VTM array
D: VIN > VOUT/K, powertrain starts in normal mode
E: VIN supply ramps down
F: VIN > VOUT/K, powertrain transfers reverse energy
G: VOUT ramps down, VIN follows
H: VC turns off
Figure 21 – Reverse inrush protection
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1
7/2009
Page 14 of 18
v i c o r p o w e r. c o m
VIV0007TFJ
PRELIMINARY DATASHEET
16.0 LAYOUT CONSIDERATIONS
The VIV0007TFJ requires equal current density along the output
J-leads to achieve rated efficiency and output power level. The
negative output J-leads are not connected internally and must
be connected on the board as close to the VTM as possible. The
layout must also prevent the high output current of the
VIV0007TFJ from interfering with the input-referenced signals.
To achieve these requirements, the following layout guidelines
are recommended:
• The total current path length from any point on the V+OUT
J-leads to the corresponding point on the V-OUT J-leads should
be equal (see Figure 22) .
Figure 22 – Equal current path
• Use vias along the negative output J-leads to connect the
negative output to a common power plane.
• Use sufficient copper weight and number of layers to carry
the output current to the load or to the output connectors.
• Be sure to include enough vias along both the positive and
negative J leads to distribute the current among the layers
of the PCB.
• Do not run input-referenced signal traces (VC, PC, TM
and IM) between the layers of the secondary outputs.
• Run the input-referenced signal traces (VC, PC, TM and IM)
such that V-IN shields the signals. See AN:005 FPA Printed
Circuit Board Layout Guidelines for more details.
Figure 23 – Symmetric layout
Equalizing the current paths is most easily accomplished by
centering the VTM output J-leads between the output
connections of the PCB and by designing the board such that
the layout is symmetric from both sides of the output and from
the front and back ends of the output as shown in Figures 23
and 24.
Figure 24 – Symmetric layout
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1
7/2009
Page 15 of 18
v i c o r p o w e r. c o m
VIV0007TFJ
PRELIMINARY DATASHEET
17.0 MECHANICAL DRAWING
17.1 RECOMMENDED LAND PATTERN
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
Bottom View
NOTES:
mm
1. DIMENSIONS ARE inch .
2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
X.XX = ≠±0.25 [0.01]
X.XXX = ≠±0.127 [0.005]
3. RoHS COMPLIANT PER CST-0001 LATEST REVISION.
Signal
Name
+In
–In
IM
TM
VC
PC
+Out
–Out
Designation
M2, M1
M4, M3
N3
N4
N2
N1
A3-L3, A2-L2
A4-L4, A1-L1
DXF and PDF files are available on vicorpower.com
Click here to view original mechanical drawing on the Vicor website.
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1
7/2009
Page 16 of 18
v i c o r p o w e r. c o m
VIV0007TFJ
PRELIMINARY DATASHEET
17.2 RECOMMENDED LAND PATTERN FOR PUSH PIN HEAT SINK
RECOMMENDED LAND PATTERN
(NO GROUNDING CLIPS)
TOP SIDE SHOWN
36.50
1.437
2.95 ± 0.07
ø
0.116 ± 0.003
(2) PL.
DASHED LINE
INDICATES
VIC POSITION
( 18.25 )
0.719
NON-PLATED
THRU HOLE
SEE NOTE 1
7.63
0.300
( 22.26 )
0.876
( 3.50 )
0.138
NOTES:
7.00
0.276
1. MAINTAIN 3.50 [0.138] DIA. KEEP-OUT ZONE
FREE OF COPPER, ALL PCB LAYERS.
2. (A) MINIMUM RECOMMENDED PITCH IS 39.50 [1.555],
THIS PROVIDES 7.00 [0.275] COMPONENT
EDGE-TO-EDGE SPACING, AND 0.50 [0.020]
CLEARANCE BETWEEN VICOR HEAT SINKS.
(B) MINIMUM RECOMMENDED PITCH IS 41.00 [1.614],
THIS PROVIDES 8.50 [0.334] COMPONENT
EDGE-TO-EDGE SPACING, AND 2.00 [0.079]
CLEARANCE BETWEEN VICOR HEAT SINKS.
( 31.48 )
2.51
0.099
1.239
39.50
1.555
SEE NOTE 2A
3. V•I CHIP LAND PATTERN SHOWN FOR REFERENCE ONLY;
ACTUAL LAND PATTERN MAY DIFFER.
DIMENSIONS FROM EDGES OF LAND PATTERN
TO PUSH-PIN HOLES WILL BE THE SAME FOR
ALL FULL SIZE V•ICHIP PRODUCTS.
RECOMMENDED LAND PATTERN
(With GROUNDING CLIPS)
TOP SIDE SHOWN
4. RoHS COMPLIANT PER CST-0001 LATEST REVISION.
38.03
1.497
ø
0.76
0.030
2.95 ± 0.07
0.116 ± 0.003
(2) PL.
( 18.25 )
NON-PLATED
THRU HOLE
SEE NOTE 1
7.63
0.300
( 22.26 )
0.876
ø 2.03
0.080
(2) PL.
PLATED
THRU HOLE
SEE NOTE 6
36.50
1.437
5. UNLESS OTHERWISE SPECIFIED:
DIMENSIONS ARE MM [INCH].
TOLERANCES ARE:
X.X [X.XX] = ±0.3 [0.01]
X.XX [X.XXX] = ±0.13 [0.005]
DASHED LINE
INDICATES
VIC POSITION
0.719
( 3.50 )
6. PLATED THROUGH HOLES FOR GROUNDING CLIPS (33855)
SHOWN FOR REFERENCE. HEATSINK ORIENTATION AND
DEVICE PITCH WILL DICTATE FINAL GROUNDING SOLUTION.
0.44
0.017
0.138
7.00
0.276
6.12
0.241
2.51
0.099
( 31.48 )
1.239
41.00
1.614
SEE NOTE 2B
Click here to view original mechanical drawing on the Vicor website.
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1
7/2009
Page 17 of 18
v i c o r p o w e r. c o m
VIV0007TFJ
PRELIMINARY DATASHEET
Warranty
Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in
normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper
application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to
the original purchaser only.
EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING,
BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
Vicor will repair or replace defective products in accordance with its own best judgement. For service under this
warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping
instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges
incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within
the terms of this warranty.
Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is
assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve
reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or
circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not
recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten
life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes
all risks of such use and indemnifies Vicor against all damages.
Vicor’s comprehensive line of power solutions includes high density AC-DC
and DC-DC modules and accessory components, fully configurable AC-DC
and DC-DC power supplies, and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for
its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or
malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are
available upon request.
Specifications are subject to change without notice.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent
applications) relating to the products described in this data sheet. Interested parties should contact Vicor's
Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Numbers:
5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917;
7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for
use under 6,975,098 and 6,984,965.
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
email
Customer Service: [email protected]
Technical Support: [email protected]
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1
7/2009
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