SiC734CD9 Vishay Siliconix Fast Switching MOSFETs With Integrated Driver FEATURES PRODUCT SUMMARY Input Voltage Range 3.3 to 24 V Output Voltage Range 0.5 to 6 V Operating Frequency 100 kHz to 1 MHz Continuous Output Current • Low-side MOSFET control pin for pre-bias start-up • Undervoltage Lockout for safe operation • Internal boostrap diode reduces component count • Break-Before-Make operation • Turn-on/Turn-off Capability • Compatible with any single or multi-phase PWM controller • Low profile, thermally enhanced PowerPAK® MLF 9 x 9 Package Up to 25 A Peak Efficiency 92.8 Optimized Duty Cycle Ratio 10 % PowerPAK MLF 9 x 9 APPLICATIONS • DC-to-DC Point-of-Load Converters - 3.3 V, 5 V, or 12 V Intermediate BUS - Examples - 12 VIN/0.8 - 2.5 VOUT - 5 VIN/0.8 - 1.5 VOUT • Servers and Computers • Single and Multi-Phase Conversion Bottom View Ordering Information: SiC734CD9-T1 DESCRIPTION The SiC734CD9 is an integrated solution which contains two PWM-optimized MOSFETs (high side and low side MOSFETs) and a driver IC. Integrating the driver allows better optimization of Power MOSFETs. This minimizes the losses and provides better performance at higher frequency. The SiC734CD9 is packed in Vishay Siliconix’s high performance PowerPAK MLF 9 x 9 package. Compact co-packing of components helps to reduce stray inductance, and hence increases efficiency. FUNCTIONAL BLOCK DIAGRAM CBOOT VDD VIN UVLO SHDN + - VDD BBM SW PWM PGND SYNC CGND Figure 1. Document Number: 73672 S-62656–Rev. C, 25-Dec-06 www.vishay.com 1 SiC734CD9 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Symbol Steady State Logic Supply VDD 7 Logic Inputs VPWM 7.3 Common Switch Node VSW 30 Drain Voltage VIN 30 CBOOT SW + 7 PD 6 Tj, Tstg - 65 to 125 Bootstrap Voltage Maximum Power Sissipation (Measured at 25 °C ) Operating Juncyion and Storage Temperature Range a, b V W °C 225 Soldering Recommendations (Peak Temperature) Unit Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Drain Voltage Logic Supply Input Logic PWM Voltage Bootstrap Capacitor Symbol VIN VDD VPWM CBOOT Steady State 3.3 to 24 4.5 to 5.5 5 100 n to 1 µ Unit Unit V F THERMAL RESISTANCE RATINGS Parameterc Maximum Junction-to-Case Maximum Junction-to-Ambient (PCB = Copper 25 mm x 25 mm) Steady State Symbol RthJC Typical 3.5 Maximum 4.5 RthJA 60 75 °C/W Notes: a. See Reliability Manual for profile. The PowerPAK MLF 9 x 9 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot guaranteed and is not required to ensure adequate bottom side soldering interconnection. b. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. c. Junction-to-case thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use in conjunction with the thermal impedance of the PC board pads to ambient (RthJA = RthJC + RthPCB-A). It can also be used to estimate chip temperature if power dissipation and the lead temperature of heat carrying (drain) lead is known. www.vishay.com 2 Document Number: 73672 S-62656–Rev. C, 25-Dec-06 SiC734CD9 Vishay Siliconix SPECIFICATIONS Parameter Symbol Test Conditions Unless Specified TA = 25 °C 4.5 V < VDD < 5.5 V, 4.5 V < VIN < 20 V Limits Min Typa Max Unit 5.5 V Controller VDD Logic Voltage Logic Current (Static) Logic Current (Dynamic) 4.5 IDD(EN) VDD = 4.5 V, SYNC = H, PWM = H, SHDN = H 1185 IDD(DIS) VDD = 4.5 V, SYNC = H, PWM = H, SHDN = L 115 IDD1(DYN) VDD = 5 V, fPWM = 250 kHzc 24 IDD2(DYN) c 52 VDD = 5 V, fPWM = 700 kHz µA mA Logic Input Logic Input (VPWM) High VPWMH Low VPWML VDD = 5 V, SYNC = H, SHDN = H Logic Input Voltage (VSYNC) VSYNC VDD = 5 V, PMW = H, SHDN = H Logic Input Voltage (VSHDN) VSHDN VDD = 5 V, PMW = H, SYNC = H Input Voltage Hysteresis (PWM) 2.5 1.35 2.0 2.0 VHYS 400 ISHDN VDD = 5.5 V, SHDN = 0 V 117 IPWM VDD = 5.5 V, PMW = 5.5 V 114 Break-Before-Make Reference VBBM VDD = 5.5 V Under-Voltage Lockout VUVLO Logic Input Current V mV µA Protection Under-Voltage Lockout Hysteresis VH 2.4 3.5 VDD = 5 V, SYNC = H, SHDN = H 4.1 4.25 V 0.4 MOSFETs Drain-Source Voltage VDS ID = 250 µA Drain-Source On-State rDS(on)1 VDD = 5 V, ID = 10 A Resistancea rDS(on)2 TA = 25 °C Diode Forward Voltagea VSD1 VSD2 IS = 2 A, VGS = 0 V 30 32 V High-Side 9.5 12.3 Low-Side 3.7 4.5 High-Side 0.7 1.1 Low-Side 0.67 1.1 mΩ V Dynamicb, c Turn On Delay Time td(on) Turn Off Delay Time td(off) 58 50 % - 50 %c 31 ns Notes: a. Pulse test; pulse width ≤ 300 ms, duty cycle ≤ 2 %. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. Using application board SiDB766706. Document Number: 73672 S-62656–Rev. C, 25-Dec-06 www.vishay.com 3 SiC734CD9 Vishay Siliconix TIMING DIAGRAM SHDN SYNC PWM HS MOSFET Gate LS MOSFET Gate SW td(on) td(off) Figure 2. APPLICATION INFORMATIONa (25 °C, unless noted, LFM = 0) 96 7 94 6 700 kHz 5 Total Loss (W) Efficiency (%) 92 90 88 300 kHz 86 500 kHz 500 kHz 4 300 kHz 3 2 84 700 kHz 1 82 0 80 3 5 7 9 11 13 15 17 19 21 23 25 3 Output Current – (A) Figure 3. Total Efficiency 12 VIN/1.3 VOUT 5 7 9 11 13 15 17 19 21 23 25 Output Current – (A) Figure 4. Total Loss 12 VIN/1.3 VOUT Notes: a. Experimental results using an evaluation board with a specific set of operating conditions. www.vishay.com 4 Document Number: 73672 S-62656–Rev. C, 25-Dec-06 SiC734CD9 Vishay Siliconix PIN CONFIGURATION VIN VIN 32 31 VIN SW 30 SW 29 SW 28 SW 27 26 25 SW PowerPAK MLF 9 mm x 9 mm (Bottom View) 24 PGND 1 23 PGND Low-Side MOS Tab 22 PGND High-Side MOS Tab VIN 4 VIN 20 PGND 19 PGND CGND 6 CBoot 7 (SW) CBoot 8 17 PGND VIN 5 Driver Tab 18 PGND VIN 3 21 PGND VIN 2 VDD CGND 9 10 11 12 13 14 15 16 VDD VDD PWM SYNC CGND SHDN PGND PGND TRUTH TABLE SHDN SYNC PWM HS MOSFET LS MOSFET L X X OFF OFF H L L OFF OFF H L H ON OFF H H L OFF ON H H H ON OFF PIN DESCRIPTION Pin Number 1 - 4, 30 - 32 5, 12 Symbol VIN Description Input-Voltage (High-Side MOSFET Drain) 6, 7 CGND CBOOT 8, 9, 10 VDD 11 PMW Pulse Width Modulation (PWM) Signal Input 13 SYNC Disable Low-Side MOSFET Drive 14 SHDN Disable All Functions (Active Low) 15 - 24 PGND 25 - 29 SW Document Number: 73672 S-62656–Rev. C, 25-Dec-06 Control Ground. Should be connected to PGND externally Connection pin for Bootstrap Capacitor for High-Side MOSFET Logic Supply Voltage - decoupling to GND with a CAP is strongly recommended Power Ground (Low-Side MOSFET Source) Connection Pin for Output Inductor (High-Side MOSFET Source/Low-Side MOSFET Drain) www.vishay.com 5 SiC734CD9 Vishay Siliconix DEVICE OPERATION Pulse Width Modulator (PWM) This is a CMOS compatible logic input that receives the drive signals from the controller circuit. The PWM signal drives the buck switch. Break-Before-Make (BBM) The SiC730CD9 has an intrenal break-before-make function to ensure that both high-side and low-side MOSFETs are not turned on the same time. The low-side MOSFET will not turn on until the high-side gate drive voltage is less than VBBM, thus ensuring that the high-side MOSFET is turned off. This parameter is not user adjustable. SHDN CMOS logic signal. In the low state, the SHDN disables both high-side and low-side MOSFET’s. Capacitor to Boot Input (CBOOT) Connected to VDD by an internal diode via the CBOOT pin, the boot capacitor is used to sustain rail for the high-side MOSFET gate drive circuit. Under Voltage Lockout (UVLO) During the start up cycle, the UVLO disables the gate drive holding high-side and low-side MOSFET’s low until the input voltage rail has reached a point at which the logic circuitry can be safely activated. The UVLO is not user adjustable. SYNC Pin for Pre-Bias Start-Up The low side MOSFET can be individually enable or disabled by using the SYNC pin. In the low state (SYNC = low), the low-side MOSFET is turned off. In the high state, the low-side MOSFET is enabled and follows the PWM input signal (see timing diagram, Figure 2). SYNC is a CMOS compatible logic input and is used for a pre–biased output voltage. Voltage Input (VIN) This is the power input to the drain of the high-side Power MOSFET. This pin is connected to the high power intermediate BUS rail. Switch Node (SW) The Switch node is the circuit PWM regulated output. This is the output applied to the filter circuit to deliver the regulated high output for the buck converter. Power Ground (PGND) This is the output connection from the source of the low-side MOSFET. This output is the ground return loop for the power rail. It should be externally connected to CGND. Control Ground (CGND) This is the control voltage return path for the driver and logic input circuitry to the SiC730CD9. This should externally connected to PGND. APPLICATION CIRCUIT 3.3 V to 16 V Power Up Sequence: The presence of VDD prior to applying the VIN and PWM is recommended to ensure a safe turn on Power Down Sequence: The sequence should be reverse of the on sequence, turn off the VIN before turning off the VDD. CBOOT VDD 5V VIN HS SYNC DC-DC Controller PWM MOSFET Drive Circuitry with Break-BeforeMake SW CGND CBOOT L VOUT + LS SHDN Q1 Q2 PGND PGND CGND Figure 7 The SiC714CD10 has a built-in delay time that is optimized for the MOSFET pair. When the PWM signal goes low, the high-side driver will turn off, after circuit delay (tdoff), and the output will start to ramp down,(t f ). After a further delay, the low-side driver turns on. The SiC734CD9 has a built-in delay time that is optimized for the MOSFET pair. When the PWM signal goes low, the highside driver will turn off, after circuit delay (tdoff), and the output will start to ramp down, (tf). After a further delay, the lowside driver turns on. www.vishay.com 6 When the PWM goes high, the low-side driver turns off,(t don). As the body diode starts to conduct, the high-side MOSFET turns on after a short delay . The delay is minimized to limit body diode conduction. The output then ramps up,(tr). When the PWM goes high, the low-side driver turns off, (tdon). As the body diode starts to conduct, the high-side MOSFET turns on after a short dalay. The delay is minimized to limit body diode conduction. The output then ramps up, (tr). Document Number: 73672 S-62656–Rev. C, 25-Dec-06 SiC734CD9 Vishay Siliconix TYPICAL APPLICATION 12 V 5V VDD VIN CBOOT SYNC SHDN SiC734CD9 PWM SW PGND CGND VDD VIN CBOOT SYNC PWM Control Circuit PWM1 SHDN PWM2 PWM PWM3 CGND SiC734CD9 SW PGND PWM4 VOUT VDD VIN CBOOT SYNC SHDN SiC734CD9 PWM SW PGND CGND VDD VIN CBOOT SYNC SHDN SiC734CD9 PWM SW PGND CGND Figure 8. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?73672. Document Number: 73672 S-62656–Rev. C, 25-Dec-06 www.vishay.com 7 Package Information Vishay Siliconix 9 0.10 C A D 0.08 C A D/2 1 2 3 0.10 M C A B D2 4 D3 D2/2 P 0.45 Pin 1 ID 0.20 R. N 1 2 3 E4 E2/2 E E1 E2 E/2 6 0.80 DIA E1/2 5 0.10 C B P D6 A3 2x D1/2 N A1 A2 D1 4 b 0.25 min (Ne−1)Xe Ref. A 4 10 2x E3 PowerPAKr MLF 9 2x 0.10 C B B 2x q 0.10 C A C Top View e L Seating Plane D5 0.25 min Side View D4 (Nd−1)Xe Ref. Bottom View CC CL CL e 4 e Terminal Tip Odd Terminal Side b A1 11 Section “C−C” Scale: None Even Terminal Side NOTES: 1. Die thickness allowable is 0.305-maximum (0.12-inches maximum) 2. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 3. N is the total number of terminals. Nd is the number of terminals in the X-direction and Ne is the number of terminals in the Y-direction. 4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. 5. The pin #1 identifier must exist on the top surface of the package. The identifier may be an indentation mark or other feature of the package body. 6. Exact shape and size of this feature is optional. 7. Millimeters will govern. 8. The shape shown on four corners are not actual I/O. 9. Package warpage maximum is 0.08 mm. 10. Applied for exposed pad and terminals exclude embedding part of exposed pad from measuring. 11. Applied only for terminals. Document Number: 73386 02-May-05 www.vishay.com 1 of 2 Package Information Vishay Siliconix PowerPAKr MLF 9 9 EXPOSED PAD VARIATIONS (Millimeters) D2 E2 D3 E3 Min Nom Max Min Nom Max Min Nom Max Min Nom Max 6.95 7.10 7.25 6.95 7.10 7.25 2.15 2.30 2.45 3.55 3.70 3.85 D4 E4 D5 D6 Min Nom Max Min Nom Max Min Nom Max Min Nom Max 2.75 2.90 3.05 2.85 3.00 3.15 3.65 3.80 3.95 4.25 4.40 4.55 EXPOSED PAD VARIATIONS (Inches) D2 E2 D3 E3 Min Nom Max Min Nom Max Min Nom Max Min Nom Max 0.274 0.280 0.285 0.274 0.280 0.285 0.085 0.091 0.096 0.140 0.146 0.152 Min Nom Max Min Nom Max Min Nom Max Min Nom Max 0.108 0.114 0.120 0.112 0.118 0.124 0.144 0.150 0.155 0.167 0.173 0.179 D4 E4 D5 D6 DIMENSIONS MILLIMETERS* Dim Min A A1 A2 A3 b D D1 e — 0.00 — Nom 0.85 0.01 0.65 0.20 REF 0.25 0.30 9.00 BSC 8.75 BSC 0.80 BSC E 9.00 BSC E1 8.75 BSC L 0.50 0.60 N 32 Nd 8 Ne 8 P 0.24 0.42 q — — * Use millimeters as the primary measurement. INCHES Max Min Nom Max NOTE 0.90 0.05 0.80 — 0.000 — 0.035 0.002 0.031 11 0.35 0.010 0.014 4 0.75 0.020 0.033 — 0.026 0.008 REF 0.012 0.354 BSC 0.344 BSC 0.031 BSC 0.354 BSC 0.344 BSC 0.024 32 8 8 0.017 — 0.60 12_ 0.009 — 0.030 3 3 3 0.024 12_ ECN: T-05143—Rev. A, 02-May-05 DWG: 5948 www.vishay.com 2 Document Number: 73386 02-May-05 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein. Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1