CMX649 CML Microcircuits ADM Codec COMMUNICATION SEMICONDUCTORS D/649/2 May 2003 Provisional Issue Features • • • Multiple Codec Modes, 16 to 128 kbps - Full duplex ADM and CVSD - Full duplex PCM: µ-law, A-law, Linear - Configurable ADM time constants - Dual channel transcoder/decoder mode High Performance Digital Architecture Low Power: 2.5mA at 3.0V typ. 2.7V - 5.5V Supply Data Clock Recovery Programmable Voice Activity Detector (VAD) - Adjust threshold level and attack/decay time - Use to powersave on low signal level - Silence/blank low level signals Programmable Digital Scrambler Flexible Interfaces - 8-bit and 16-bit burst data with sync strobe - 1 bit serial data with clock - Host serial control/data interface • • • • • • • XTAL/ Clock XTAL Osc Clock Gen • • Internal and External Sample Clocking Programmable Filters - Encoder mic input ADC anti-alias - Decoder audio out DAC anti-imaging Low Noise Differential Mic Input Amp Programmable Analog Interface Gain - Microphone in - Decoder audio out - Sidetone path Applications • • • • • • • • Low Cost Digital Cordless Headset Personal Area Network (PAN) Voice Link Digital Cordless Telephone Wireless Digital PBX Full Duplex Digital Radio Systems Time Division Duplex (TDD) Systems Portable Digital Voice Communicator Digital Voice Delay Data & Sample Clocks ENCODER PCM Tx VAD Transcode Buffer Scramble Analog Input Analog Output TX data ADM MIC AMP Transcoded Data & Status sidetone ADM Rx VAD Transcode Buffer + PCM Descramble Data & Sample Clocks Serial I/O serial control & data Data & Clock Recovery Control RX data DECODER 1. Brief Description The CMX649 Adaptive Delta Modulation (ADM) Voice Codec provides full duplex ADM, companded (µ/A-law) PCM and linear PCM codec and transcoder functions for cost effecive, low power, wireless voice applications. Selectable modes and algorithms support many applications. Robust ADM coding (e.g. CVSD) reduces host protocol and software burdens, eliminating forward error correction, framing protocols and algorithm processing. Dual transcode/decode mode supports multichannel applications. Integrated filter responses adjust independent of 16kbps to 128kbps codec data rates. Codec sample clocks are externally applied or internally generated. High performance analog interfaces and sidetone include digital gain controls. Encoder and decoder voice activity detectors support powersaving. The CMX649 ADM Voice Codec supports 2.7V to 5.5V operation and is available in 20-pin SOIC (D3) and TSSOP packages (E3) packages. 2003 CML Microsystems Plc ADM Codec CMX649 CONTENTS Section Page 1. Brief Description.................................................................................. 1 2. Block Diagram ..................................................................................... 3 3. Signal List ............................................................................................ 4 4. External Components.......................................................................... 5 5. General Description............................................................................. 6 5.1 Block Descriptions.................................................................. 6 5.1.1 ADM Coding Engine ................................................... 6 5.1.2 PCM Encoding and Decoding.................................... 7 5.1.3 Transcoding with the Encoder and Decoder ............ 8 5.1.4 Non-Linear Instantaneous Companding ................... 9 5.1.5 Digitally Controlled Amplifiers................................... 9 5.1.6 Microphone Amplifier................................................. 9 5.1.7 Programmable Anti-alias/image SC Filters ............... 9 5.1.8 Data Clock Recovery ................................................ 11 5.1.9 Data Scrambler/De-scrambler .................................. 11 5.1.10 Voice Activity Detector (VAD) .................................. 12 5.2 C-BUS Description ................................................................ 13 5.2.1 Write Only Register Description .............................. 16 5.2.2 Read Only Register Description .............................. 35 6. Application Notes .............................................................................. 37 6.1 C-BUS Operation................................................................... 37 6.2 CODEC Data Interface........................................................... 38 6.3 Example CODEC Setups and Application Help................... 39 7. Performance Specification................................................................ 44 7.1 Electrical Performance.......................................................... 44 7.2 Packaging.............................................................................. 49 2003 CML Microsystems Plc 2 D/649/2 + VREF AAF/AIF BW REG $61 AUDIO LEVEL REG $63 ANALOG POWER CONTROL REGS $64 & $65 + + - VAD $E2 & $E4 PCM OUTPUT REG $E6 STATUS REG $80 + ENCODER FEEDBACK IRQ CTL REG $81 1st ADM CTL REG $E1 OFFSET NULLING REGS $E3 & $E5 ENCODE SETUP REG $E0 2nd ESTIMATOR INTEGRATORS LINEAR PCM OUT LINEAR TO µ/A LAW MODE REG $70 ADM CTL REG $D1 x x ADM INPUT REG $E8 DELAY REGISTER PROGRAMMABLE STEP SIZE CONTROL Q ADM OUTPUT REG $EA 0 1 ADM OUT 1 0 CLOCK SOURCE CONTROL REG $73 PROGRAMMABLE SCRAMBLER REG $71 ADM OUTPUT REG $DA ADM INPUT REG $D8 D CLOCK RECOVERY ENCODE & DECODE BIT CLKS DIVIDERS OSCILLATOR DATA OUT BUFFER BIT PRESCALER DELAY REGISTER PROGRAMMABLE STEP SIZE CONTROL ADM IN PROGRAMMABLE DE-SCRAMBLER REG $71 CLOCK DIVIDER CONTROL REG $72 DATA IN BUFFER µ/A LAW TO LINEAR LINEAR PCM IN DECODE SETUP REG $D0 2nd ESTIMATOR INTEGRATORS 1st PCM TO ADM TRANSCODE FEEDBACK PCM INPUT REG $E7 PCM INPUT REG $D7 + PCM OUTPUT REG $D6 + OFFSET NULLING REGS $D3 & $D5 PCM TO ADM TRANSCODE FEEDBACK 3 Figure 1 Block Diagram VAD $D2 & $D4 + CBUS CONTROL INTERFACE SIDETONE AUDIO FILTER CLOCK DIVIDER AUDIO FILTER PRESCALER DIVIDER PROGRAMMABLE ANTI-ALIAS FILTER Block Diagram ADM Codec 2. MIC - MIC OUT MIC + VDD VSS VBIAS SCK CMD CSN IRQN VOL & SIDETONE REG $62 PROGRAMMABLE ANTI-IMAGE FILTER + RPLY AUDIO OUT 2003 CML Microsystems Plc + CMX649 ENC VAD TX DATA XTAL/CLOCK TX CLK STROBE RX CLK/BURST CLK RX DATA DEC VAD D/649/2 ADM Codec 3. CMX649 Signal List SOIC (D3) Package TSSOP (E3) Package Pin No. Pin No. Name Type 1 1 STRB Digital Input 2 2 ENC VAD Digital Output 3 3 VDD Power 4 4 MIC OUT Analog Output 5 5 MIC + Analog Input Analog non-inverting input to microphone amplifier. 6 6 MIC - Analog Input Analog inverting input to microphone amplifier. 7 7 VBIAS Analog Output 8 8 AUDIO OUT Analog Output VDD/2 – Not suitable for external applications without buffering. Pin should be decoupled to VSS with a capacitor (>1µF). Analog Output signal from decoder. 9 9 VSS Power 10 10 DEC VAD Digital Output 11 11 RX DATA Digital Input 12 12 RX CLK Digital I/O 13 13 XTAL/CLK Analog Input 4 – 16 MHz crystal oscillator input. 14 14 IRQN Digital Output ) 15 15 RPLY Digital Output ) 16 16 CMD Digital Input ) C-BUS control signals. 17 17 SCLK Digital Input ) 18 18 CSN Digital Input ) 19 19 TX CLK Digital I/O 20 20 TX DATA Digital Output Notes: I/O NC = = 2003 CML Microsystems Plc Signal Description Strobe signal for 8/16 buffered serial I/O. Encoder voice activity detector output. Positive supply rail. Analog output signal from microphone amplifier. Negative supply rail (Ground). Decoder voice activity detector output. Received signal serial data input. Decoder data clock. Clock signal for encoded data out. Encoded data output. Input/Output No Connection 4 D/649/2 ADM Codec 4. CMX649 External Components STRB ENCODE VAD 1 20 2 19 3 18 4 17 5 16 TX CLK VDD C1 MIC OUT C2 C6 R2 R1 MIC C4 R4 R3 MIC+ MIC- C3 VBIAS CSN SCLK CMD CMX649E3 6 15 7 14 8 13 C5 VSS 9 12 DECODE VAD 10 11 RPLY µC INTERFACE IRQN AUDIO OUT C7 TX DATA XTAL/CLK X1 RX CLK RX DATA Figure 2 Recommended External Components R1, R2 R3, R4 C1, C3 C2, C4 Note 1 Note 1 Note 1 Note 1 100kΩ 100kΩ 100 pF 0.01µF ±10% ±10% ±20% ±20% C5 C6 C7 X1 Note 2 Note 3 Note 4 Note 5 33.0µF 1.0µF 1.0µF 4.096MHz ±20% ±20% ±20% Notes: 1. C1 - C4 and R1 - R4 set the microphone amplifier gain and frequency response. The values shown set the gain to unity and the low and high –3 dB frequency rolloff points to approximately 150Hz and 15kHz respectively. 2. DC blocking capacitor for driving a speaker from an external speaker amplifier. The value shown is based on a 32Ω impedance speaker where the highpass rolloff frequency is set to approximately 150Hz. 3. VDD decoupling capacitor. 4. Bias decoupling capacitor. 5. A 4.096MHz Xtal/Clock input will yield exactly 16kbps/32kbps/64kbps internally generated data clock rates. 6. To achieve good noise performance, VDD and VBIAS decoupling and protection of the signal path from extraneous in-band signals are very important. It is recommended that the printed circuit board is laid out with a ground plane in the CMX649 area to provide a low impedance connection between the VSS pin and the VDD and VBIAS decoupling capacitors. 2003 CML Microsystems Plc 5 D/649/2 ADM Codec 5. CMX649 General Description The CMX649 encodes and decodes analog audio signals to/from ADM, Linear PCM, µ-law PCM or A-law PCM. It has programmable clock dividers that enable it to use a range of 4-16 MHz crystal clocks and to sample the data over a large range of data rates. Programmable current sources for on-chip op-amps enable the overall power consumption to be optimised for any given supply voltage and clocking scheme, thus achieving extremely low working power levels. Anti-Alias Image filters and gain controls are fully programmable. All the time constants and other parameters of the ADM can be programmed for optimum performance. The CMX649 also includes a Microphone Amplifier, Data Clock Recovery, Data Scrambler/De-Scrambler and Voice Activity Detector (VAD) circuits. All of these parameters are controlled via C-BUS. 5.1 Block Descriptions The CMX649 contains a full duplex speech codec supporting common Adaptive Delta Modulation (ADM) and non-linear PCM coding algorithms. In addition, it supports linear PCM coding for DSP interface applications. This codec offers simple interface and application, yet is configurable to support a wide variety of speech quantisation systems. 5.1.1 ADM Coding Engine ADM is a differential waveform coding technique predominantly applied to speech. Figure 3 illustrates the ADM encoder employed. The device is for speech quantising applications and is based on popular Continuously Variable Slope Delta (CVSD) encoder approaches, with optional modifications and improvements configurable through the ENCODE and DECODE ADM CONTROL Registers ($E1 and $D1). Optional second order integration in the feedback loop provides improved speech quality at a given bit rate or similar quality at a lower bit rate. Toll quality is achieved at bit rates much lower than for PCM. The decoder is embedded in the encoder, as is the case with most differential encoders. Note the symmetry between the encoder and decoder of Figures 3 and 4 respectively. The signal flows for ADM are shown in bold. INPUT + ENCODER FEEDBACK PCM TO ADM TRANSCODE FEEDBACK ADM INPUT REG $E8 OFFSET NULLING REGS $E3 & $E5 ADM OUT + + ENCODE SETUP REG $E0 1st ADM CTL REG $E1 2nd DELAY REGISTER + x ADM OUTPUT REG $EA PROGRAMMABLE STEP SIZE CONTROL ESTIMATOR INTEGRATORS PCM OUTPUT REG $E6 LINEAR PCM IN PCM INPUT REG $E7 LINEAR PCM OUT Figure 3 ADM Encoding 2003 CML Microsystems Plc 6 D/649/2 ADM Codec CMX649 PCM INPUT REG $D7 LINEAR PCM IN PCM OUTPUT REG $D6 ADM IN ESTIMATOR INTEGRATORS 2nd + 1st + DECODE SETUP REG $D0 + DECODER OUT PROGRAMMABLE STEP SIZE CONTROL x ADM CTL REG $D1 DELAY REGISTER ADM INPUT REG $D8 ADM OUTPUT REG $DA OFFSET NULLING REGS $D3 & $D5 PCM TO ADM TRANSCODE FEEDBACK Figure 4 ADM Decoding The estimator integrators (principal and second) as well as the step size decay (companding integrator) have programmable time constants. Additionally, the minimum and maximum step height and the depth of the delay register are programmable via preset values in the DECODE and ENCODE ADM CONTROL Registers ($D1 and $E1) to support a wide variety of different ADM algorithms including CVSD of Bluetooth™ version 1.1. The switches in Figures 3 and 4 are controlled by the ENCODER and DECODER MODE and SETUP Registers ($E0 and $D0). Various signal flows are possible to allow standard ADM and PCM encoding and decoding as well as transcoding either direction between ADM and PCM (e.g. Figures 7 and 8). Additionally, several summing options are possible. In the decoder a PCM and ADM input stream may be summed – note that this requires at least one of the streams to be input via C-BUS. In the encoder a PCM input stream may be summed with the ADM estimate causing the encoded ADM bit stream to represent the sum of the analog input and linear PCM stream input over CBUS. 5.1.2 PCM Encoding and Decoding + ENCODER FEEDBACK PCM TO ADM TRANSCODE FEEDBACK ADM INPUT REG $E8 OFFSET NULLING REGS $E3 & $E5 ADM OUT + + ENCODE SETUP REG $E0 ADM CTL REG $E1 1st 2nd DELAY REGISTER + x ADM OUTPUT REG $EA PROGRAMMABLE STEP SIZE CONTROL ESTIMATOR INTEGRATORS PCM OUTPUT REG $E6 LINEAR PCM IN PCM INPUT REG $E7 LINEAR PCM OUT Figure 5 PCM Encoding The output of the first or principal estimator integrator in Figures 3 and 4 is linear PCM. By decimating and filtering this signal it is possible to obtain a linear PCM representation, as shown in Figures 5 and 6. Employing either 8:1 or 4:1 decimation filters provides about 30dB attenuation of out of band quantisation noise prior to decimation. The ADM coding engine, which suppresses out of band noise by roughly 20dB, provides (in conjunction with the decimating filter) an overall out of band suppression of approximately 50dB. Using second order ADM at 64kbps with the 8:1 decimation filter provides better than toll quality linear speech samples. Accordingly, 8k samples/sec linear PCM encoder performance can be enhanced when the ADM codec second order integrator is enabled and the ADM codec is operated at the maximum rate. Decoding PCM simply requires interpolation and filtering to compensate for sin(x)/x roll-off of zero holding the PCM samples. The interpolation ratio can be programmed to 4 or 8. 2003 CML Microsystems Plc 7 D/649/2 ADM Codec CMX649 PCM INPUT REG $D7 LINEAR PCM IN PCM OUTPUT REG $D6 ADM IN ESTIMATOR INTEGRATORS 2nd + 1st + DECODE SETUP REG $D0 + DECODER OUT PROGRAMMABLE STEP SIZE CONTROL x ADM CTL REG $D1 DELAY REGISTER ADM INPUT REG $D8 ADM OUTPUT REG $DA OFFSET NULLING REGS $D3 & $D5 PCM TO ADM TRANSCODE FEEDBACK Figure 6 PCM Decoding 5.1.3 Transcoding with the Encoder and Decoder INPUT + ENCODER FEEDBACK PCM TO ADM TRANSCODE FEEDBACK ADM INPUT REG $E8 OFFSET NULLING REGS $E3 & $E5 ADM OUT + + ENCODE SETUP REG $E0 1st ADM CTL REG $E1 DELAY REGISTER x 2nd ADM OUTPUT REG $EA + PROGRAMMABLE STEP SIZE CONTROL ESTIMATOR INTEGRATORS PCM OUTPUT REG $E6 LINEAR PCM IN PCM INPUT REG $E7 LINEAR PCM OUT Figure 7 PCM to ADM transcoding with Encoder (note that the decoder also can be configured to do this function and in this example all data is read and written via C-BUS registers $EA ($DA) and $E7 ($D7) respectively (for decoder)) PCM INPUT REG $D7 LINEAR PCM IN PCM OUTPUT REG $D6 ADM IN ESTIMATOR INTEGRATORS 2nd + + 1st + DECODER OUT x DECODE SETUP REG $D0 ADM CTL REG $D1 PROGRAMMABLE STEP SIZE CONTROL DELAY REGISTER ADM INPUT REG $D8 ADM OUTPUT REG $DA OFFSET NULLING REGS $D3 & $D5 PCM TO ADM TRANSCODE FEEDBACK Figure 8 ADM to PCM transcoding with Decoder (note that the encoder can also be configured to do this function and in this example all data is read and written via C-BUS registers $D6 ($E6) and $D8 ($E8) respectively (for encoder)) 2003 CML Microsystems Plc 8 D/649/2 ADM Codec CMX649 5.1.4 Non-Linear Instantaneous Companding When using the device over its standard PCM codec style interface, instantaneous companding can be enabled to cut in half the PCM word size. Either µ-law or A-law type companding algorithms are provided and use 16-chord piecewise linear approximations. Essentially the companded 8-bit PCM word is a simple floating-point representation with a sign bit, a 3-bit exponent and a 4-bit mantissa. This approach yields toll quality speech at reduced data rates. 5.1.5 Digitally Controlled Amplifiers There are three Digitally Controlled Amplifiers (DCA) on-chip, which are used to set the signal levels for transmit-audio-in, side-tone-audio, and receive-audio-out (volume control). The transmit-audio DCA is adjustable in 0.5dB steps over a +7.5dB to –7.5dB range. The side-tone DCA is adjustable in 6.0dB steps over a 0dB to –21.0dB range. Side-tone audio is added to the audio output signal via an operational amplifier configured as a summing amplifier. This feeds the receive-audio DCA, which is adjustable in 1.5dB steps over a +12.0dB to –33.0dB range. 5.1.6 Microphone Amplifier The input amplifier is a high gain low-noise operational amplifier capable of interfacing with a variety of different microphones. Figure 9 is a simplified schematic showing the external components required for typical application with an electret condenser microphone. Typical values for R1, R3, C1 and C3 should be set according to microphone sensitivity requirements, those shown are for unity gain. Note also that the microphone biasing resistors (R5 and R6) are microphone specification dependent. VDD MIC OUT R5 C2 C1 R1 MIC - R2 R4 R6 C4 + R3 MIC + C3 20k C6 BIAS C7 20k VSS Figure 9 Electret Microphone - Input Amplifier Schematic R1, R3 R2, R4 C1, C3 C2, C4 100kΩ ±10% 100kΩ 100 pF ±10% ±20% 0.01µF ±20% R5 R6 C6 C7 100kΩ ±10% 100kΩ 1.0µF ±10% ±20% 1.0µF ±20% 5.1.7 Programmable Anti-alias/image SC Filters The anti-aliasing (AAF) and anti-imaging (AIF) switched capacitor (SC) filters have a programmable cutoff frequency to accommodate different input signal bandwidths. Typically, the audio filter bandwidth 2003 CML Microsystems Plc 9 D/649/2 ADM Codec CMX649 should be programmed to be 1/10th of the ADM bit rate (or lower) for “toll” (or better) quality audio reconstruction. For “communications” quality, the audio bandwidth may approach 1/6th of the ADM bit rate for ADM rates below 20kbps. The anti-alias/image SC filter bandwidth is programmed directly via CBUS commands to the AAF/AIF BANDWIDTH Register ($61). Additionally, the switched capacitor clock frequency can be altered via C-BUS commands to the CLK DIVIDER CONTROL Register ($72). Typically, the CLK DIVIDER CONTROL Register should be programmed to provide a 256kHz SC filter clock. Altering the SC filter clock from the recommended 256kHz frequency proportionally scales the frequency axis in the plot below: 20 0 -20 -40 Gain (dB) -60 B W = 14 . 0 k H z B W = 10 . 0 k H z BW=7.0kHz -80 BW=5.0kHz BW=3.7kHz BW=2.9kHz -100 -120 -140 -160 -180 1,000 10,000 100,000 Frequency (Hz) Figure 10a Typical Anti-Alias/Image Filter Frequency Response 2003 CML Microsystems Plc 10 D/649/2 ADM Codec CMX649 20 0 -20 -40 B W = 14 . 0 k H z Gain (dB) -60 B W = 10 . 0 k H z BW=7.0kHz BW=5.0kHz -80 BW=3.7kHz BW=2.9kHz -100 HPF -120 -140 -160 -180 10 100 1,000 10,000 100,000 Frequency (Hz) Figure 10b Typical Anti-Image Filter Frequency Response 5.1.8 Data Clock Recovery Data from the RX DATA pin is driven into a comparator to remove amplitude variations. The output of the comparator is a logic signal that can be inverted by setting the appropriate control bit in the SCRAMBLER CONTROL Register ($71). Using the output of the comparator, the clock recovery block can be enabled to generate a phase-locked clock equal to the CVSD data rate, which is used to clock data from the RX DATA pin into the decoder. The recovered clock frequency is controlled by the CLK DIVIDER CONTROL Register ($72). If the clock recovery block is bypassed, data must then be applied which is synchronised to the clock on the RX CLK pin (either internally generated or externally applied). External ADM rate bit clocks can be used for both the encoder and decoder paths and do not require use of the clock recovery PLL. Externally applied clocks act directly as the ADM sample clocks and should be generated with little jitter for best performance. Please note that the maximum usable frequency of th externally applied bit clocks is 1/60 of the frequency of the output of the internal bit clock prescaler. The clock recovery circuit is normally applied to the decoder. However, it is possible to use the recovered clock for the encoder section as well. This supports systems where the base unit is using an internal clock or local external clock for transmit and clock recovery for the decoder clock. The remote unit can then be configured to use the recovered clock for both encode and decode. Internal data clocks for the encoder and decoder can also be selected for data input and output control. 5.1.9 Data Scrambler/De-scrambler The scrambler receives digital data from the encoder. It is implemented with a 10-bit programmable linear feedback shift register (LFSR) allowing a choice of various maximal length scrambling codes. The scrambler, also known as a randomizer, provides not only a level of communication security, but may also help reduce the occurrence of abnormally long strings of 1s or 0s. 2003 CML Microsystems Plc 11 D/649/2 ADM Codec CMX649 The de-scrambler receives the scrambled data from the data slicer and de-scrambles it to the original data as long as the selected LFSR maximal length sequence is the same as that in the transmitting scrambler. The de-scrambler block has the same configuration as the scrambler and is selfsynchronizing. Both the scrambler and de-scrambler can be bypassed. Nine example maximal length codes are represented below through their polynomial coefficients which can be directly programmed in Bits 9-0 of the SCRAMBLER CONTROL Register ($71): Length 2 3 4 5 6 7 8 9 10 Polynomial coefficients in hex format 0x003 0x006 0x00C 0x014 0x030 0x060 0x08E 0x110 0x240 5.1.10 Voice Activity Detector (VAD) The VAD function is implemented with an energy detector circuit. This circuit consists of an absolute value function, an integrator and a threshold detector. The threshold detector level and the integrator time constants (i.e. attack and decay time control) are user programmable via the DECODE and ENCODE VAD THRESHOLD Registers ($D2 and $E2) and the DECODER and ENCODER MODE AND SETUP Registers ($D0 and $E0). Referring to Figure 11, the input to the VAD comes from the PCM signal. The signal is rectified and averaged with a lossy integrator. The output of the integrator is compared to the VAD threshold to derive the logic signal VAD_OUT. If VAD_OUT is a logic one, signal energy greater than the threshold is present. If VAD_OUT is a logic zero, signal energy is below the threshold. Attack and decay times for the decoder VAD and encoder VAD can be independently controlled via the DECODER and ENCODER MODE AND SETUP Registers ($D0 and $E0). Typical attack and decay times used for detecting voice activity are 5ms and 150ms, respectively. The energy levels may be read from DECODE and ENCODE VAD LEVEL OUTPUT Registers ($D4 and $E4) for the decoder and encoder and used to adaptively set the detector threshold value by observing the energy level of background noise. VAD LEVEL $D4 & $E4 PCM SIGNAL VAD OUT + |y| - Time Constants $D0 & $E0 decay τ attack time constant factor C 1/4 1/8 1/16 1/32 0.5 VAD Threshold $D2 & $E2 Figure 11 VAD Block Diagram 2003 CML Microsystems Plc 12 D/649/2 ADM Codec 5.2 CMX649 C-BUS Description Address/Commands Instructions and data are transferred, via C-BUS, in accordance with the timing information given in Figure 12. Instruction and data transactions to and from the CMX649 consist of an Address/Command (A/C) byte followed by either: (i) (ii) a further instruction or data (1 or 2 bytes) or a status or Rx data reply (1 or 2 bytes) Write Only C-BUS Registers REGISTER NAME GENERAL RESET AAF/AIF BANDWIDTH HEX ADDRESS/ COMMAN D $01 BIT 7 (D7) BIT 6 (D6) BIT 5 (D5) BIT 4 (D4) BIT3 (D3) BIT 2 (D2) BIT 1 (D1) BIT 0 (D0) X X X X X X X X Anti-Alias Filter $61 By-Pass Band-Width VOLUME/SIDETONE LEVEL $62 Volume AUDIO INPUT LEVEL CTRL $63 Input Level POWER CONTROL 1 $64 POWER CONTROL 2 $65 CODEC MODE CONTROL $70 SCRAMBLER CONTROL (1) 0 AntiAlias Filter Mic Amp Current 0 Anti-Image Filter 0 0 By-Pass Side-Tone 0 AntiImage Filter Audio Current 0 Enc DAC Current Volume Current 0 SCRAMBLER $71 Band-Width 0 0 INVERT EN T7 T6 T5 T4 PREN DCKEN ECKEN 0 0 0 Dec DAC Current Xtal Current Analog Enable Codec Modes DE-SCRAMBLER EN ON/OFF Polynomial INVERT T9 T8 T2 T1 T0 Polynomial (2) CLK DIVIDER CONTROL (1) $72 (2) CLK SOURCE CONTROL (1) Bit Clock Pre-Scaler (2) CODEC INTERRUPT CONTROL 0 0 PLL EN Rx Bit Clk Select $73 $81 2003 CML Microsystems Plc T3 Filter Pre-Scaler Decoder Bit Clock Divider Phase Detect Input Select Tx Bit Clock Select Encode Enable 13 0 Data Filter ByPass Filter Divider Encoder Bit Clock Divider 0 0 Data Filter and Slicer Power Control 0 Data Filter BW Decode Enable D/649/2 ADM Codec REGISTER NAME DECODER MODE AND SETUP (1) CMX649 HEX ADDRESS/ COMMAN D $D0 (2) DECODE ADM CONTROL (1) DEC BY 4/8 $D1 BIT 5 (D5) Select PCM IN Syllabic Time Constant Estimator Integrator Principal Time Constant Select ADM IN Decoder Output Select VAD Attack Time Constant Select VAD Output Source Dynamic Range for Step Size Integrator 2nd Order Estimator Time Constant BIT 0 (D0) 0 0 Companding Rule Zero location for 2nd Order Integration Dec Zero Direct Write to DAC Input Bits 15 - 8 $D7 Direct Write to DAC Input Bits 7 – 0 $D8 ENCODER MODE AND SETUP (1) $E0 (2) Decode ADM Input DEC BY 4/8 Select PCM IN VAD Decay Time Constant $E1 Syllabic Time Constant Estimator Integrator Principal Time Constant (2) $E2 (2) ENCODE OFFSET LEVEL (1) BIT 1 (D1) Offset Input Level Bits 7 – 0 DECODE ADM INPUT ENCODE VAD THRESHOLD (1) BIT 2 (D2) Offset Input Level Bits 15 - 8 $D3 (2) ENCODE ADM CONTROL (1) BIT3 (D3) Voice Activity Detector Threshold Setting Bits 7 - 0 (2) DECODE LINEAR PCM INPUT (1) BIT 4 (D4) Voice Activity Detector Threshold Setting Bits 15 - 8 $D2 (2) DECODE OFFSET LEVEL (1) BIT 6 (D6) VAD Decay Time Constant (2) DECODE VAD THRESHOLD (1) BIT 7 (D7) Select ADM IN Local Decoder Output Select VAD Attack Time Constant Select VAD Output Source Dynamic Range for Step Size Integrator 2nd Order Estimator Time Constant Idle Channel Enhance ADM Output Select Companding Rule Zero location for nd 2 Order Integration Dec Zero Voice Activity Detector Threshold Setting Bits 15 - 8 Voice Activity Detector Threshold Setting Bits 7 - 0 Offset Input Level Bits 15 - 8 $E3 Offset Input Level Bits 7 – 0 (2) 2003 CML Microsystems Plc 14 D/649/2 ADM Codec REGISTER NAME ENCODE DAC INPUT (1) CMX649 HEX ADDRESS/ COMMAN D BIT 7 (D7) BIT 6 (D6) BIT 4 (D4) BIT3 (D3) BIT 2 (D2) BIT 1 (D1) BIT 0 (D0) BIT 1 (D1) BIT 0 (D0) Direct Write to DAC Input Bits 15 - 8 $E7 (2) ENCODE ADM INPUT BIT 5 (D5) Direct Write to DAC Input Bits 7 – 0 Encode ADM Input $E8 Read Only C-BUS Registers REGISTER NAME HEX ADDRESS/ COMMAN D CODEC STATUS (READ) $80 DECODE VAD LEVEL OUTPUT (1) $D4 (2) DECODE OFFSET LEVEL OUTPUT (1) BIT 7 (D7) BIT 6 (D6) BIT 5 (D5) Encode Process Status BIT3 (D3) BIT 2 (D2) Decode Processor Status Voice Activity Detector Level Output Bits 15 - 8 Voice Activity Detector Level Output Bits 7 - 0 Offset Level Output Bits 15 - 8 $D5 (2) DECODE LINEAR PCM OUTPUT (1) BIT 4 (D4) Offset Level Output Bits 7 - 0 $D6 (2) Linear PCM Output Signal Bits 15 - 8 Linear PCM Output Signal Bits 7 - 0 DECODE ADM OUTPUT $DA Decode ADM Output ENCODE VAD LEVEL OUTPUT (1) $E4 Voice Activity Detector Level Output Bits 15 - 8 (2) 2003 CML Microsystems Plc Voice Activity Detector Level Output Bits 7 - 0 15 D/649/2 ADM Codec REGISTER NAME CMX649 HEX ADDRESS/ COMMAN D ENCODE OFFSET LEVEL OUTPUT (1) BIT 7 (D7) BIT 6 (D6) BIT 5 (D5) 5.2.1 BIT 2 (D2) BIT 1 (D1) BIT 0 (D0) Offset Level Output Bits 7 - 0 Linear PCM Output Signal Bits 15 - 8 $E6 (2) ENCODE ADM OUTPUT BIT3 (D3) Offset Level Output Bits 15 - 8 $E5 (2) ENCODE LINEAR PCM OUTPUT (1) BIT 4 (D4) Linear PCM Output Signal Bits 7 - 0 Encode ADM Output $EA Write Only Register Description GENERAL RESET ($01) The reset command has no data attached to it. Application of the GENERAL RESET sets all write only register bits to 0. AAF/AIF BANDWIDTH Register ($61) AAF Bypass (Bit 7) AAF Bandwidth (Bits 6 – 4) When this bit is set to logic 1 the anti-alias filter is bypassed. The –3dB cutoff frequency of the anti-alias filter is controlled by bits 4 – 6. The filter shape is not altered other than to move the cutoff frequency. Bit 6 0 0 0 0 1 1 Bit 5 0 0 1 1 0 0 Bit 4 0 1 0 1 0 1 -3dB Frequency 2.9kHz 3.7kHz 5.0kHz 7.0kHz 10.0kHz 14.0kHz AIF Bypass (Bit 3) When this bit is set to a logic 1 the anti-image filter is bypassed. AIF Bandwidth (Bits 2 – 0) The –3dB cutoff frequency of the anti-image filter is controlled by bits 0-2. The filter shape is not altered other than to move the cutoff frequency. 2003 CML Microsystems Plc 16 D/649/2 ADM Codec CMX649 Bit 2 0 0 0 0 1 1 Bit 1 0 0 1 1 0 0 Bit 0 0 1 0 1 0 1 -3dB Frequency 2.9kHz 3.7kHz 5.0kHz 7.0kHz 10.0kHz 14.0kHz VOLUME/SIDETONE LEVEL Register ($62) The five most significant bits in this register are used to set the gain of the volume control according to the table below: Volume Level (Bits 7 – 3) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2003 CML Microsystems Plc 17 Increment Per Step = 1.5dB Steps Off -33.0dB -31.5dB -30.0dB -28.5dB -27.0dB -25.5dB -24.0dB -22.5dB -21.0dB -19.5dB -18.0dB -16.5dB -15.0dB -13.5dB -12.0dB -10.5dB -9.0dB -7.5dB -6.0dB -4.5dB -3.0dB -1.5dB 0.0dB 1.5dB 3.0dB 4.5dB 6.0dB 7.5dB 9.0dB 10.5dB 12.0dB D/649/2 ADM Codec Sidetone Level (Bits 2 – 1) CMX649 These bits control the gain of the sidetone signal coming from the AAF output to be summed in with the decode signal at the input to the AIF. Bit 2 0 0 1 1 Sidetone Enable (Bit 0) Bit 1 0 1 0 1 Gain Setting 0dB -9dB -15dB -21dB When this bit is a logic 1 the sidetone path is enabled with the gain setting controlled as shown above. When this bit is logic 0 the sidetone path is disabled. AUDIO INPUT LEVEL CONTROL Register ($63) Audio Input Level Control (Bits 7 – 3) These bits are used to set the gain of the Digitally Controlled Amplifier (DCA) at the output of the microphone amplifier. Bit 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reserved (Bits 2– 0) Bit 6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Audio Input Gain Off -7.5dB -7.0dB -6.5dB -6.0dB -5.5dB -5.0dB -4.5dB -4.0dB -3.5dB -3.0dB -2.5dB -2.0dB -1.5dB -1.0dB -0.5dB 0.0dB 0.5dB 1.0dB 1.5dB 2.0dB 2.5dB 3.0dB 3.5dB 4.0dB 4.5dB 5.0dB 5.5dB 6.0dB 6.5dB 7.0dB 7.5dB These bits are reserved and should be set to a logic 0. 2003 CML Microsystems Plc 18 D/649/2 ADM Codec CMX649 POWER CONTROL 1 Register ($64) This bit is reserved and should be set to a logic 0 AAF Power Control (Bit 7) AAF Power Control (Bit 6) This bit is dedicated to power/current control for the AAF. Note: It is necessary to keep the power level set to one of the “ON” settings when the AAF is bypassed. Bit 7 0 0 Bit 6 0 1 Power Level Setting Power down (Off). Normal operation. AIF Power Control (Bit 5) This bit is reserved and should be set to a logic 0. AIF Power Control (Bit 4) This bit is dedicated to power/current control for the AIF and the Sidetone DCA. Note: It is necessary to keep the power level set to one of the “ON” settings when the AIF is bypassed. Bit 5 0 0 Encode DAC Power Control (Bits 3 – 2) Power Level Setting Power down (Off). Normal operation. These bits are dedicated to power/current control for the Encode DAC. Bit 3 0 0 1 1 Decode DAC Power Control (Bits 1 – 0) Bit 4 0 1 Bit 2 0 1 0 1 Power Level Setting Power down (Off). Lowest power (for bit rates less than 32kbps). Low power (for bit rates between 32kbps and 64kbps). Normal operation (for bit rates greater than 64kbps). These bits are dedicated to power/current control for the Decode DAC. Bit 1 0 0 1 1 2003 CML Microsystems Plc Bit 0 0 1 0 1 Power Level Setting Power down (Off). Lowest power (for bit rates less than 32kbps). Low power (for bit rates between 32kbps and 64kbps). Normal operation (for bit rates greater than 64kbps). 19 D/649/2 ADM Codec CMX649 POWER CONTROL 2 Register ($65) These bits are dedicated to power/current control for the Microphone Amplifier. MIC AMP Power Control (Bits 7 – 6) Bit 7 0 0 1 1 Bit 6 0 1 0 1 Power Level Setting Power down (Off). Lowest power (for audio bandwidths less than 3.3kHz). Low power (for bit rates between 3.3kHz and 10kHz). Normal operation (for audio bandwidths greater than 10kHz). These bits are dedicated to power/current control for the Audio Input Digitally Controlled Amplfier. AUDIO DCA Power Control (Bits 5 – 4) Bit 5 0 0 1 Bit 4 0 1 0 1 1 Power Level Setting Power down (Off). Lowest power (for audio bandwidths less than 3.3kHz). Low power (for audio bandwidths between 3.3kHz and 10kHz). Normal operation (for audio bandwidths greater than 10kHz). These bits are dedicated to power/current control for the Volume Digitally Controlled Amplifier. VOLUME DCA Power Control (Bits 3 – 2) Bit 3 0 0 1 1 Bit 2 0 1 0 1 Power Level Setting Power down (Off). Lowest power (for bit rates less than 32kbps). Low power (for bit rates between 32kbps and 64kbps). Normal operation (for bit rates greater than 64kbps). XTAL Power Save (Bit 1) When this bit is a logic 1 the one-pin crystal oscillator circuit is powered down. ANALOG Enable (Bit 0) When this bit is set to a logic 1 all of the analog circuitry (register $64 and bits 7-2 of register $65) is enabled. When this bit is set to a logic 0 all of the analog circuitry is powered down (on-chip bandgap reference is powered down). This is equivalent to setting all of the bits of register $64 and bits 7-2 of register $65 to a logic 0. So to enable the AAF pabk, register $64 bit 6 and register $65 bit 0 must both be set to logic 1. Note that these bits control power to their respective blocks and that a signal path may still exist even if the block is power send. 2003 CML Microsystems Plc 20 D/649/2 ADM Codec CMX649 CODEC MODE CONTROL Register ($70) Reserved (Bits 7 – 3) These bits are reserved and should be set to a logic 0. CODEC MODE (Bits 2 – 0) Bit 2 0 0 0 0 1 Bit 1 0 0 1 1 0 Bit 0 0 1 0 1 0 CODEC Mode ADM mode without buffered I/O ADM mode with buffered I/O Linear PCM with buffered I/O µ-law PCM with buffered I/O A-law PCM with buffered I/O SCRAMBLER CONTROL Register ($71) Scrambler Enable (Bit 15) Setting this bit to a logic 1 enables the scrambler. Reserved (Bit 14) Reserved for future use. Set to ‘0’. Scrambler Output Invert (Bit 13) Setting this bit to a logic 1 inverts the scrambler output polarity. De-Scrambler Enable (Bit 12) Setting this bit to a logic 1 enables the de-scrambler. Reserved (Bit 11) Reserved for future use. Set to ‘0’. De-Scrambler Input Invert. (Bit 10) Setting this bit to a logic 1 inverts the de-scrambler input polarity. LFSR Tap Select (Bits 9 – 0) These bits directly program the polynomial for the scrambler and de-scrambler: 9 8 7 6 5 4 3 2 1 0 PR = B9X + B8X + B7X +B6X + B5X + B4X + B3X + B2X + B1X + B0X 2003 CML Microsystems Plc 21 D/649/2 ADM Codec CMX649 CLK DIVIDER CONTROL Register ($72) Pre-Scaler Enable (Bit 15) Setting this bit to a logic 1 enables the pre-scaler divider. Decode Bit Clock Enable (Bit 14) Setting this bit to a logic 1 enables the decode bit clock. Encode Bit Clock Enable (Bit 13) Setting this bit to a logic 1 enables the encode bit clock. Filter Clock PreScaler (Bits 12 – 11) These bits control the internal switched capacitor filter clock pre-scaler. Bit 12 0 0 1 1 Filter Clock Divider (Bits 10 – 8) Divider Ratio 1 2 3 4 These bits control the internal switched capacitor filter clock divider. Bit 10 0 0 0 0 1 1 1 1 Bit Clock PreScaler (Bits 7 – 6) Bit 11 0 1 0 1 Bit 9 0 0 1 1 0 0 1 1 Bit 8 0 1 0 1 0 1 0 1 Divider Ratio 2.000 8.000 15.500 15.750 16.000 22.000 31.250 46.750 These bits control the bit clock pre-scaler. Bit 7 0 0 1 1 2003 CML Microsystems Plc Bit 6 0 1 0 1 Divider Ratio 1 2 3 4 22 D/649/2 ADM Codec Decode Bit Clock Divider (Bits 5 – 3) CMX649 These bits control the decode bit clock divider. Bit 5 0 0 0 0 1 1 1 1 Encode Bit Clock Divider (Bits 2 – 0) Bit 4 0 0 1 1 0 0 1 1 Bit 3 0 1 0 1 0 1 0 1 Divider Ratio 1.000 2.000 2.250 2.625 3.000 3.125 3.375 3.500 These bits control the encode bit clock divider. Bit 2 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 Divider Ratio 1.000 2.000 2.250 2.625 3.000 3.125 3.375 3.500 The audio filter clock divider should be programmed to set the audio filter clock as near as possible to 256kHz, via selection of the XTAL frequency and the Filter Prescaler and Filter Divider settings. The encoder and decoder ADM bit rate clocks should be programmed to the desired ADM bit rate or PCM sample rate, multiplied by the interpolation/decimation setting of the PCM filter. The PCM filter can be programmed to run at either 4x or 8x the PCM sample rate depending on the corresponding setting in the encode/decode processors. The encoder and decoder ADM bit rate clocks are further divided by a constant factor of 64 (unless the PLL is enabled in which case the average is near 64 but can pull off slightly depending on the reference source). 2003 CML Microsystems Plc 23 D/649/2 ADM Codec CMX649 CLK SOURCE CONTROL Register ($73) Reserved (Bits 15-14) Phase Detect Input Select (Bit 13) These bits are reserved and should be set to a logic 0. 0 = PLL locks to external input clock 1 = PLL locks to external input strobe. (Bit 12) 0 = PLL locks to data edges. 1 = PLL locks to external clock or strobe edges according to Bit 13 value. Reserved (Bits 11-8) These bits are reserved and should be set to a logic 0. PLL Enable (Bit 7) Setting this bit to a logic 1 enables the phase locked loop in the clock recover circuit. When the PLL is enabled the decoder ADM bit clock adjusts its phase in increments of 1/32 of the programmed period to minimise noise due to timing jitter. Setting this bit to a logic 0 free-wheels the post divide by 64 decode clock divider and thus produces a bit clock which is synchronised to the XTAL/CLK input. Decode Bit Clock Select (Bit 6) Setting this bit to a logic 1 selects the bit clock generated by the clock recovery circuit. Setting this bit to a logic 0 selects a bit clock externally applied to the RX CLK pin. Encode Bit Clock Select (Bits 5 – 4) These bits allow for the selection of three different sources for the encode bit clock. Bit 5 X 0 1 Bit 4 0 1 1 Encode Bit Clock External Tx Clock Pin. Internally Generated encode clock. Internally Generated from decode clock. Note that a system clock or crystal is always required on the XTAL/CLK pin, in order to generate the various internal timing signals, even when Rx and Tx Clocks are recovered from the RX DATA pin. Data Filter Bypass (Bit 3) Setting this bit to a logic 1 bypasses the data filter and inputs the RX DATA signal directly into the data slicer. Data Filter and Slicer Power Control (Bits 2 – 1) These bits are dedicated to power/current control for the data filter and slicer. Bit 2 0 0 1 Bit 1 0 1 0 1 1 Power Level Setting Power down (Off). Lowest power (for bit rates less than 32kbps). Low power (for bit rates between 32kbps and 64kbps). Normal operation (for bit rates greater than 64kbps). When the Data Filter and Slicer are powered off, the RX DATA input pin signal must conform to logic level amplitudes. When operating the device in buffered I/O modes, the Data Filter and Slicer should be powered off. 2003 CML Microsystems Plc 24 D/649/2 ADM Codec CMX649 Setting this bit to a logic 1 forces the data filter to narrow bandwidth mode. Data Filter Bandwidth (Bit 0) CODEC INTERRUPT CONTROL Register ($81) Encoder Control (Bits 7 – 4) Bit 7 Bit 5 Bit 4 Encoder Setting 0 1 1 Bit 6 X 0 1 X 0 X X 0 X 1 X 1 X 1 X X 1 Encoder is disabled and reset. Encoder is enabled to run without generating IRQs. Encoder is enabled and will generate IRQs to indicate VAD status changes. Encoder is enabled and will generate periodic IRQs to indicate whether PCM data is available or needed when transcoding. Encoder is enabled and will generate periodic IRQs to indicate whether ADM data is available or needed when transcoding. Bit 3 0 1 1 Bit 2 X 0 1 Bit 1 X 0 X Bit 0 X 0 X 1 X 1 X 1 X X 1 Decoder Control (Bits 3 – 0) Decoder Setting Decoder is disabled and reset. Decoder is enabled to run without generating IRQs. Decoder is enabled and will generate IRQs to indicate VAD status changes. Decoder is enabled and will generate periodic IRQs to indicate whether the PCM data is needed or available when transcoding. Decoder is enabled and will generate periodic IRQs to indicate whether the ADM data is needed or available when transcoding. DECODER MODE AND SETUP Register ($D0) Decimation Rate (by 4/8) (Bit 15) The decoder PCM filter functions as an interpolator for the DAC when PCM words are being received by the decoder and as a decimator when the decoder is receiving delta modulation. In the case where delta modulation is received, transcoded PCM values are available in the DECODE LINEAR PCM OUTPUT Register ($D6) at the decimation rate. When PCM is received the device can be set to transcode to an ADM stream available in the DECODE ADM OUTPUT Register ($DA) at the interpolated rate. A logic 1 sets the interpolation (decimation) rate to 4 (1/4th the bit th rate). A logic 0 sets the interpolation (decimation) rate to 8 (1/8 the bit rate). 2003 CML Microsystems Plc 25 D/649/2 ADM Codec PCM Input Select (Bits 14 – 13) CMX649 Allows selection of the input to the PCM rate converting filter. Bit 14 0 Bit 13 X 1 0 1 1 Selected PCM Input PCM filter decimates ADM estimator output. PCM words available in register $D6. PCM filter interpolates linear PCM input from burst mode interface (RX DATA pin). This selection must be made in conjunction with the CODEC MODE CONTROL Register ($70). Note that the burst interface expands µLaw or Alaw signals to linear PCM prior to the PCM filter. PCM filter interpolates linear PCM input from C-BUS interface via the DECODE LINEAR PCM INPUT Register($D7). If PCM filter interpolates, the decoder can digitally transcode a PCM signal to ADM. If PCM filter decimates, the decoder can digitally transcode an ADM signal to PCM. ADM Input Select (Bits 12 – 11) Decoder Output Select (Bits 10 – 9) Reserved (Bit 8) Bit 12 0 Bit 11 0 0 1 1 X Bit 10 0 0 Bit 9 0 1 1 1 0 1 Selected ADM Input ADM decoder input from the RX DATA pin. (Normal mode operation). ADM decoder gets input from C-BUS via the DECODE ADM INPUT Register ($D8). This could be used to force in an idle pattern or to play out an arbitrary stored signal. (Alternate ADM input operation). ADM input from digital feedback. When ADM input comes from digital feedback it will transcode from PCM to ADM. PCM filter must be set to interpolate. In this mode the analog interface can be powered down since all signal processing is done digitally. (PCM to ADM transcoding input operation). Selected Decoder Output ADM estimator output drives decoder output. ADM estimator output summed with PCM interpolation filter output drives decoder output. The ADM and PCM signals can be input from any combination of RX DATA pin and C-BUS input registers. Direct PCM test mode. Interpolated PCM output. This bit is reserved and should be set to a logic 0. 2003 CML Microsystems Plc 26 D/649/2 ADM Codec Decoder VAD Decay Time Constant (Bits 7 – 5) CMX649 Allows selection of the Voice Activity Detector decay time constant. Bit 7 Bit 6 Bit 5 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Decay Time Constant (ms), Bit Rate in kbps 128/(Bit Rate) 256/(Bit Rate) 512/(Bit Rate) 1024/(Bit Rate) 2048/(Bit Rate) 4096/(Bit Rate) 8192/(Bit Rate) 16384/(Bit Rate) Decoder VAD Attack Time Constant (Bits 4 – 3) Allows selection of the Voice Activity Detector attack time constant. Decoder VAD Output Source (Bits 2 – 1) Allows selection of the Voice Activity Detector output source. Reserved (Bit 0) Bit 4 0 0 1 1 Bit 3 0 1 0 1 Bit 2 0 0 Bit 1 0 1 1 1 0 1 Attack Time Constant (ms) (VAD Decay Time Constant)/4 (VAD Decay Time Constant)/8 (VAD Decay Time Constant)/16 (VAD Decay Time Constant)/32 VAD Output Normal VAD operation. ADM bits are driven over VAD pin at the ADM bit rate (may be useful when transcoding or verifying proper application of the burst interface). VAD output driven to 0. VAD output driven to 1. This bit is reserved and should be set to a logic 0. DECODE ADM CONTROL Register ($D1) Syllabic Time Constant (Bits 15 – 13) Step size integrator Loss Coefficient: allows selection of syllabic time constant. 2003 CML Microsystems Plc Bit 15 0 0 0 0 1 1 Bit 14 0 0 1 1 0 0 Bit 13 0 1 0 1 0 1 1 1 1 1 0 1 27 Syllabic Filter Time Constant (ms) 512/(3*Bit Rate) 768/(3*Bit Rate) 1024/(3*Bit Rate) 1536/(3*Bit Rate) 2048/(3*Bit Rate) 3072/(3*Bit Rate) Bluetooth compatible when running at 64kbps. 4096/(3*Bit Rate) 6144/(3*Bit Rate) D/649/2 ADM Codec CMX649 Dynamic Range for Step Size Integrator (Bits 12 – 10) Maximum and minimum step size are based on 16-bit word length (-32768 to 32767). Companding Rule (Bits 9 – 8) This is the number of consecutive ones or zeros that must occur for the step size to be adjusted. Bit 9 Bit 8 Companding Rule 0 0 3 of 3 0 1 4 of 4 Bluetooth compatible when running at 64kbps. 1 0 5 of 5 1 1 6 of 6 Estimator Integrator Time Constant (Bits 7 – 5) Allows selection of the estimator integrator time constant. Second Order Estimator Time Constant (Bits 4 – 3) Bit 12 0 0 0 0 1 1 1 1 Bit 11 0 0 1 1 0 0 1 1 Bit 10 0 1 0 1 0 1 0 1 Maximum Step 10240 10240 5120 5120 2560 2560 1280 1280 Bit 7 0 0 0 0 1 1 Bit 6 0 0 1 1 0 0 Bit 5 0 1 0 1 0 1 1 1 1 1 0 1 Minimum Step 20 10 20 10 20 10 20 10 Bluetooth compatible when running at 64kbps. Decay Time Constant (ms) 16/(3*Bit Rate) 24/(3*Bit Rate) 32/(3*Bit Rate) 48/(3*Bit Rate) 64/(3*Bit Rate) 96/(3*Bit Rate) Bluetooth compatible when running at 64kbps. 128/(3*Bit Rate 192/(3*Bit Rate) Allows selection of the second order estimator time constant. 2003 CML Microsystems Plc Bit 4 0 0 1 1 Bit 3 0 1 0 1 Time Constant (ms), Bit Rate in kbps N/A (selects first order estimator). (Estimator Time Constant)/2 (Estimator Time Constant)/4 (Estimator Time Constant)/8 28 D/649/2 ADM Codec Zero Selection (Bits 2 – 1) CMX649 When second order integration is used, a zero can be inserted to help encoder stability. Not generally used in the decoder unless set to digitally transcode from PCM to ADM. Bit 2 0 0 1 1 Zero at ½ Bit Rate (Bit 0) Bit 1 0 1 0 1 Time Constant (ms), Bit Rate in kbps N/A (select for first order estimator). 1.5/Bit Rate 2.5/Bit Rate 4.5/Bit Rate When decoding ADM, a zero at (bit rate)/2 can be enabled by setting this bit to logic 1. When transcoding from PCM to ADM this bit should always be set to logic 0 to avoid instability in the transcoding loop. DECODE VAD THRESHOLD Register ($D2) Decode VAD Threshold (Bits 15 – 0) These bits directly program the threshold of detection for the Voice Activity Detector. The number programmed into this register can range from $0 to $7FFF (0 to 32767). The equation for the VAD threshold is: (Signal Detection Threshold) ⋅ 215 Register Value = (DAC Full Scale Reference Voltage) DECODE OFFSET LEVEL Register ($D3) Decode Offset Input (Bits 15 – 0) For normal Decoder operation this register should be set to logic 0. These bits allow for an offset amount to be directly programmed. This offset amount is useful in trimming out offsets that may occur in the on-chip analog circuitry. The number format is 2’s complement and ranges from $8000 through $0000 to $7FFF (-32768 to 32767). The equation for the Offset value is: Register Value = (Offset Voltage) ⋅ 218 (DAC Full Scale Reference Voltage) The programmed offset will be summed with the decoder output signal. DECODE LINEAR PCM INPUT Register ($D7) Decode Linear PCM Input (Bits 15 – 0) This register allows input of linear PCM via C-BUS for transcoding. The number format is 2’s complement and ranges from $8000 through $0000 to $7FFF (-32768 to 32767). Bit 1 of the CODEC INTERRUPT CONTROL Register ($81) can be set to a logic 1 to enable interrupts informing a micro-controller when the register should be updated. 2003 CML Microsystems Plc 29 D/649/2 ADM Codec CMX649 DECODE ADM INPUT Register ($D8) Decoder ADM Input (Bits 7 – 0) This register allows ADM bits to be written into the decoder via C-BUS and is intended for transcoding. Bit 0 of the CODEC INTERRUPT CONTROL Register ($81) can be set to a logic 1 to enable interrupts informing a micro-controller when the register should be updated. Additionally this register can be loaded with an idle data pattern ($55 or $AA) and then selected as the input to the decoder via the DECODER MODE AND SETUP Register ($D0) ENCODER MODE AND SETUP Register ($E0) Decimation Rate (by 4/8) (Bit 15) The encoder PCM filter functions as a decimating lowpass when the encoder is running. PCM values are available in the ENCODE LINEAR PCM OUTPUT Register ($E6) at the decimation rate. A logic 1 sets the decimation rate to 4 (1/4th the bit rate). A logic 0 sets the decimation rate to 8 (1/8th the bit rate). PCM Input Select (Bits 14 – 13) Allows selection of the input to the PCM rate converting filter. Bit 14 0 Bit 13 X 1 0 1 1 Selected PCM Input PCM filter decimates ADM estimator output PCM words available in register $E6. PCM filter interpolates PCM input from burst mode interface (RX DATA pin). This selection must be made in conjunction with the CODEC MODE CONTROL Register ($70). PCM filter interpolates PCM input from CBUS interface via the ENCODE DAC TEST CONTROL Register ($E7). If PCM filter is interpolating, the encoder can transcode a PCM signal to ADM. If PCM filter is decimating, the encoder will transcode an ADM signal to PCM. ADM Input Select (Bits 12 – 11) Bit 12 0 Bit 11 0 0 1 1 X 2003 CML Microsystems Plc Selected ADM Input ADM encoder input from Comparator. (Normal mode operation). ADM encoder gets input from C-BUS breaking the feedback loop and allowing the local decoder to digitally transcode an ADM signal input via C-BUS to a PCM signal output via C-BUS or the burst interface. (Alternate ADM input operation). ADM input from transcode feedback. When ADM input comes from transcode feedback it will transcode from PCM to ADM. The PCM filter must be set to interpolate. In this mode the encode analog interface can be powered down since it is not used. (PCM to ADM transcoding input operation). 30 D/649/2 ADM Codec Local Decoder Output Select (Bits 10 – 9) CMX649 Bit 10 0 Bit 9 0 0 1 1 1 Idle Channel Enhance (Bit 8) 0 1 Selected Local Decoder Output ADM estimator output drives local decoder output. ADM estimator output summed with PCM interpolation filter output drives local decoder output. For encoder, ADM output tracks sum of MIC input analog signal plus a PCM signal input over the C-BUS interface. Direct PCM test mode. Interpolated PCM output. This bit improves the perceived low-level sound quality by enabling the automatic tracking of offsets, which reduces internal offset levels. Some increase in harmonic distortion may result from the use of this bit. If automatic compensation is not required, this bit should be set to logic 0 and the ENCODE OFFSET LEVEL Register ($E3) should also be set to logic 0. This bit should normally be set to a logic 1 to allow analog offsets to be automatically compensated. When running the encoder as a digital ADM to PCM transcoder this bit should be set to 0 since the local ADM decoder runs outside a feedback loop. When enabling offset compensation, ensure the encoder ADM input selection is set either for feedback from the comparator or for PCM to ADM transcoding. Also load the ENCODE OFFSET LEVEL Register ($E3) with a small positive constant. If transcode feedback is selected then the PCM filter must also be set to interpolate. Encoder VAD Decay Time Constant (Bits 7 – 5) These bits allow selection of the Voice Activity Detector decay time constant. Encoder VAD Attack Time Constant (Bits 4 – 3) Allows selection of the Voice Activity Detector attack time constant. Encoder VAD Output Source (Bits 2 – 1) Bit 7 0 0 0 0 1 1 1 1 Bit 6 0 0 1 1 0 0 1 1 Bit 5 0 1 0 1 0 1 0 1 Decay Time Constant (ms), Bit Rate in kbps 128/(Bit Rate) 256/(Bit Rate) 512/(Bit Rate) 1024/(Bit Rate) 2048/(Bit Rate) 4096/(Bit Rate) 8192/(Bit Rate) 16384/(Bit Rate) Bit 4 Bit 3 Attack Time Constant (ms) 0 0 (VAD Decay Time Constant)/4 0 1 (VAD Decay Time Constant)/8 1 0 (VAD Decay Time Constant)/16 1 1 (VAD Decay Time Constant)/32 Allows selection of the Voice Activity Detector output source. Bit 2 0 0 Bit 1 0 1 1 1 0 1 2003 CML Microsystems Plc VAD Output Nominal VAD operation. ADM bits are driven over VAD pin at the ADM bit rate (may be useful when transcoding or verifying proper application of the burst interface). VAD output driven to 0. VAD output driven to 1. 31 D/649/2 ADM Codec ADM Output Select (Bit 0) CMX649 For normal operation this bit should be set to a logic 0. Setting this bit to a logic 1 allows arbitrary ADM streams, written in via the ENCODE ADM INPUT Register ($E8), to be output. For example to force the encoder to output an idle pattern 010101… while running, regardless of the input analog waveform, write $55 into register $E8 and set this bit to a logic 1. ENCODE ADM CONTROL Register ($E1) Syllabic Time Constant (Bits 15 – 13) Dynamic Range for Step Size Integrator Step Size Integrator (Bits 12 – 10) Companding Rule (Bits 9 – 8) Step size integrator Loss Coefficient: allows selection of syllabic time constant. Bit 15 Bit 14 Bit 13 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 1 1 1 0 1 Syllabic Filter Time Constant (ms), Bit Rate in kbps 512/(3*Bit Rate) 768/(3*Bit Rate) 1024/(3*Bit Rate) 1536/(3*Bit Rate) 2048/(3*Bit Rate) 3072/(3*Bit Rate) Bluetooth compatible when running at 64kbps. 4096/(3*Bit Rate) 6144/(3*Bit Rate) Numbers given for maximum and minimum step size are based on 16-bit word length (-32768 to 32767). Bit 12 0 0 0 0 1 1 1 1 Bit 11 0 0 1 1 0 0 1 1 Bit 10 0 1 0 1 0 1 0 1 Maximum Step 10240 10240 5120 5120 2560 2560 1280 1280 Minimum Step 20 10 20 10 20 10 20 10 Bluetooth compatible when running at 64kbps. This is the number of consecutive ones or zeros that must occur for the step size to be adjusted. 2003 CML Microsystems Plc Bit 9 0 0 Bit 8 0 1 1 1 0 1 32 Companding Rule 3 of 3 4 of 4 Bluetooth compatible when running at 64kbps. 5 of 5 6 of 6 D/649/2 ADM Codec Estimator Integrator Time Constant (Bits 7 – 5) CMX649 Allows selection of the estimator integrator time constant. Bit 7 Bit 6 Bit 5 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 1 1 1 0 1 Decay Time Constant (ms), Bit Rate in kbps 16/(3*Bit Rate) 24/(3*Bit Rate) 32/(3*Bit Rate) 48/(3*Bit Rate) 64/(3*Bit Rate) 96/(3*Bit Rate) Bluetooth compatible when running at 64kbps. 128/(3*Bit Rate 192/(3*Bit Rate) Second Order Estimator Time Constant (Bits 4 – 3) Allows selection of the second order estimator time constant. Zero Selection (Bits 2 – 1) When second order integration is used, a zero can be inserted to help stability. Bit 4 0 0 1 1 Bit 2 0 0 1 1 Zero at ½ Bit Rate (Bit 0) Bit 3 0 1 0 1 Bit 1 0 1 0 1 Loss Factor N/A (selects first order estimator). (Estimator Time Constant)/2 (Estimator Time Constant)/4 (Estimator Time Constant)/8 Time Constant (ms), Bit Rate in kbps N/A (select for first order estimator) 1.5/Bit Rate 2.5/Bit Rate 4.5/Bit Rate When decoding ADM, a zero at (bit rate)/2 can be enabled by setting this bit to logic 1. When encoding or transcoding from PCM to ADM this bit should always be set to a logic 0 to avoid instability of the ADM feedback loop. 2003 CML Microsystems Plc 33 D/649/2 ADM Codec CMX649 ENCODE VAD THRESHOLD Register ($E2) Encode VAD Threshold (Bits 15 – 0) These bits directly program the threshold of detection for the Voice Activity Detector. The number programmed into this register can range from $0 to $7FFF (0 to 32767). The equation for the VAD threshold is: (Signal Detection Threshold) ⋅ 215 Register Value = (DAC Full Scale Reference Voltage) ENCODE OFFSET LEVEL Register ($E3) Encode Offset Input (Bits 15 - 0) These bits allow for an offset amount to be directly programmed. This offset amount is useful in trimming out offsets that may occur in the on-chip analog circuitry. The number format is 2’s complement and ranges from $8000 through $0000 to $7FFF (-32768 to 32767). The equation for the direct offset value is: (Offset Voltage) ⋅ 218 Register Value = (DAC Full Scale Reference Voltage) For normal Encoder operation this register should be loaded with a small positive constant (eg in the range [2-16]) and bit 8 of the ENCODER MODE AND SETUP Register ($E0) should be set to logic 1. The programmed offset will be summed with the encoder input signal. If offset compensation is not required, bit 8 of the register $E0 should be set to logic 0 and the ENCODE OFFSET LEVEL Register should also be set to logic 0. Offset compensation can be suspended by loading this register with 0 while leaving Bit 8 of register $E0 true. This holds the current offset estimate constant. The offset estimate can be read out via the ENCODE OFFSET LEVEL OUTPUT Register ($E5). ENCODE DAC INPUT Register ($E7) Encode DAC Input (Bits 15 – 0) This register allows direct access to the encoder DAC input. The number format is 2’s complement and ranges from $8000 through $0000 to $7FFF (-32768 to 32767). ENCODE ADM INPUT TEST Register ($E8) Encoder ADM Input Test (Bits 7 – 0) This register allows ADM bits to be written via C-BUS for transcoding from ADM to PCM. An interrupt can be enabled to inform a micro-controller when the register needs reloading. 2003 CML Microsystems Plc 34 D/649/2 ADM Codec 5.2.2 CMX649 Read Only Register Description PROCESSOR STATUS READ Register ($80) Reading this STATUS register clears any pending IRQ. The PCM and ADM data available and data needed flags (bits 5, 4, 1 and 0 respectively) are cleared when the appropriate CBUS register is read (or written), in order to service the IRQ. The VAD detection flags (bits 6 and 2) are constantly updated to indicate the status of voice activity. Any change in state of either flag will cause an IRQ to be generated. Encoder Status (Bits 7 – 4) Bit 7 is permanently set to logic 0. A logic 1 in Bit 6 indicates Voice Activity is detected. A logic 1 in Bit 5 indicates PCM data is available (or needed when transcoding) A logic 1 in Bit 4 indicates ADM samples are available (or needed when transcoding). Decoder Status (Bits 3 – 0) Bit 3 is permanently set to logic 0. A logic 1 in Bit 2 indicates Voice Activity is detected. A logic 1 in Bit 1 indicates PCM data is needed (or available when transcoding). A logic 1 in Bit 0 indicates ADM samples are needed (or available when transcoding). DECODE VAD LEVEL OUTPUT READ Register ($D4) Decode VAD Level Output (Bits 15 – 0) These bits indicate the average amplitude of the envelope of the audio signal. This negative 2’s complement number can range from $0 to $8000 (0 to -32768 and can be used to assist in calculating an appropriate value to be programmed into the DECODE VAD THRESHOLD Register ($D2). The equation for the VAD level register value is: Register Value = -1⋅ (Envelope voltage level) ⋅ 215 (DAC Full Scale Reference Voltage) DECODE OFFSET LEVEL OUTPUT READ Register ($D5) Decode Offset Level Output (Bits 15 – 0) These bits indicate offset level as input by the user in register $D3. The number format is 2’s complement and ranges from $8000 through $0000 to $7FFF (-32768 to 32767). The equation for the offset value is: Register Value = (Offset Voltage) ⋅ 218 (DAC Full Scale Reference Voltage) DECODE LINEAR PCM OUTPUT READ Register ($D6) Decode Linear PCM Output (Bits 15 – 0) This register contains the linear PCM equivalent of the ADM or non-linear PCM input signal. The number format is 2’s complement and ranges from $8000 through $0000 to $7FFF (-32768 to 32767). Bit 1 of the CODEC INTERRUPT CONTROL Register ($81) can be set to a logic 1 to enable interrupts, informing a micro-controller when the register has been updated. The equation for the PCM register value is: (PCM voltage) ⋅ 215 Register Value = (DAC Full Scale Reference Voltage) 2003 CML Microsystems Plc 35 D/649/2 ADM Codec CMX649 DECODE ADM OUTPUT READ Register ($DA) Decode ADM Output (Bits 7 – 0) This register allows ADM bits to be read via C-BUS and is updated every eighth bit. Bit 0 of the CODEC INTERRUPT CONTROL Register ($81) can be set to a logic 1 to enable interrupts, informing a micro-controller when the register has been updated. When the decoder is set to transcode from PCM to ADM the ADM bits are available via this register. ENCODE VAD LEVEL OUTPUT READ Register ($E4) Encode VAD Level Output (Bits 15 – 0) These bits indicate the average amplitude of the envelope of the audio signal. This negative 2’s complement number can range from $0 to $8000 (0 to -32768) and can be used to assist in calculating an appropriate value to be programmed into the ENCODE VAD THRESHOLD Register ($E2). The equation for the VAD level register value is: Register Value = -1⋅ (Envelope voltage level) ⋅ 215 (DAC Full Scale Reference Voltage) ENCODE OFFSET LEVEL OUTPUT READ Register ($E5) Encode Offset Level Output (Bits 15 – 0) These bits indicate the offset level as input by the user in register $E3, which is dynamically updated if Idle Channel Enhance is enabled. The number format is 2’s complement and ranges from $8000 through $0000 to $7FFF (-32768 to 32767). It can be used as an appropriate value to be programmed into the ENCODE OFFSET LEVEL Register ($E3) if offset compensation will be disabled. The equation for the offset value is: Register Value = (Offset Voltage) ⋅ 218 (DAC Full Scale Reference Voltage) ENCODE LINEAR PCM OUTPUT READ Register ($E6) Encode Linear PCM Output (Bits 15 – 0) This register containes the linear PCM equivalent of the encoded ADM signal. The number format is 2’s complement and ranges from $8000 through $0000 to $7FFF (-32768 to 32767). Bit 5 of the CODEC INTERRUPT CONTROL Register ($81) can be set to a logic 1 to enable interrupts, informing a micro-controller when the register has been updated. The equation for the PCM register value is: (PCM voltage) ⋅ 215 Register Value = (DAC Full Scale Reference Voltage) ENCODE ADM OUTPUT READ Register ($EA) Encode ADM Output Test (Bits 7 – 0) This register allows Encoder ADM bits to be read via C-BUS and is updated every eighth bit. Bit 4 of the CODEC INTERRUPT CONTROL Register ($81) can be set to a logic 1 to enable interrupts, informing a micro-controller when the register has been updated. 2003 CML Microsystems Plc 36 D/649/2 ADM Codec CMX649 6. Application Notes 6.1 C-BUS Operation C-BUS Operation Instructions, status and data are transferred between the CMX649 and the host µC over the C-BUS. Instruction and data transfers to and from the CMX649 consist of an Address/Command (A/C) byte followed by either: 1. a further instruction or 2. 1 or 2 bytes of data (write) or 3. 1 or 2 bytes of status or received data reply (read). The number of data bytes following an A/C byte is dependent on the value of the A/C byte. The most significant bit of the address or data is sent first. The C-BUS SERIAL_CLOCK input to the CMX649 originates from the host µC. CSN SERIAL_CLOCK CMD_DATA 7 6 5 4 3 2 1 0 MSB 7 6 5 4 3 2 1 0 LSB First Data Byte Address/Command Byte REPLY_DATA 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB Logic level is not important Last Data Byte 7 6 5 4 3 2 1 0 LSB First Reply Data Byte Last Reply Data Byte Figure 12 C-BUS Timing Diagram 2003 CML Microsystems Plc 37 D/649/2 ADM Codec 6.2 CMX649 CODEC Data Interface Clock generation (internal clock - Master mode) non burst mode Synchronous operation (external clock – Slave mode) Max Frame length : limited by burst clock to bit rate ratio only Burst_CLK frequency : 5MHz max Data word length : 8 or 16 bits SYNC Delay : 0 Burst CLKs SYNC Length : 1 – (data word length – 1 ) Burst CLKs Words (slots) per frame : 1 Slot start references (from SYNC) Line TX_DATA RX_DATA Directio n Output Input Start at Clk Data Transition Edge Transmission Order Data Word Length and Byte Order 1 1 rise rise msb first msb first 8 or 16 bits (m.s. byte first) 8 or 16 bits (m.s. byte first) Tx and Rx clocks are tied together for burst mode. There is only one sync input. Sync_setup 75nS min Rx_setup 75nS min Sync_hold 75nS min Rx_hold 75nS min SYNC 70% BURST CLOCK 30% RX DATA TX DATA Configure to tri-state or drive between frames. 7 6 5 4 3 2 1 0 7 6 7 6 5 4 3 2 1 0 7 6 Tx_delay, 50nS max Figure 13 Burst Interface Timing Diagram for Concatenated Byte Transfers Notes for Figure 13: • In this example Bit 7 is the most significant bit. • Once started Rx and Tx data bits are continuously streaming so long as the SYNC pulse continues at the PCM sample rate. • Configuration options support some variations of this timing diagram, e.g. data word length, without affecting the timing shown. • The TX_DATA output may be high impedance between burst frames depending on bit 9 of CLK SOURCE CONTROL Register ($73). 2003 CML Microsystems Plc 38 D/649/2 ADM Codec 6.3 CMX649 Example CODEC Setups and Application Help Below are tabulated some applicable settings for the CLOCK DIVIDER CONTROL Register ($72) . Audio Switched Capacitor Filter Clock Settings (clock frequency in kHz) Crystal vs Audio Filter Divider Chart for CMX649 Yielding the Recommended ~256kHz SCF Clock Divider values 8 15.5 15.75 16 22 31.25 47.75 001 010 011 100 101 110 111 258.065 253.968 Register bits clk ctrl[10:8] Crystal Prescaler Freq MHz Value clk ctrl[12:11] 2.048 1 00 4 1 00 4.032 1 00 4.096 1 00 8 1 00 8.064 2 01 8.192 2 01 11.2896 2 01 12 1 00 12.096 3 10 12.288 3 10 16 2 01 16.128 4 11 16.384 4 11 2003 CML Microsystems Plc 256.000 256.000 256.000 256.000 256.000 256.000 256.582 256.684 256.000 256.000 256.000 256.000 256.000 39 D/649/2 ADM Codec CMX649 When selecting divider settings to arrive at a desired bit rate from a given crystal frequency, note that some power savings are realized by selecting a lower divider value in conjunction with a higher prescaler value, thus minimizing the frequency of the prescaler output. Bit Rate (kbps) Settings with Bit Rate Prescaler = 1 Crystal vs Divider chart for CMX649 Divider values 1 2 2.25 2.625 3 3.125 3.375 3.5 000 001 010 011 100 101 110 111 Register bits clk ctrl[5:3] [2:0] Crystal Freq MHz clk ctrl[7:6] 4 00 62.500 31.250 27.778 23.810 20.833 20.000 18.519 17.857 4.032 00 63.000 31.500 28.000 24.000 21.000 20.160 18.667 18.000 4.096 00 64.000 32.000 28.444 24.381 21.333 20.480 18.963 18.286 8 00 125.000 62.500 55.556 47.619 41.667 40.000 37.037 35.714 8.064 00 126.000 63.000 56.000 48.000 42.000 40.320 37.333 36.000 8.192 00 128.000 64.000 56.889 48.762 42.667 40.960 37.926 36.571 Applicable Bit Rate (kbps) Settings with Bit Rate Prescaler = 2 Crystal vs Divider chart for CMX649 Divider values 1 2 2.25 2.625 3 3.125 3.375 3.5 000 001 010 011 100 101 110 111 Register bits clk ctrl[5:3] [2:0] Crystal Freq MHz clk ctrl[7:6] 4 01 31.250 15.625 4.032 01 31.500 15.750 4.096 01 32.000 16.000 8 01 62.500 31.250 27.778 23.810 20.833 20.000 18.519 17.857 8.064 01 63.000 31.500 28.000 24.000 21.000 20.160 18.667 18.000 8.192 01 64.000 32.000 28.444 24.381 21.333 20.480 18.963 18.286 11.2896 01 88.200 44.100 39.200 33.600 29.400 28.224 26.133 25.200 12 01 93.750 46.875 41.667 35.714 31.250 30.000 27.778 26.786 12.096 01 94.500 47.250 42.000 36.000 31.500 30.240 28.000 27.000 12.288 01 96.000 48.000 42.667 36.571 32.000 30.720 28.444 27.429 16 01 125.000 62.500 55.556 47.619 41.667 40.000 37.037 35.714 16.128 01 126.000 63.000 56.000 48.000 42.000 40.320 37.333 36.000 16.384 01 128.000 64.000 56.889 48.762 42.667 40.960 37.926 36.571 2003 CML Microsystems Plc 40 D/649/2 ADM Codec CMX649 Applicable Bit Rate (kbps) Settings with Bit Rate Prescaler = 3 Crystal vs Divider chart for CMX649 Divider values 1 2 2.25 2.625 3 3.125 3.375 3.5 000 001 010 011 100 101 110 111 Register bits clk ctrl[5:3] [2:0] Crystal Freq MHz clk ctrl[7:6] 4 10 20.833 4.032 10 21.000 4.096 10 21.333 8 10 41.667 20.833 18.519 15.873 8.064 10 42.000 21.000 18.667 16.000 8.192 10 42.667 21.333 18.963 16.254 11.2896 10 58.800 29.400 26.133 22.400 19.600 18.816 17.422 16.800 12 10 62.500 31.250 27.778 23.810 20.833 20.000 18.519 17.857 12.096 10 63.000 31.500 28.000 24.000 21.000 20.160 18.667 18.000 12.288 10 64.000 32.000 28.444 24.381 21.333 20.480 18.963 18.286 16 10 83.333 41.667 37.037 31.746 27.778 26.667 24.691 23.810 16.128 10 84.000 42.000 37.333 32.000 28.000 26.880 24.889 24.000 16.384 10 85.333 42.667 37.926 32.508 28.444 27.307 25.284 24.381 Applicable Bit Rate (kbps) Settings with Bit Rate Prescaler = 4 Crystal vs Divider chart for CMX649 Divider values 1 2 2.25 2.625 3 3.125 3.375 3.5 000 001 010 011 100 101 110 111 Register bits clk ctrl[5:3] [2:0] Crystal Freq MHz clk ctrl[7:6] 4 11 15.625 4.032 11 15.750 4.096 11 16.000 8 11 31.250 15.625 8.064 11 31.500 15.750 8.192 11 32.000 16.000 11.2896 11 44.100 22.050 19.600 16.800 12 11 46.875 23.438 20.833 17.857 15.625 15.000 12.096 11 47.250 23.625 21.000 18.000 15.750 15.120 12.288 11 48.000 24.000 21.333 18.286 16.000 15.360 16 11 62.500 31.250 27.778 23.810 20.833 20.000 18.519 17.857 16.128 11 63.000 31.500 28.000 24.000 21.000 20.160 18.667 18.000 16.384 11 64.000 32.000 28.444 24.381 21.333 20.480 18.963 18.286 2003 CML Microsystems Plc 41 D/649/2 ADM Codec CMX649 6.3.1 32kbps ADM with clock and data recovery //Initialize device with general reset // This powers down everything excluding the xtal oscillator circuit $01 //Setup analog section // $61 00 filters set for 2.9kHz BW (default after reset) // volume=0dB side_tone=-21dB and off $62 $BE // audio_level=0dB $63 $80 // power_control everything on (lowest current setting) $64 $55 $65 $55 // codec mode // default $70 $00 ADM unbuffered (continuous bit serial mode) // Clock Divider Control // using 4.096MHz master clock // filter clock prescale/=2 main divider/=8 => 256kHz SCF clock // bit clock prescale/=2 encode and decode bit dividers/=1 since constant divider/=64 => 32kbps $72 $E9 $40 // PLL is off, Bypass PLL Data Filter and Power it Down // Internal Decode and Encode clocks from // Decode internal clock $73 $00 $78 // setup decoder // decimate by 8 // decode adm input from RX Data // adm estimator drives output // vad attack tc=4ms and decay tc=128ms // normal vad outputs $D0 $00 $B8 // adm encode feedback from comparator, nulling for improved idle – otherwise as decoder $E0 $01 $B8 // to enable offset nulling load small positive constant into encoder offset input reg $E3 $00 $04 // adm mode syllabic tc=16ms // step size dynamic range 5120/10 // companding rule = 4 of 4 // principal tc=0.33ms // second order tc=0.083ms // encoder zero tc=0.047ms decoder zero tc=N/A // decoder zero at 16kHz i.e. bit_rate/2 enabled $D1 $6D $51 $E1 $6D $52 // vad thresholds ~20mv $D2 $02 $00 $E2 $02 $00 // prime idle pattern into CBUS ADM source byte regs $D8 $AA $E8 $AA //Scrambler and Descrambler both on, using polynomial $14 (5 bit LFSR) $71 $90 $14 // enable encoder and decoder with no IRQs $81 $88 // note some useful register changes from the above settings // force encoder to output an idle pattern ($E0 $81 $B9) (requires $E8 $AA above) // force decoder to idle via idling its input ($D0 $88 $B8) (requires $D8 $AA above) // force decoder to mute output via direct PCM out ($D0 $86 $B8) (reset default has $D7 $00 $00) // turn Scrambler and Descrambler off ($71 $00 $00) // To Make PLL run with input from data pad // internal RX and TX clocks // RX data input acting as analog input i.e. data filter and data slicer running // ($73 $00 $D2) 2003 CML Microsystems Plc 42 D/649/2 ADM Codec CMX649 6.3.2 64kbps burst mode Bluetooth Compatible CVSD //Initialize device with general reset // This powers down everything excluding the xtal oscillator circuit $01 //Setup analog section // $61 00 filters set for 2.9kHz BW (default after reset) // volume=0dB side_tone=-21dB and on $62 $BF // audio_level=0dB $63 $80 // power_control everything on (lowest current setting) $64 $55 $65 $55 // codec mode ADM buffered (burst bytes at 1/8 bit rate mode) $70 $01 // Clock Divider Control // with 4.096MHz master clock // filter clock prescale/=2 main divider/=8 => 256kHz SCF clock // bit clock prescale/=1 main divider/=1 since constant divider/=64 always => 64kHz bit clocks $72 $E9 $00 // PLL is not running // internal RX and TX bit clocks both from RX bit clock // RX data input acting as digital input for burst mode $73 $00 $70 // setup decoder // decimate by 8 // decode adm input from RX Data // adm estimator drives output // decode vad driven by adm bits at bit rate $D0 $00 $02 // adm encode feedback from comparator, nulling for improved idle – otherwise as decoder $E0 $01 $02 // to enable offset nulling load small positive constant into encoder offset input reg $E3 $00 $04 // adm mode BT CVSD algorithm // syllabic tc=16ms // step size dynamic range 1280/10 // companding rule = 4 of 4 // principal tc=0.5ms // second order tc=N/A // zero tc=N/A // zero at bit_rate/2 disabled $D1 $BD $A0 $E1 $BD $A0 // prime idle pattern into CBUS ADM source byte regs $D8 $AA $E8 $AA // enable encoder and decoder with no IRQs $81 $88 // Alternative settings for PCM format using second order ADM algorithm // syllabic tc=16ms // step size dynamic range 5120/10 // companding rule = 5 of 5 // principle tc=0.5ms // second order tc=0.0625ms // predictor zero tc=0.0234ms for encoder // zero at bit_rate/2 enabled for decoder //$D1 $AE $A1 //$E1 $AE $BA // codec mode 2=linear PCM buffered (3=uLaw 4=Alaw) //$70 $02 // decoder flow for input PCM plus transcode to ADM with offset null and output via VAD output. //$D0 $57 $02 //$D3 $00 $04 2003 CML Microsystems Plc 43 D/649/2 ADM Codec 7. Performance Specification 7.1 Electrical Performance CMX649 7.1.1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Supply (VDD - VSS) Voltage on any pin to VSS Current into or out of VDD and VSS pins Current into or out of any other pin Min. -0.3 -0.3 -30 -20 Max. 7.0 VDD + 0.3 +30 +20 E3 and D3 Package E3 Total Allowable Power Dissipation at Tamb = 25°C Derating above 25°C D3 Total Allowable Power Dissipation at Tamb = 25°C Derating above 25°C Storage Temperature Operating Temperature Min. – – – – -55 -40 Max. 300 5.0 800 13 +125 +85 Units V V mA mA Units mW mW/°C mW mW/°C °C °C 7.1.2 Operating Limits Correct operation of the device outside these limits is not implied. Notes Supply (VDD - VSS) Operating Temperature Xtal Frequency 2003 CML Microsystems Plc 44 Min. 2.7 -40 4.0 Max. 5.5 +85 16.0 Units V °C MHz D/649/2 ADM Codec CMX649 7.1.3 Operating Characteristics The following conditions are assumed unless otherwise specified: VDD = 2.7V to 5.5V at TAMB = -40 to +85°C, Audio Test Frequency = 820Hz, Xtal/Clock f0 = 4.096MHz, Data Rate = 32kbps, Audio reference level (0 dBm0) = 489mVRMS. DC Parameters IDD (powersaved) at VDD = 3.0V IDD (powersaved) at VDD = 5.0V IDD (XTAL only) at VDD = 3.0V IDD (XTAL only) at VDD = 5.0V IDD (low powermode) at VDD = 3.0V IDD (low powermode) at VDD = 5.0V Notes Min. Typ. Max. Units 1 1 1 1 1 1 – – – – 1.0 1.0 0.34 0.91 2.0 3.4 10.0 10.0 2.0 2.5 3.8 4.9 µA µA mA mA mA mA 70%VDD – 80% VDD – 1.0 300 – – – – – – – – – – – – 200 – ±4 1.235 – 30% VDD – 20%VDD – – 4.0 – 200 – – V V V V MΩ kΩ kΩ kΩ Ω µA V 2 2 -37 -37 – – 4.0 4.0 dB dB 2 2 - 0 0 - dB dB 3 3 3 3 – – – – -1.5 – – 2900 1400 6.0 24 40 0 – -61 -62 – – – – 3.0 - Input logic 1 Input logic 0 Output logic 1 Output logic 0 Logic I/O Pin Input Impedance Logic Input Pins, Pull-up Resistor Digital Output Impedance Analog Input Impedance Analog Output Impedance Three State Output Leakage DAC Full Scale Reference Voltage Dynamic Values Encoder Analog Signal Input Sensitivity VDD = 3.0V VDD = 5.0V Encoder Input to Decoder Output Insertion Loss VDD = 3.0V VDD = 5.0V Encoder/Decoder (Full Codec) Passband Lowest Corner Frequency Passband Highest Corner Frequency Stopband Lowest Corner Frequency Stopband Highest Corner Frequency Stopband Attenuation Passband Gain Passband Ripple Output Noise (Input Short Circuit) Perfect Idle Channel Noise (Encode Forced) Notes: 5 4,6 4,6 Hz Hz kHz kHz dB dB dB dBmOp dBmOp 1. Not including any current drawn from the device by external circuits. 2. Input and output signal levels are independent of supply voltage. 3. Passband and stopband corner frequencies are programmable. Specified values are at nominal crystal frequencies of 4.096, 8.192, 12.288, or 16.384Mhz with the master clock divider configured for a divide by 1, 2, 3, or 4 respectively. For other crystal frequencies passband and stopband corner frequencies must be scaled accordingly. 4. dBmOp units imply the use of a psophometrically weighted filter that is commonly used in voice communication applications per ITU Recommendation G.223. 5. From 400Hz to 3000Hz with a 3.7kHz bandwidth. 6. At VDD =2.7Vm, data rate = 64kbps, 2.9kHz bandwidth, offsets compensated and 1st order integration only. 2003 CML Microsystems Plc 45 D/649/2 ADM Codec CMX649 MIC Amplifier Open Loop Gain Unity Gain Bandwidth Input Impedance Output Impedance (open loop) Distortion 2003 CML Microsystems Plc 10 - 46 6.0 1.0 10 1 2 dB MHz MΩ KΩ % D/649/2 ADM Codec CMX649 7.1.3 (continued) C-BUS Timing Diagram Figure 14 C-BUS Timing Diagram 2003 CML Microsystems Plc 47 D/649/2 ADM Codec CMX649 C-BUS Timing (see Figure 14) tCSE CSN Enable to SClk high time tCSH Last SClk high to CSN high time tLOZ SClk low to ReplyData Output Enable Time tHIZ CSN high to ReplyData high impedance tCSOFF CSN high time between transactions tNXT Inter-byte time tCK SClk cycle time tCH SClk high time tCL SClk low time tCDS Command Data setup time tCDH Command Data hold time tRDS Reply Data setup time tRDH Reply Data hold time Notes: Notes Min. 100 100 0.0 Typ. Max. Unit ns ns ns 1.0 µs µs ns ns ns ns ns ns ns ns 1.0 200 200 100 100 75 25 50 0 1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the peripheral MSB (Bit 7) first, LSB (Bit 0) last. REPLY DATA is read from the peripheral MSB (Bit 7) first, LSB (Bit 0) last. 2. Data is clocked into the peripheral on the rising SERIAL_CLOCK edge. 3. Commands are acted upon at the end of each command (rising edge of CSN). 4. To allow for differing µC serial interface formats C-BUS compatible ICs are able to work with SERIAL_CLOCK pulses starting and ending at either polarity. 5. Maximum 30pF load on IRQN pin and each C-BUS interface line. These timings are for the CMX649, and allow faster transfers than the original C-BUS specification. For codec data interface timing specifications and diagrams please refer to section 6.2. 2003 CML Microsystems Plc 48 D/649/2 ADM Codec 7.2 CMX649 Packaging Figure 15 20-Lead TSSOP Mechanical Outline: Order as part no. CMX649E3 Figure 16 20-Lead SOIC Mechanical Outline: Order as part no. CMX649D3 2003 CML Microsystems Plc 49 D/649/2 ADM Codec CMX649 Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed. www.cmlmicro.com For FAQs see: www.cmlmicro.com/products/faqs/ For a full data sheet listing see: www.cmlmicro.com/products/datasheets/download.htm For detailed application notes: www.cmlmicro.com/products/applications/ Oval Park, Langford, Maldon, Essex, CM9 6WG - England. 4800 Bethania Station Road, Winston-Salem, NC 27105 - USA. No 2 Kallang Pudding Road, #09 to 05/06 Mactech Industrial Building, Singapore 349307 No. 218, Tian Mu Road West, Tower 1, Unit 1008, Shanghai Kerry Everbright City, Zhabei, Shanghai 200070, China. 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