INTEGRATED CIRCUITS DATA SHEET UDA1342TS Audio CODEC Preliminary specification File under Integrated Circuits, IC01 2000 Mar 29 Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS CONTENTS 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 8.2 8.2.1 8.2.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.14.1 8.14.2 8.14.3 8.15 8.15.1 8.15.2 8.15.3 8.15.4 8.15.5 8.16 8.16.1 8.16.2 8.16.3 8.16.4 8.16.5 System clock ADC analog front-end Application with 2 V (RMS) input Double differential mode Decimation filter (ADC) Digital mixer (ADC) Interpolation filter (DAC) Mute Digital mixer (DAC) Noise shaper Filter stream DAC Digital interface Sampling speed Power-on reset Control modes Static pin mode System clock setting select Digital interface format select ADC input channel select L3-bus interface Introduction Device addressing Register addressing Data write mode Data read mode I2C-bus interface Addressing Slave address Register address Write cycle Read cycle 9 REGISTER MAPPING 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 Reset Quick mode switch Bypass mixer DC filter DC filter ADC mode ADC polarity System clock frequency Data format 2000 Mar 29 9.9 9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22 9.23 9.24 9.25 9.26 DAC power control Input oversampling rate DAC polarity DAC mixing position switch DAC mixer Silence detection period Multi purpose output Mode Bass boost Treble Silence detector switch Mute Quick mute mode De-emphasis ADC input amplifier gain DAC volume control DAC mixer volume control ADC mixer gain control 10 LIMITING VALUES 11 HANDLING 12 QUALITY SPECIFICATION 13 THERMAL CHARACTERISTICS 14 DC CHARACTERISTICS 15 AC CHARACTERISTICS 16 TIMING 17 APPLICATION INFORMATION 18 PACKAGE OUTLINE 19 SOLDERING 19.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 19.2 19.3 19.4 19.5 2 20 DATA SHEET STATUS 21 DEFINITIONS 22 DISCLAIMERS 23 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Preliminary specification Audio CODEC 1 UDA1342TS FEATURES General • 2.7 to 3.6 V power supply • 5 V tolerant digital inputs • High pin compatibility with UDA1341TS • 24 bits data path • Selectable control via L3-bus interface, I2C-bus interface or static pin control; choice of 2 device addresses in L3-bus and I2C-bus mode Advanced audio configuration • Separate power control for ADC and DAC • 4 channel (2 × stereo) single-ended inputs with programmable gain amplifiers and 2 channel (1 × stereo) single-ended outputs configuration • ADC and Programmable Gain Amplifiers (PGA) plus integrated high-pass filter to cancel DC offset • Output signal polarity control in L3-bus mode or I2C-bus mode • Integrated digital filter plus DAC • High linearity, wide dynamic range, low distortion • Digital silence detection • Double differential input configuration for enhanced ADC sound quality. • Supports sample frequencies from 16 to 110 kHz • No analog post filtering required for DAC • Slave mode only applications 2 • Easy application. APPLICATIONS • Eminently suitable for MiniDisc (MD) home and portable applications. Multiple format data interface • I2S-bus, MSB-justified and LSB-justified format compatible 3 • 1fs to 4fs input and 1fs output format data rate. GENERAL DESCRIPTION The UDA1342TS is a single-chip 4 channel analog-to-digital converter and 2 channel digital-to-analog converter with signal processing features employing bitstream conversion techniques. The low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates recording and playback functions. DAC digital sound processing • Separate digital logarithmic volume control for left and right channels in L3-bus mode or I2C-bus mode • Digital tone control, bass boost and treble in L3-bus mode or I2C-bus mode • Digital de-emphasis for sample frequencies of 32, 44.1, 48 and 96 kHz in L3-bus mode or I2C-bus mode The UDA1342TS supports the I2S-bus data format with word lengths of up to 24 bits, the MSB-justified data format with word lengths of up to 24 bits and the LSB-justified serial data format with word lengths of 16, 20 and 24 bits. The device also supports a combination of the MSB-justified output format and the LSB-justified input format. • Soft or quick mute in L3-bus mode or I2C-bus mode • Output signal polarity control in L3-bus mode or I2C-bus mode • Digital mixer for ADC output signal and digital serial input signal. The UDA1342TS has special sound processing features in the playback mode such as de-emphasis, volume, mute, bass boost and treble, which can be controlled by the microcontroller via the L3-bus or I2C-bus interface. 2000 Mar 29 3 Philips Semiconductors Preliminary specification Audio CODEC 4 UDA1342TS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA(ADC) ADC analog supply voltage 2.7 3.0 3.6 V VDDA(DAC) DAC analog supply voltage 2.7 3.0 3.6 V VDDD digital supply voltage 2.7 3.0 3.6 V IDDA(ADC) ADC analog supply current 1 ADC + 1 PGA enabled − 10.0 − mA 2 ADCs + 2 PGAs enabled − 20.0 − mA all ADCs + all PGAs power-down − 200 − µA operating − 6.0 − mA DAC power-down − 250 − µA IDDA(DAC) IDDD Tamb DAC analog supply current digital supply current operating − 9.0 − mA ADC power-down − 4.5 − mA DAC power-down − 5.5 − mA −40 − +85 °C − 0.9 − V − −90 − dB − −40 − dB at −1 dB − −93 − dB at −60 dB; A-weighted − −41 − dB − −84 − dB − −40 − dB normal mode; Vi = 0 V; A-weighted − 100 − dB double differential mode; Vi = 0 V; A-weighted − 101 − dB normal mode; Vi = 0 V; A-weighted − 99 − dB − 100 − dB ambient temperature Analog-to-digital convertor Vi(rms) input voltage (RMS value) (THD+N)/S48 total harmonic distortion-plus-noise normal mode to signal ratio at fs = 48 kHz at −1 dB at 0 dB (FS) digital output at −60 dB; A-weighted double differential (THD+N)/S96 total harmonic distortion-plus-noise normal mode to signal ratio at fs = 96 kHz at −1 dB at −60 dB; A-weighted S/N48 signal-to-noise ratio at fs = 48 kHz S/N96 signal-to-noise ratio at fs = 96 kHz αcs channel separation 2000 Mar 29 4 Philips Semiconductors Preliminary specification Audio CODEC SYMBOL UDA1342TS PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Digital-to-analog convertor 0.9 − V − −90 − dB − −40 − dB − −83 − dB − −39 − dB 100 − dB output voltage (RMS value) (THD+N)/S48 total harmonic distortion-plus-noise at 0 dB to signal ratio at fs = 48 kHz at −60 dB; A-weighted total harmonic distortion-plus-noise at 0 dB to signal ratio at fs = 96 kHz at −60 dB; A-weighted S/N48 signal-to-noise ratio at fs = 48 kHz code = 0; A-weighted − S/N96 signal-to-noise ratio at fs = 96 kHz code = 0; A-weighted αcs channel separation (THD+N)/S96 at 0 dB (FS) digital input; note 1 − Vo(rms) − 99 − dB − 100 − dB Note 1. The output voltage of the DAC is proportionally to the DAC power supply voltage. 5 ORDERING INFORMATION TYPE NUMBER UDA1342TS 2000 Mar 29 PACKAGE NAME DESCRIPTION VERSION SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 5 Philips Semiconductors Preliminary specification Audio CODEC 6 UDA1342TS BLOCK DIAGRAM VDDA(ADC) handbook, full pagewidth VSSA(ADC) 3 VINL2 VDDD 1 10 VADCN 7 11 5 6 8 PGA PGA 2 4 PGA PGA ADC UDA1342TS 9 ADC DECIMATION FILTER DIGITAL MIXER (ADC) 22 23 DC-CANCELLATION FILTER DATAO BCK WS DATAI 18 13 16 L3-BUS/ I2C-BUS INTERFACE DIGITAL INTERFACE 17 VINR2 ADC ADC VINL1 VADCP VSSD 19 14 15 21 DIGITAL MIXER (DAC) DSP FEATURES 12 VINR1 IPSEL STATUS QMUTE L3MODE L3CLOCK L3DATA STATIC SYSCLK INTERPOLATION FILTER 20 NOISE SHAPER DAC VOUTL DAC 26 24 25 VDDA(DAC) 28 Vref Fig.1 Block diagram. 2000 Mar 29 TEST1 6 VOUTR 27 VSSA(DAC) MGT016 Philips Semiconductors Preliminary specification Audio CODEC 7 UDA1342TS PINNING SYMBOL PIN TYPE DESCRIPTION VSSA(ADC) 1 analog ground pad ADC analog ground VINL1 2 analog input pad ADC input left 1 VDDA(ADC) 3 analog supply pad ADC analog supply voltage VINR1 4 analog input pad ADC input right 1 VADCN 5 analog pad ADC reference voltage N VINL2 6 analog input pad ADC input left 2 VADCP 7 analog pad ADC reference voltage P VINR2 8 analog input pad ADC input right 2 IPSEL 9 5 V tolerant digital input pad channel select input: input left 1 and right 1 or input left 2 and right 2 VDDD 10 digital supply pad digital supply voltage VSSD 11 digital ground pad digital ground SYSCLK 12 5 V tolerant digital input pad system clock input: 256fs, 384fs, 512fs or 768fs L3MODE 13 5 V tolerant digital input pad L3-bus mode input or mode selection input L3CLOCK 14 5 V tolerant digital input pad L3-bus/I2C-bus clock input or clock selection input L3DATA 15 5 V tolerant open drain input/output L3-bus/I2C-bus data input/output or format selection input BCK 16 5 V tolerant digital input pad bit clock input WS 17 5 V tolerant digital input pad word select input DATAO 18 5 V tolerant 2 mA slew rate controlled digital output data output DATAI 19 5 V tolerant digital input pad data input TEST1 20 5 V tolerant digital input pad test control input; to be connected to ground STATIC 21 5 V tolerant digital input pad mode selection input: static pin control or L3-bus/I2C-bus control STATUS 22 5 V tolerant 2 mA slew rate controlled digital output general purpose output QMUTE 23 5 V tolerant digital input pad quick mute input VOUTR 24 analog output pad DAC output right VDDA(DAC) 25 analog supply pad DAC analog supply voltage VOUTL 26 analog output pad DAC output left VSSA(DAC) 27 analog ground pad DAC analog ground Vref 28 analog pad reference voltage for ADC and DAC 2000 Mar 29 7 Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS 8.2 handbook, halfpage The analog front-end of the UDA1342TS consists of two stereo ADCs with a programmable gain stage (gain from 0 to 24 dB with 3 dB steps) which can be controlled via the L3-bus/I2C-bus interface. 28 Vref VSSA(ADC) 1 27 VSSA(DAC) VINL1 2 VDDA(ADC) 3 ADC analog front-end 26 VOUTL 8.2.1 25 VDDA(DAC) VINR1 4 VADCN 5 24 VOUTR VINL2 6 23 QMUTE VADCP 7 In applications in which a 2 V (RMS) input signal is used, a 15 kΩ resistor must be used in series with the input of the ADC (see Fig.3). This forms a voltage divider together with the internal ADC resistor and ensures that only 1 V (RMS) maximum is input to the IC. Using this application for a 2 V (RMS) input signal, the gain switch must be set to 0 dB. When a 1 V (RMS) input signal is input to the ADC in the same application, the gain switch must be set to 6 dB. 22 STATUS UDA1342TS VINR2 8 21 STATIC IPSEL 9 20 TEST1 VDDD 10 19 DATAI VSSD 11 18 DATAO SYSCLK 12 17 WS L3MODE 13 16 BCK An overview of the maximum input voltages allowed against the presence of an external resistor and the setting of the gain switch is given in Table 1. Table 1 L3CLOCK 14 RESISTOR (15 kΩ) Fig.2 Pin configuration. 8.1 Application modes using input gain stage 15 L3DATA MGT017 8 APPLICATION WITH 2 V (RMS) INPUT PGA GAIN MAXIMUM INPUT VOLTAGE Present 0 dB 2 V (RMS) Present 6 dB 1 V (RMS) Absent 0 dB 1 V (RMS) Absent 6 dB 0.5 V (RMS) FUNCTIONAL DESCRIPTION System clock The UDA1342TS operates in slave mode only, this means that in all applications the system must provide the system clock. The system clock frequency is selectable and depends on the mode of operation: • L3-bus/I2C-bus mode: 256fs, 384fs, 512fs or 768fs handbook, halfpage • Static pin mode: 256fs or 384fs. The system clock must be locked in frequency to the digital interface signals. input signal 2 V (RMS) 15 kΩ VINL1, VINR1, VINL2, VINR2 2, 4, 6, 8 10 kΩ gain = 0 dB 10 kΩ Vref Remarks: • The bit clock frequency fBCK can be up to 128fs, or in other words the bit clock frequency is 128 times the word select frequency fWS or less: fBCK ≤ 128fWS UDA1342TS MGT018 • The WS edge MUST fall on the negative edge of the BCK signal at all times for proper operation of the digital interface • The UDA1342TS operates with sample frequencies from 16 to 110 kHz, however for a system clock of 768fs the sampling frequency must be limited to 55 kHz. 2000 Mar 29 Fig.3 Schematic of ADC front-end. 8 Philips Semiconductors Preliminary specification Audio CODEC 8.2.2 UDA1342TS 8.6 DOUBLE DIFFERENTIAL MODE Mute Since the UDA1342TS is equipped with two stereo ADCs, these two pairs of stereo ADCs can be used to convert a single stereo signal to a signal with a higher performance by using the ADCs in the double differential mode. Muting the DAC will result in a cosine roll-off soft mute, using 32 × 32 = 1024 samples in the normal mode: this results in 24 ms at fs = 44.1 kHz. The cosine roll-off curve is illustrated in Fig.4. This mode and the input signals, being channel 1 or 2 as input to the double differential configuration, can be selected via the L3-bus/I2C-bus interface. This cosine roll-off functions are implemented in the DAC data path before the digital mixer and before the master mute (see Fig.5). 8.3 Decimation filter (ADC) The decimation from 64fs to 1fs is performed in two stages. sin x 4 The first stage realizes a ----------- characteristic with a x decimation factor of 8. The second stage consists of three half-band filters, each decimating by a factor of 2. The filter characteristics are shown in Table 2. Table 2 mute factor 0.8 CONDITION VALUE (dB) Pass-band ripple 0 to 0.45fs ±0.01 Pass-band droop 0.45fs −0.2 Stop band >0.55fs −70 0 to 0.45fs >135 Dynamic range 0.6 0.4 0.2 Digital mixer (ADC) The two stereo ADC outputs are mixed with gain coefficients from +24 to −60 dB to be set via the microcontroller interface. 0 0 5 10 15 20 25 t (ms) In front of the mixer there is a DC filter. In order to prevent clipping, it is needed to filter out the DC component before mixing or amplifying the signals. The mixing function can be enabled via the microcontroller interface. 8.5 MGU119 1 handbook, halfpage Decimation filter characteristics ITEM 8.4 In the L3-bus and I2C-bus mode, the setting of the master mute can be overruled always by pin QMUTE. This quick mute uses the same cosine roll-off, but now for only 32 samples: this is 750 µs at fs = 44.1 kHz. Fig.4 Mute as a function of raised cosine roll-off. 8.7 Digital mixer (DAC) The ADC output signal and the digital interface input signal can be mixed without an external DSP (see Fig.5). Interpolation filter (DAC) This mixer can be controlled via the microcontroller interface. The digital interpolation filter interpolates from 1fs to 64fs by means of a cascade of FIR filters. The filter characteristics are shown in Table 3. Table 3 In order to prevent clipping when mixing two 0 dB signals, the signals are attenuated digitally by −6 dB before mixing. After mixing the signal is gained by 6 dB after the master volume. This way clipping at the digital mixer is prevented. After the 6 dB gain, the signals can clip again, but this clipping can be removed by decreasing the master volume. Interpolation filter characteristics ITEM CONDITION VALUE (dB) Pass-band ripple 0 to 0.45fs ±0.025 Stop band Dynamic range 2000 Mar 29 >0.55fs −60 0 to 0.45fs >135 9 Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS to digital interface output handbook, full pagewidth from decimation filter VOLUME AND MUTE master from digital interface input DE-EMPHASIS VOLUME AND MUTE BASS BOOST AND TREBLE + + VOLUME AND MUTE to interpolation filter MGT019 Fig.5 Digital mixer (DAC). 8.8 Noise shaper 8.10 The 5th-order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream Digital-to-Analog Converter (FSDAC). 8.9 The UDA1342TS supports the following data input/output formats for the various modes (see Fig.6). L3-bus and I2C-bus mode: • I2S-bus format with data word length of up to 24 bits • MSB-justified serial format with data word length of up to 24 bits Filter stream DAC • LSB-justified serial format with data word lengths of 16, 20 or 24 bits The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. • MSB-justified data output and LSB-justified 16, 20 and 24 bits data input. Static pin mode: • I2S-bus format with data word length of up to 24 bits • MSB-justified data output and LSB-justified 16, 20 and 24 bits data input. The output voltage of the FSDAC is proportionally to the power supply voltage. 2000 Mar 29 Digital interface 10 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... RIGHT >=8 3 2 3 MSB B2 1 >=8 BCK MSB DATA B2 MSB Philips Semiconductors 2 Audio CODEC 1 handbook, full pagewidth 2000 Mar 29 LEFT WS I2S-BUS FORMAT RIGHT LEFT WS 1 2 >=8 3 1 2 >=8 3 BCK DATA MSB B2 LSB MSB B2 LSB MSB B2 MSB-JUSTIFIED FORMAT WS LEFT RIGHT 16 15 2 11 1 16 B15 LSB MSB 15 2 1 BCK DATA MSB B2 B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS WS LEFT 20 RIGHT 19 18 17 16 15 2 1 20 B19 LSB MSB 19 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B5 B6 B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20 BITS WS LEFT 23 22 21 20 RIGHT 19 18 17 16 15 24 B23 LSB MSB 23 22 21 20 19 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B2 B3 LSB-JUSTIFIED FORMAT 24 BITS Fig.6 Serial interface input/output formats. B4 B5 B6 B7 B8 B9 B10 B23 LSB MGT020 UDA1342TS 1 2 Preliminary specification 24 Philips Semiconductors Preliminary specification Audio CODEC 8.11 UDA1342TS Sampling speed Important: in the double speed mode an input signal of 0 dB is allowed, but in the quad speed mode the input signal must be limited to −6 dB to prevent the system from clipping. The UDA1342TS operates with sample frequencies from 16 to 110 kHz. This range holds for the CODEC as a whole. The DAC part can be configured in the L3-bus and I2C-bus mode to accept 2 times and even 4 times the data speed (e.g. fs is 96 or 192 kHz), but in these modes not all of the features can be used. Some examples of the input oversampling rate settings are shown in Table 4. Table 4 Examples of the input oversampling rate settings SYSTEM CLOCK 12.288 MHz (256 × 48 kHz) 22.5792 MHz (512 × 44.1 kHz) SYSTEM CLOCK FREQUENCY SETTING SAMPLING FREQUENCY (kHz) 256fs 48 single speed all 96 double speed only master volume and mute 192 quad speed no features 44.1 single speed all 512fs 256fs 33.8688 MHz (768 × 44.1 kHz) 768fs 384fs 8.12 INPUT OVERSAMPLING RATE FEATURES SUPPORTED 88.2 single speed all 176.4 double speed only master volume and mute 44.1 single speed all 88.2 single speed all 176.4 double speed only master volume and mute Power-on reset The UDA1342TS has an internal Power-on reset circuit (see Fig.7) which resets the test control block. All the digital sound processing features and the system controlling features are set to their default setting in the L3-bus and I2C-bus mode. handbook, halfpage VDDA(DAC) 25 3.0 V 8 kΩ The reset time (see Fig.8) is determined by an external capacitor which is connected between pin Vref and ground. The reset time should be at least 1 µs for Vref < 1.25 V. When VDDA(DAC) is switched off, the device will be reset again for Vref < 0.75 V. RESET CIRCUIT Vref 28 C1 > 10 µF 8 kΩ UDA1342TS During the reset time the system clock should be running. MGU001 Fig.7 Power-on reset circuit. 2000 Mar 29 12 Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS 3.0 VDDD handbook, halfpage (V) 1.5 0 t 3.0 VDDA(DAC) (V) 1.5 0 t 3.0 Vref (V) 1.5 1.25 0.75 0 t >1 µs MGU002 Fig.8 Power-on reset timing. 8.13 Control modes Table 6 The control mode can be set with pin STATIC and pin L3MODE: FUNCTION • Static pin mode • I2C-bus mode • L3-bus mode. Table 5 Mode selection PIN STATIC PIN L3MODE LOW − L3-bus mode HIGH LOW I2C-bus mode HIGH HIGH static pin mode SELECTION PIN NAME L3-BUS MODE L3CLOCK L3CLOCK SCL clock select L3MODE L3MODE LOW level HIGH level L3DATA L3DATA SDA format select QMUTE QMUTE QMUTE format select IPSEL A0 A0 I2C-BUS MODE STATIC PIN MODE channel select All features in the L3-bus and I2C-bus mode are explained in Sections 8.15 and 8.16. The pin functions in the various modes are summarized in Table 6. 2000 Mar 29 Pin function in the selected mode 13 Philips Semiconductors Preliminary specification Audio CODEC 8.14 UDA1342TS Static pin mode 8.15 L3-bus interface All digital processing features and system controlling features of the UD1342TS can be controlled by a microcontroller via the L3-bus interface. The controllable features in the static pin mode are: • System clock frequency • Data input and output format select • ADC input channel select. The controllable features are: 8.14.1 • System clock frequency • Reset SYSTEM CLOCK SETTING SELECT • Data input and output format In the static pin mode pin L3CLOCK is used to select the system clock setting. Table 7 • Multi purpose output • ADC features System clock setting – Operation mode control PIN L3CLOCK SYSTEM CLOCK SETTING 0 256fs 1 384fs – Polarity control – Input amplifier gain control – Mixer control – DC filtering. 8.14.2 • DAC features DIGITAL INTERFACE FORMAT SELECT – Power control In the static pin mode the digital interface audio formats can be selected via pins L3DATA and QMUTE. The following interface formats can be selected (see Table 8): – Polarity control – Input data oversampling rate • I2S-bus format with data word length of up to 24 bits – Mixer position selection • MSB-justified output format and LSB-justified input format with data word length of 16, 20 or 24 bits. – Mixer control – Silence detector Table 8 Data format select in static pin mode PIN L3DATA PIN QMUTE – Volume INPUT/OUTPUT FORMAT 0 0 I2S 0 1 LSB-justified 16 bits input and MSB-justified output 1 0 LSB-justified 20 bits input and MSB-justified output 1 1 LSB-justified 24 bits input and MSB-justified output 8.14.3 – De-emphasis – Flat/min./max. switch – Quick mute mode. 8.15.1 • L3DATA: microcontroller interface data line • L3MODE: microcontroller interface mode line ADC input channel select input channel 1 (pins VINL1 and VINR1) 1 input channel 2 (pins VINL2 and VINR2) 2000 Mar 29 • L3CLOCK: microcontroller interface clock line. CHANNEL SELECT 0 INTRODUCTION The exchange of data and control information between the microcontroller and the UDA1342TS is accomplished through a serial hardware interface comprising the following pins: In the static pin mode pin IPSEL selects the ADC input channel. PIN IPSEL – Treble – Mute ADC INPUT CHANNEL SELECT Table 9 – Bass boost The UDA1342TS acts as a slave receiver or a slave transmitter. Therefore L3CLOCK and L3MODE lines transfer only input data and the L3DATA line transfers bidirectional data. 14 Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS Table 11 Selection of data transfer Information transfer via the microcontroller bus is organized LSB first and in accordance with the so called ‘L3’ format, in which two different modes of operation can be distinguished: address mode and data transfer mode. DOM TRANSFER BIT 0 BIT 1 Important: 0 0 not used • When the device is powered-up, at least one L3CLOCK pulse must be sent to the L3-bus interface to wake-up the interface prior to sending information to the device. This is only needed once after the device is powered-up. 1 0 not used 0 1 data write or prepare read 1 1 data read • Inside the microcontroller there is a hand-shake mechanism which handles proper data transfer from the microcontroller clock to destination clock domains. This means that when data is sent to the microcontroller interface, the system clock must be running. 8.15.3 REGISTER ADDRESSING After sending the device address, including the flags (DOM bits) whether the information is read or written, the data transfer mode is entered and one byte is sent with the destination register address (see Table 12) using 7 bits, and one bit which signals whether information will be read or written. • The L3-bus interface is designed in such a way that data is clocked into the device (write mode) on the positive clock edge, while the device starts the output data (read mode) on the negative clock edge. The microcontroller must read the data from the device on the positive clock edge to ensure the data is always stable. The fundamental timing for the data transfer mode is given in Fig.14. Table 12 L3-bus register address 8.15.2 DEVICE ADDRESSING LSB BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 MSB The device address mode is used to select a device for subsequent data transfer. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 bits. The fundamental timing in the address mode is shown in Fig.13. R/W DEVICE ADDRESS LSB BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 MSB 0 1 0 0 A1 A0 Important: 0 1. Each time a new destination address needs to be written, the device address must be sent again. The UDA1342TS can be set to different addresses (00 1000 or 10 1000) by setting pin IPSEL to HIGH or LOW level. In the event that the device receives a different address, it will deselect its microcontroller interface logic. 2. When addressing the device for the first time after power-up of the device, at least one L3CLOCK cycle must be given to enable the L3-bus interface. Basically, 2 types of data transfer can be defined: data transfer to the device and data transfer from the device (see Table 11). 2000 Mar 29 A2 3. Read action itself: in this case the device returns a register address prior to sending data from that register. When the first bit of the byte is at logic 0, the register address was valid and if the first bit is at logic 1 the register address was invalid. Table 10 L3-bus interface slave address IPSEL A3 2. Prepare read addressing: the first bit of the byte is at logic 1, signalling data will be read from the register indicated. • Bits 2 to 7 represent a 6-bit device address. 1 A4 1. Register addressing for L3-bus write: the first bit is at logic 0 indicating a write action to the destination register, and is followed by 7 bits indicating the register address. • Bits 0 and 1 are called Data Operation Mode (DOM) bits and represent the type of data transfer R/W A5 Basically there are 3 cases for register addressing: The device address consists of one byte, which is split up in two parts (see Table 10): DOM A6 15 Philips Semiconductors Preliminary specification Audio CODEC 8.15.4 UDA1342TS The data read mode is explained below: DATA WRITE MODE 1. One byte with the device address, being ‘01X0 1000’ where ‘X’ stands for the IPSEL value, including ‘01’ for signalling write to the device. The data write format is given in Table 13 and illustrated in Fig.9. When writing data to a device four bytes must be sent: 2. One byte is sent with the register address which needs to be read. This byte starts with a logic 1, which indicates that there will be a read action from the register. 1. One byte with the device address, being ‘01X0 1000’ where ‘X’ stands for the IPSEL value, including ‘01’ for signalling write to the device. 2. One byte starting with a logic 0 for signalling write followed by 7 bits indicating the register address. 3. One byte with the device address including ‘11’ is sent to the device. The ‘11’ indicates that the device must write data to the microcontroller. 3. One byte which is the Most Significant Data (MSD) byte 1. 4. The device now writes the requested register address on the L3-bus, indicating whether the requested register was valid (logic 0) or invalid (logic 1). 4. One byte which is the Least Significant Data (LSD) byte 2. 8.15.5 5. The device writes data from the requested register to the L3-bus with the MSD byte 1 first, followed by the LSD byte 2. DATA READ MODE The data write format is given in Table 14 and illustrated in Fig.10. When reading from the device, a prepare read must first be done. After the prepare read, the device address is sent again. The device then returns with the register address, indicating whether the address was valid or not, and the data of the register. Table 13 L3-bus format for data write FIRST IN TIME L3MODE LAST IN TIME DATA TYPE BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 Address device address 0 1 IPSEL 0 1 0 0 0 Data transfer 1 register address 0 A6 A5 A4 A3 A2 A1 A0 Data transfer 2 MSD byte 1 D15 D14 D13 D12 D11 D10 D9 D8 Data transfer 3 LSD byte 2 D7 D6 D5 D4 D3 D2 D1 D0 Table 14 L3-bus format for prepare read and read data FIRST IN TIME L3MODE LAST IN TIME DATA TYPE BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 Prepare read Address device address 0 1 IPSEL 0 1 0 0 0 Data transfer 1 register address 1 A6 A5 A4 A3 A2 A1 A0 Read data Address device address 1 1 IPSEL 0 1 0 0 0 Data transfer 1 register address 0/1 A6 A5 A4 A3 A2 A1 A0 Data transfer 2 MSD byte 1 D15 D14 D13 D12 D11 D10 D9 D8 Data transfer 3 LSD byte 2 D7 D6 D5 D4 D3 D2 D1 D0 2000 Mar 29 16 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... L3CLOCK Philips Semiconductors Audio CODEC 2000 Mar 29 L3 wake-up pulse after power-up L3MODE register address device address 0 L3DATA 1 data byte 1 data byte 2 0 MGS753 DOM bits write Fig.9 Data write mode for L3-bus version 2. 17 L3CLOCK L3MODE register address device address 1 DOM bits read 1 1 data byte 1 data byte 2 0/1 valid/non-valid prepare read send by the device Fig.10 Data read mode for L3-bus version 2. MGS754 UDA1342TS 0 1 register address Preliminary specification L3DATA device address Philips Semiconductors Preliminary specification Audio CODEC 8.16 UDA1342TS 8.16.3 I2C-bus interface The UDA1342TS register address format is given in Table 16. Besides the L3-bus mode the UDA1342TS supports the I2C-bus mode; all the features can be controlled by the microcontroller with the same register addresses as used in the L3-bus mode. Table 16 I2C-bus register address format The exchange of data and control information between the microcontroller and the UDA1342TS in the I2C-bus mode is accomplished through a serial hardware interface comprising the following pins and signals: MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB 0 • L3DATA: Serial Data line (SDA). The clock and data timing of the I2C-bus transfer is shown in Fig.15. ADDRESSING Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the START procedure (S). 8.16.2 SLAVE ADDRESS The UDA1342TS acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is an input or output signal (bidirectional line). The UDA1342TS slave address format is shown in Table 15. Table 15 I2C-bus slave address format MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB 0 0 1 1 0 1 IPSEL R/W The slave address bit IPSEL corresponds to the hardware address pin IPSEL which allows selecting the slave address. 2000 Mar 29 A6 A5 A4 A3 A2 A1 A0 The register mapping of the I2C-bus and L3-bus interfaces is the same (see Section 9). • L3CLOCK: Serial Clock Line (SCL) 8.16.1 REGISTER ADDRESS 18 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... The write cycle is used to write data from the microcontroller to the internal registers. The I2C-bus format for a write cycle is shown in Table 17. The device and register addresses are one byte each, data is always two bytes (2-bytes data). The format of the write cycle is as follows: 1. The microcontroller starts with a START condition S. 2. The first byte (8 bits) contains the device address 0011 01X and a write command (bit R/W = 0). 3. This is followed by an acknowledge (A) from the UDA1342TS. Philips Semiconductors WRITE CYCLE Audio CODEC 2000 Mar 29 8.16.4 4. The microcontroller then writes the register address (8 bits) where writing of the register content of the UDA1342TS must start. 5. The UDA1342TS acknowledges this register address. 6. The microcontroller sends 2-bytes data with the Most Significant Data (MSD) byte first and then the Least Significant Data (LSD) byte, where each byte is acknowledged by the UDA1342TS. 7. After the last acknowledge the UDA1342TS frees the I2C-bus and the microcontroller can generate a STOP condition (P). Table 17 Master transmitter writes to UDA1342TS registers ACKNOWLEDGE FROM UDA1342TS 19 S DEVICE ADDRESS R/W 0011 01X 0 8 bits REGISTER ADDRESS A 0XXX XXXX 8 bits DATA(1) A MSD1 8 bits A LSD1 8 bits A MSD2 8 bits A LSD2 8 bits A MSDn 8 bits A LSDn A P 8 bits Note 1. Auto increment of the register address is carried out if repeated groups of 2 bytes are transmitted. Preliminary specification UDA1342TS This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... The read cycle is used to read data from the internal registers of the UDA1342TS to the microcontroller. The I2C-bus format for a read cycle is shown in Table 18. The format of the read cycle is as follows: 1. The microcontroller starts with a START condition S. 2. The first byte (8 bits) contains the device address 001 01X and a write command (bit R/W = 0). 3. This is followed by an acknowledge (A) from the UDA1342TS. Philips Semiconductors READ CYCLE Audio CODEC 2000 Mar 29 8.16.5 4. The microcontroller then writes the register address where reading of the register content of the UDA1342TS must start. 5. The UDA1342TS acknowledges this register address. 6. Then the microcontroller generates a repeated START (Sr). 7. Again the device address 0011 01X is given, but this time followed by a read command (bit R/W = 1). 8. The UDA1342TS sends the two-byte data with the Most Significant Data (MSD) byte first and then the Least Significant Data (LSD) byte, where each byte is acknowledged by the microcontroller (master). 9. The microcontroller stops this cycle by generating a negative acknowledge (NA). 10. The UDA1342TS then frees the I2C-bus and the microcontroller can generate a STOP condition (P). 20 Table 18 Master transmitter reads from UDA1342TS registers ACKNOWLEDGE FROM UDA1342TS DEVICE R/W ADDRESS S 0011 01X 8 bits 0 REGISTER ADDRESS A 0XXX XXXX A Sr 8 bits ACKNOWLEDGE FROM MASTER DEVICE R/W ADDRESS 0011 01X 8 bits 1 DATA(1) A MSD1 8 bits A LSD1 8 bits A MSD2 8 bits A LSD2 8 bits A MSDn 8 bits A LSDn NA P 8 bits Note 1. Auto increment of the register address is carried out if repeated groups of 2 bytes are transmitted. Preliminary specification UDA1342TS This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... The addresses of the control registers with default values at Power-on reset are shown in Table 19. Functions of the registers are shown in Tables 20 to 45. Table 19 Register map ADDRESS 00H 01H FUNCTION system sub system 02H to 0FH reserved D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RST QS MDC DC AM2 AM1 AM0 − 0 0 1 1 0 1 PAD 0 SC1 SC0 IF2 IF1 IF0 DP PDA 0 0 0 0 0 0 0 1 0 − − − − − − − − MIX SD1 − − − − − − − − 0 0 − − − − − − − − − − 0 0 0 0 0 0 − − − − − − M0 BB3 BB2 BB1 BB0 TR1 TR0 MT QM DE2 OS1 OS0 MPS SD0 MP1 MP0 10H DAC features M1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11H DAC master volume VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0 VR7 VR6 VR5 VR4 VR3 VR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VB7 VB6 VB5 VB4 VB3 VB2 VB1 VB0 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13H to 1FH reserved − − − − − − − − − − − − − − − − 20H ADC input and mixer gain channel 1 0 0 0 0 IA3 IA2 IA1 IA0 0 0 0 0 0 0 0 0 ADC input and mixer gain channel 2 0 0 0 0 IB3 IB2 IB1 IB0 0 0 0 0 0 0 0 0 12H 21 21H DAC mixer volume SDS MTB MTA DE1 DE0 0 0 VR1 VR0 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 0 0 0 0 0 0 0 0 MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0 0 0 0 0 0 0 0 0 22H to 2FH reserved − − − − − − − − − − − − − − − − 30H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 − − − − − − − − − − − − − − − − evaluation 31H to FFH reserved Philips Semiconductors REGISTER MAPPING Audio CODEC 2000 Mar 29 9 Preliminary specification UDA1342TS Philips Semiconductors Preliminary specification Audio CODEC 9.1 UDA1342TS 9.5 Reset I2C-bus registers A 1-bit value to initialize the L3-bus and except the system register (00H) with default settings by setting bit RST = 1. A 3-bit value to select the mode of the ADC. Table 24 ADC mode AM2 AM1 AM0 Table 20 Reset bit RST 9.2 FUNCTION 0 no reset 1 reset registers to default Quick mode switch A 1-bit value to enable the quick mode change of the ADC. The soft mode change works only between modes if bit AM2 = 1. Table 21 Quick mode switch QS ADC mode FUNCTION 0 soft mode change 1 quick mode change FUNCTION 0 0 0 ADC power-off 0 0 1 input 1 select (input 2 off) 0 1 0 input 2 select (input 1 off) 0 1 1 not used 1 0 0 channel swap and signal inversion 1 0 1 input 1 select (double differential mode) 1 1 0 input 2 select (double differential mode) 1 1 1 mixing mode 9.6 ADC polarity A 1-bit value to control the ADC polarity. Table 25 Polarity control of the ADC 9.3 Bypass mixer DC filter PAD A 1-bit value to disable the DC filter of the ADC mixer. This DC filter is in front of the mixer to prevent clipping inside the mixer due to DC signals. Table 22 Mixer DC filtering MDC 9.7 enable mixer DC filtering 1 disable mixer DC filtering A 1-bit value to enable the DC filter of the ADC output. This DC filter is inside the decimation filter. Table 23 DC-filtering FUNCTION 0 disable output DC filtering 1 enable output DC filtering 2000 Mar 29 inverting Table 26 System clock frequency settings DC filter DC non-inverting 1 System clock frequency SC1 9.4 0 A 2-bit value to select the external clock frequency. FUNCTION 0 FUNCTION 22 SC0 FUNCTION 0 0 256fs 0 1 384fs 1 0 512fs 1 1 768fs Philips Semiconductors Preliminary specification Audio CODEC 9.8 UDA1342TS Data format 9.11 DAC polarity A 3-bit value to select the data format. A 1-bit value to control the DAC polarity. Table 27 Data format selection Table 29 Polarity control of DAC IF2 IF1 IF0 PDA FUNCTION FUNCTION 0 0 0 I2S-bus 0 0 1 LSB-justified16 bits 0 1 0 LSB-justified 20 bits 0 1 1 LSB-justified 24 bits 9.12 1 0 0 MSB-justified 1 0 1 LSB-justified 16 bits input and MSB-justified output A 1-bit value to select the mixing position of the ADC signal in the DAC. 1 1 0 LSB-justified 20 bits input and MSB-justified output 1 1 1 LSB-justified 24 bits input and MSB-justified output 9.9 inverting DAC mixing position switch MPS 9.13 A 1-bit value to disable the DAC to reduce power consumption. The DAC power-off is not recommended when the DAC outputs are DC loaded. FUNCTION 0 before sound features 1 after sound features DAC mixer A 1-bit value to enable the digital mixer of the DAC. Table 31 DAC mixer MIX Table 28 DAC power control 9.10 non-inverting 1 Table 30 DAC mixing position switch DAC power control DP 0 FUNCTION 0 DAC power-off 1 DAC power-on FUNCTION 0 disable mixer 1 enable mixer Input oversampling rate A 2-bit value to select the oversampling rate of the input signal (see Table 32). In the quad speed input rate, care must be taken that the input signal is smaller than −5.67 dB (FS). Table 32 Input oversampling rate OS0 0 0 single speed 16 to 110 kHz supported all digital filters and all features, including mixing are available 0 1 double speed 32 to 220 kHz not supported first digital filter is bypassed, only master volume and master mute features are available 1 0 quad speed 64 to 440 kHz not supported no mixing nor any sound feature is supported 1 1 reserved − − − 2000 Mar 29 MODE SAMPLING FREQUENCY OS1 ADC 23 DAC FEATURES Philips Semiconductors Preliminary specification Audio CODEC 9.14 UDA1342TS Table 36 Bass boost settings Silence detection period A 2-bit value to define the silence period for the silence detector. BASS BOOST (dB) BB3 Table 33 Silence detection period SD1 SD0 0 0 3200 samples 0 1 4800 samples 1 0 9600 samples 1 9.15 1 FUNCTION 19200 samples Multi purpose output A 2-bit value to select the output signal on pin STATUS. Table 34 Multi purpose output selection FUNCTION BB2 BB1 BB0 FLAT MIN. MAX. 0 0 0 0 0 0 0 0 0 0 1 0 2 2 0 0 1 0 0 4 4 0 0 1 1 0 6 6 0 1 0 0 0 8 8 0 1 0 1 0 10 10 0 1 1 0 0 12 12 0 1 1 1 0 14 14 1 0 0 0 0 16 16 1 0 0 1 0 18 18 1 0 1 0 0 18 20 1 0 1 1 0 18 22 MP1 MP0 0 0 no output 1 1 0 0 0 18 24 0 1 overflow (ADC) detection 1 1 0 1 0 18 24 1 1 0 0 18 24 1 1 0 18 24 1 0 reserved 1 1 1 digital silence detection 1 1 9.16 Mode 9.18 Treble A 2-bit value to program the treble setting. The used set depends on the setting of bits M1 and M0. At fs = 44.1 kHz the −3 dB point for minimum setting is 3.0 kHz and the −3 dB point for maximum setting is 1.5 kHz. The default value is 00. A 2-bit value to program the mode of the sound processing filters of bass boost and treble. Table 35 Flat/min./max. switch position M1 M0 FUNCTION 0 0 flat 0 1 min. 1 0 min. 1 1 max. 9.17 Table 37 Treble settings TREBLE (dB) TR1 Bass boost A 4-bit value to program the bass boost settings. The used set depends on the setting of bits M1 and M0. At fs = 44.1 kHz the −3 dB point for minimum setting is 250 Hz and the −3 dB point for maximum setting is 300 Hz. The default value is 0000. 2000 Mar 29 24 TR0 FLAT MIN. MAX. 0 0 0 0 0 0 1 0 2 2 1 0 0 4 4 1 1 0 6 6 Philips Semiconductors Preliminary specification Audio CODEC 9.19 UDA1342TS Silence detector switch 9.23 A 1-bit value to enable the silence detector. Two 4-bit values to program the gain of the input amplifiers. Bits IA applies for input amplifier A and bits IB to input amplifier B. Table 38 Silence detector switch SDS 9.20 FUNCTION 0 disable silence detector 1 enable silence detector Table 42 ADC input amplifier gain settings Mute Three 1-bit values to enable the digital mute. Bit MT is the master mute, using bit MTA the signal from the digital interface can be soft muted when the DAC mixer is enabled and using bit MTB the signal from ADC can be soft muted. Table 39 Mute MT MTA MTB 9.21 FUNCTION 0 no muting 1 muting Quick mute mode A 1-bit value to enable the quick mute function of the master mute. Table 40 Quick mute mode settings QM 9.22 FUNCTION 0 soft mute mode 1 quick mute mode De-emphasis A 3-bit value to enable the digital de-emphasis filter. Table 41 De-emphasis settings DE2 DE1 DE0 0 0 0 no de-emphasis 0 0 1 de-emphasis at fs = 32 kHz 0 1 0 de-emphasis at fs = 44.1 kHz 0 1 1 de-emphasis at fs = 48 kHz 1 0 0 de-emphasis at fs = 96 kHz 2000 Mar 29 ADC input amplifier gain FUNCTION 25 IA3 IB3 IA2 IB2 IA1 IB1 IA0 IB0 AMPLIFIER GAIN (dB) 0 0 0 0 0 0 0 0 1 3 0 0 1 0 6 0 0 1 1 9 0 1 0 0 12 0 1 0 1 15 0 1 1 0 18 0 1 1 1 21 1 0 0 0 24 Philips Semiconductors Preliminary specification Audio CODEC 9.24 UDA1342TS DAC volume control Four 8-bit values to program the volume attenuations. The range is from 0 to −66 dB and −∞ dB in steps of 0.25 dB. Bits VL and VR are master volumes for the left and right channels. Table 43 DAC volume settings VL7 VR7 VL6 VR6 VL5 VR5 VL4 VR4 VL3 VR3 VL2 VR2 VL1 VR1 VL0 VR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 −0.25 0 0 0 0 0 0 1 0 −0.50 0 0 0 0 0 0 1 1 −0.75 0 0 0 0 0 1 0 0 −1.00 : : : : : : : : : 1 1 0 0 0 1 0 0 −49.0 1 1 0 0 0 1 0 1 −49.25 1 1 0 0 0 1 1 0 −49.5 1 1 0 0 0 1 1 1 −49.75 1 1 0 0 1 0 0 0 −50.0 1 1 0 0 1 1 0 0 −52.0 1 1 0 1 0 0 0 0 −54.0 1 1 0 1 0 1 0 0 −57.0 1 1 0 1 1 0 0 0 −60.0 1 1 0 1 1 1 0 0 −66.0 1 1 1 0 0 0 0 0 −∞ : : : : : : : : : 1 1 1 1 1 1 1 1 −∞ 9.25 VOLUME (dB) DAC mixer volume control Four 8-bit values to program the volume attenuations. The range is from 0 to −60 dB and −∞ dB in steps of 0.25 dB. When the DAC mixer is enabled, the signal from the digital interface can be controlled by bits VA and the signal from the ADC can be controlled by bits VB. Table 44 DAC volume settings VA7 VB7 VA6 VB6 VA5 VB5 VA4 VB4 VA3 VB3 VA2 VB2 VA1 VB1 VA0 VB0 VOLUME (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 −0.25 0 0 0 0 0 0 1 0 −0.50 0 0 0 0 0 0 1 1 −0.75 0 0 0 0 0 1 0 0 −1.00 : : : : : : : : : 1 0 1 0 1 1 0 0 −43.0 1 0 1 0 1 1 0 1 −43.25 2000 Mar 29 26 Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS VA7 VB7 VA6 VB6 VA5 VB5 VA4 VB4 VA3 VB3 VA2 VB2 VA1 VB1 VA0 VB0 VOLUME (dB) 1 0 1 0 1 1 1 0 −43.5 1 0 1 0 1 1 1 1 −43.75 1 0 1 1 0 0 0 0 −44.0 1 0 1 1 0 1 0 0 −46.0 1 0 1 1 1 0 0 0 −48.0 1 0 1 1 1 1 0 0 −51.0 1 1 0 0 0 0 0 0 −54.0 1 1 0 0 0 1 0 0 −60.0 1 1 0 0 1 0 0 0 −∞ : : : : : : : : : 1 1 1 1 1 1 1 1 −∞ 9.26 ADC mixer gain control Two 8-bit values to program the channel 1 and 2 mixing, when the mixer mode is selected. Bits MA applies to channel 1 and bits MB to channel 2. The range is from +24 to −63.5 dB and −∞ dB in steps of 0.5 dB. Table 45 ADC mixer gain settings MA7 MB7 MA6 MB6 MA5 MB5 MA4 MB4 MA3 MB3 MA2 MB2 MA1 MB1 MA0 MB0 MIXER GAIN (dB) 0 0 1 1 0 0 0 0 +24.0 0 0 1 0 1 1 1 1 +23.5 0 0 1 0 1 1 1 0 +23.0 : : : : : : : : : 0 0 0 0 0 0 1 0 +1.0 0 0 0 0 0 0 0 1 +0.5 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 −0.5 : : : : : : : : : 1 0 0 0 0 1 0 0 −62.0 1 0 0 0 0 0 1 1 −62.5 1 0 0 0 0 0 1 0 −63.0 1 0 0 0 0 0 0 1 −63.5 1 0 0 0 0 0 0 0 −∞ 2000 Mar 29 27 Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT − 4 V maximum crystal temperature − 150 °C Tstg storage temperature −65 +125 °C Tamb ambient temperature −40 +85 °C Ves electrostatic handling voltage note 2 −1100 +1100 V note 3 −250 +250 V - 200 mA output short-circuited to VSSA(DAC) − 450 mA output short-circuited to VDDA(DAC) − 325 mA VDD supply voltage Txtal(max) note 1 Ilu(prot) latch-up protection current Tamb = 125 °C; VDD = 3.6 V Isc(DAC) short-circuit current of DAC Tamb = 0 °C; VDD = 3 V; note 4 Notes 1. All supply connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor. 3. Equivalent to discharging a 200 pF capacitor via a 0.75 µH series inductor. 4. DAC operation after short-circuiting cannot be warranted. 11 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. 12 QUALITY SPECIFICATION In accordance with “SNW-FQ-611-E”. 13 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient in free air VALUE UNIT 90 K/W 14 DC CHARACTERISTICS VDDD = VDDA(ADC) = VDDA(DAC) = 3.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages measured with respect to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies; note 1 VDDA(ADC) ADC analog supply voltage 2.7 3.0 3.6 V VDDA(DAC) DAC analog supply voltage 2.7 3.0 3.6 V VDDD 2.7 3.0 3.6 V digital supply voltage 2000 Mar 29 28 Philips Semiconductors Preliminary specification Audio CODEC SYMBOL IDDA(ADC) UDA1342TS PARAMETER ADC analog supply current IDDA(DAC) DAC analog supply current IDDD digital supply current CONDITIONS MIN. TYP. MAX. UNIT 1 ADC + 1 PGA enabled − 10 − mA 2 ADCs + 2 PGAs enabled − 20 − mA all ADCs + all PGAs power-down − 200 − µA operating − 6.0 − mA DAC power-down − 250 − µA operating − 9.0 − mA ADC power-down − 4.5 − mA DAC power-down − 5.5 − mA 2.0 − 5.5 V Digital input pins (5 V tolerant TTL compatible) VIH HIGH-level input voltage VIL LOW-level input voltage −0.5 − +0.8 V ILI input leakage current − − 1 µA Ci input capacitance − − 10 pF Digital output pins VOH HIGH-level output voltage IOH = −2 mA 0.85VDDD − − V VOL LOW-level output voltage IOL = 2 mA − 0.4 V with respect to VSSA(ADC); note 2 0.45VDDA 0.5VDDA 0.55VDDA V − 5 − − Reference voltage Vref reference voltage Ro(Vref) output resistance on pin Vref kΩ Analog-to-digital converter VADCP positive reference voltage of the ADC − VDDA(ADC) − V VADCN negative reference voltage of the ADC − 0.0 − V Ri input resistance − 10 − kΩ Ci input capacitance − 24 − pF (THD + N)/S < 0.1% − tbf − mA 3 − − kΩ note 3 − − 50 pF Digital-to-analog converter Io(max) maximum output current RL load resistance CL load capacitance Notes 1. All supply connections must be made to the same power supply unit. 2. VDDA = VDDA(DAC) = VDDA(ADC). 3. When higher capacitive loads must be driven, a 100 Ω resistor must be connected in series with the DAC output in order to prevent oscillations in the output operational amplifier. 2000 Mar 29 29 Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS 15 AC CHARACTERISTICS VDDD = VDDA(ADC) = VDDA(DAC) = 3.0 V; fi = 1 kHz at −1 dB; Tamb = 25 °C; RL = 5 kΩ; all voltages measured with respect to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Analog-to-digital converter Vi(rms) input voltage (RMS value) 0 dB setting − 900 − mV 3 dB setting − 640 − mV 6 dB setting − 450 − mV 9 dB setting − 320 − mV 12 dB setting − 225 − mV 15 dB setting − 160 − mV 18 dB setting − 122.5 − mV 21 dB setting − 80 − mV 24 dB setting − 61.25 − mV − <0.1 − dB ∆Vi unbalance between channels (THD + N)/S48 normal mode; at −1 dB total harmonic distortion-plus-noise to 0 dB setting signal ratio at fs = 48 kHz 3 dB setting − −90 − dB − tbf − dB 6 dB setting − tbf − dB 9 dB setting − tbf − dB 12 dB setting − tbf − dB 15 dB setting − tbf − dB 18 dB setting − tbf − dB 21 dB setting − tbf − dB 24 dB setting − tbf − dB 0 dB setting − −40 − dB 3 dB setting − tbf − dB 6 dB setting − tbf − dB 9 dB setting − tbf − dB 12 dB setting − tbf − dB 15 dB setting − tbf − dB 18 dB setting − tbf − dB 21 dB setting − tbf − dB 24 dB setting − tbf − dB at 0 dB gain − −93 − dB at 0 dB gain; −60 dB input; A-weighted − −41 − dB normal mode; at −60 dB; A-weighted double differential mode 2000 Mar 29 30 Philips Semiconductors Preliminary specification Audio CODEC SYMBOL (THD + N)/S96 S/N48 PARAMETER UDA1342TS CONDITIONS total harmonic normal mode distortion-plus-noise to at 0 dB gain signal ratio at fs = 96 kHz at −60 dB; A-weighted signal-to-noise ratio at fs = 48 kHz S/N96 signal-to-noise ratio at fs = 96 kHz αcs channel separation PSRR power supply rejection ratio MIN. TYP. MAX. UNIT − −84 − dB − −40 − dB normal mode − 100 − dB double differential mode − 101 − dB − 99 − dB − 100 − dB fripple = 1 kHz; Vripple = 30 mV (p-p) − 30 − dB at 0 dB (FS) digital input − 0.9 − V Vi = 0 V; A-weighted Vi = 0 V; A-weighted; normal mode Digital-to-analog converter Vo(rms) output voltage (RMS value) ∆Vo unbalance between channels − <0.1 − dB (THD+N)/S48 at 0 dB total harmonic distortion-plus-noise to at −60 dB; A-weighted signal ratio at fs = 48 kHz − −90 − dB − −40 − dB total harmonic at 0 dB distortion-plus-noise to at −60 dB; A-weighted signal ratio at fs = 96 kHz − −83 − dB − −39 − dB S/N48 signal-to-noise ratio at fs = 48 kHz code = 0; A-weighted − 100 − dB S/N96 signal-to-noise at fs = 96 kHz code = 0; A-weighted − 99 − dB αcs channel separation − 100 − dB PSRR power supply rejection ratio − 60 − dB (THD+N)/S96 2000 Mar 29 fripple = 1 kHz; Vripple = 30 mV (p-p) 31 Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS 16 TIMING VDDD = VDDA(ADC) = VDDA(DAC) = 2.7 to 3.6 V; Tamb = −20 to +85 °C; all voltages referenced to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT System clock timing; note 1 (see Fig.11) Tsys tCWL tCWH system clock cycle time system clock LOW time system clock HIGH time fsys = 256fs 35 81 250 ns fsys = 384fs 23 54 170 ns fsys = 512fs 17 41 130 ns fsys = 768fs 17 27 90 ns fsys < 19.2 MHz 0.3Tsys − 0.7Tsys ns fsys ≥ 19.2 MHz 0.4Tsys − 0.6Tsys ns fsys < 19.2 MHz 0.3Tsys − 0.7Tsys ns fsys ≥ 19.2 MHz 0.4Tsys − 0.6Tsys ns − − 128fs Hz − 1⁄ s Serial interface input/output data timing (see Fig.12) fBCK bit clock frequency Tcy(s) = sample − frequency cycle time Tcy(BCK) bit clock cycle time tBCKH bit clock HIGH time 30 − − ns tBCKL bit clock LOW time 30 − − ns tr rise time − − 20 ns tf fall time − − 20 ns tsu(WS) word select set-up time 10 − − ns th(WS) word select hold time 10 − − ns tsu(DATAI) data input set-up time 10 − − ns th(DATAI) data input hold time 10 − − ns th(DATAO) data output hold time 0 − − ns td(DATAO-BCK) data output to bit clock delay − − 30 ns td(DATAO-WS) data output to word select delay − − 30 ns 128Tcy(s) L3-bus interface timing (see Figs 13 and 14) tr rise time note 2 − − 10 ns/V tf fall time note 2 − − 10 ns/V Tcy(CLK)L3 L3CLOCK cycle time note 3 500 − − ns tCLK(L3)H L3CLOCK HIGH time 250 − − ns tCLK(L3)L L3CLOCK LOW time 250 − − ns tsu(L3)A L3MODE set-up time in address mode 190 − − ns th(L3)A L3MODE hold time in address mode 190 − − ns tsu(L3)D L3MODE set-up time in data transfer mode 190 − − ns th(L3)D L3MODE hold time in data transfer mode 190 − − ns 2000 Mar 29 32 Philips Semiconductors Preliminary specification Audio CODEC SYMBOL UDA1342TS PARAMETER CONDITIONS MIN. TYP. MAX. UNIT tstp(L3) L3MODE stop time in data transfer mode 190 − − ns tsu(L3)DA L3DATA set-up time in address and data transfer mode 190 − − ns th(L3)DA L3DATA hold time in address and data transfer mode 30 − − ns tsu(L3)R L3DATA set-up time for read data 50 − − ns th(L3)R L3DATA hold time for read data 360 − − ns ten(L3)R L3DATA enable time for read data 380 − − ns tdis(L3)R L3DATA disable time for read data 50 − − ns I2C-bus interface timing (see Fig.15) fSCL SCL clock frequency 0 − 400 kHz tLOW SCL LOW time 1.3 − − µs tHIGH SCL HIGH time 0.6 − − µs tr rise time SDA and SCL note 4 20 + 0.1Cb − 300 ns tf fall time SDA and SCL note 4 20 + 0.1Cb − 300 ns tHD;STA hold time START condition note 5 0.6 − − µs tSU;STA set-up time repeated START 0.6 − − µs tSU;STO set-up time STOP condition 0.6 − − µs tBUF bus free time between a STOP and START condition 1.3 − − µs tSU;DAT data set-up time 100 − − ns tHD;DAT data hold time 0 − − µs tSP pulse width of spikes 0 − 50 ns Cb capacitive load for each bus line − − 400 pF note 6 Notes 1. The typical value of the timing is specified at 48 kHz sampling frequency. 2. In order to prevent digital noise interfering with the L3-bus communication, it is best to have the rise and fall times as small as possible. 3. When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to 1⁄64fs cycle. 4. Cb is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF. 5. After this period, the first clock pulse is generated. 6. To be suppressed by the input filter. 2000 Mar 29 33 Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS t CWH handbook, full pagewidth MGR984 t CWL Tsys Fig.11 Timing of system clock. handbook, full pagewidth WS tr t BCKH t d(DATAO-BCK) t h(WS) tf t su(WS) BCK t BCKL Tcy(BCK) t d(DATAO-WS) t h(DATAO) DATAO t su(DATAI) t h(DATAI) DATAI MGS756 Fig.12 Serial interface input data timing. 2000 Mar 29 34 Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS handbook, full pagewidth L3MODE tsu(L3)A th(L3)A tCLK(L3)L tsu(L3)A tCLK(L3)H th(L3)A L3CLOCK Tcy(CLK)(L3) tsu(L3)DA th(L3)DA BIT 7 BIT 0 L3DATA MGL723 Fig.13 Timing of address mode. tstp(L3) handbook, full pagewidth L3MODE tCLK(L3)L th(L3)D Tcy(CLK)L3 tCLK(L3)H tsu(L3)D L3CLOCK tsu(L3)DA th(L3)DA L3DATA write BIT 7 BIT 0 L3DATA read ten(L3)R tsu(L3)R th(L3)R tdis(L3)R MGU015 Fig.14 Timing of data transfer mode for write and read. 2000 Mar 29 35 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... t BUF t LOW tr tf t HD;STA t SP Philips Semiconductors Audio CODEC 2000 Mar 29 SDA SCL t HD;STA P S t HD;DAT t HIGH t SU;DAT t SU;STA t SU;STO Sr MBC611 P Fig.15 Timing of the I2C-bus transfer. 36 Preliminary specification UDA1342TS Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS 17 APPLICATION INFORMATION handbook, full pagewidth L1 +3 V BLM32A07 L2 BLM32A07 ground D VDDA VDDD VDDA C12 100 µF (16 V) R16 1Ω C10 C13 100 µF (16 V) A R17 220 Ω C11 100 µF (16 V) 100 µF (16 V) 100 µF (16 V) C23 C24 C22 100 nF (63 V) 100 nF (63 V) 100 nF (63 V) VADCP VSSA(DAC) VDDA(DAC) VSSA(ADC) VDDA(ADC) VADCN R13 system clock SYSCLK 47 Ω DATAO BCK I2S-bus WS DATAI R1 left C2 R2 47 µF (16 V) 0Ω right VINL2 C4 R4 47 µF (16 V) 0Ω 27 28 C20 100 nF (63 V) L3DATA C7 47 µF (16 V) 17 19 C5 R5 47 µF (16 V) 100 Ω VOUTL 2 left output R11 10 kΩ UDA1342TS 9 22 13 14 21 15 20 10 VSSD VDDD C21 100 nF (63 V) C8 100 µF (16 V) R14 1Ω VDDD Fig.16 Application diagram. 37 MGT021 C6 R6 47 µF (16 V) 100 Ω VOUTR 6 23 L3CLOCK Vref 16 11 2000 Mar 29 25 18 VINR2 8 L3MODE I2C-bus 7 12 VINR1 4 0Ω 47 µF (16 V) right L3-bus 5 24 R3 left input 2 VINL1 0Ω 47 µF (16 V) C3 3 26 C1 input 1 1 R15 1Ω C9 IPSEL QMUTE STATUS STATIC TEST1 R12 10 kΩ right output Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS 18 PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 2000 Mar 29 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 MO-150 38 o Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS If wave soldering is used the following conditions must be observed for optimal results: 19 SOLDERING 19.1 Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 19.2 – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.3 19.4 Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. 2000 Mar 29 Manual soldering When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 39 Philips Semiconductors Preliminary specification Audio CODEC 19.5 UDA1342TS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Mar 29 40 Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS 20 DATA SHEET STATUS DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Note 1. Please consult the most recently issued data sheet before initiating or completing a design. 21 DEFINITIONS 22 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 23 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2000 Mar 29 41 Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS NOTES 2000 Mar 29 42 Philips Semiconductors Preliminary specification Audio CODEC UDA1342TS NOTES 2000 Mar 29 43 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/25/01/pp44 Date of release: 2000 Mar 29 Document order number: 9397 750 06651