March 2001 PRELIMINARY ML4800 Power Factor Correction and PWM Controller Combo GENERAL DESCRIPTION FEATURES The ML4800 is a controller for power factor corrected, switched mode power supplies. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with IEC1000-3-2 specification. Intended as a BiCMOS version of the industry-standard ML4824, the ML4800 includes circuits for the implementation of leading edge, average current, “boost” type power factor correction and a trailing edge, pulse width modulator (PWM). It also includes a TriFault Detect™ function to help ensure that no unsafe conditions will result from single component failure in the PFC. Gate-drivers with 1A capabilities minimize the need for external driver circuits. Low power requirements improve efficiency and reduce component costs. ■ Internally synchronized leading-edge PFC and trailingedge PWM in one IC ■ TriFault Detect™ for UL1950 compliance and enhanced safety ■ Slew rate enhanced transconductance error amplifier for ultra-fast PFC response ■ Low power: 200µA startup current, 5.5mA operating current ■ Low total harmonic distortion, high PF ■ Reduced ripple current in storage capacitor between PFC and PWM sections ■ Average current, continuous boost leading edge PFC ■ PWM configurable for current-mode or voltage mode operation ■ Current fed gain modulator for improved noise immunity ■ Overvoltage and brown-out protection, UVLO, and soft start An over-voltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brownout protection. The PWM section can be operated in current or voltage mode, at up to 250kHz, and includes an accurate 50% duty cycle limit to prevent transformer saturation. BLOCK DIAGRAM 16 VFB 13 1 POWER FACTOR CORRECTOR IEAO VEAO VEA 15 0.5V - 2.5V IEA 1.6kΩ IAC - GAIN MODULATOR VRMS 2.75V - -1V + - 7.5V REFERENCE S Q R Q S Q R Q S Q R Q VREF 14 PFC OUT 1.6kΩ ISENSE 17V + + - 2 4 OVP TRI-FAULT - + + + VCC VCC PFC ILIMIT 12 3 RAMP 1 OSCILLATOR 7 RAMP 2 DUTY CYCLE LIMIT 8 VDC 6 1.25V VCC SS - 25µA 5 DC ILIMIT 9 + + VFB - 2.45V + VIN OK 1.0V VREF PULSE WIDTH MODULATOR + PWM OUT 11 DC ILIMIT VCC UVLO REV. 1.0.2 3/7/2001 ML4800 PIN CONFIGURATION ML4800 16-Pin PDIP (P16) 16-Pin Narrow SOIC (S16N) IEAO 1 IAC 2 16 VEAO 15 VFB ISENSE 3 14 VREF VRMS 4 13 VCC SS 5 VDC 6 12 PFC OUT 11 PWM OUT RAMP 1 7 10 GND RAMP 2 8 9 DC ILIMIT TOP VIEW PIN DESCRIPTION PIN NAME FUNCTION PIN NAME FUNCTION 1 IEAO Slew rate enhanced PFC transconductance error amplifier output 9 DC ILIMIT PWM cycle-by-cycle current limit comparator input 2 IAC PFC AC line reference input to Gain Modulator 10 GND Ground 11 PWM OUT PWM driver output 3 ISENSE Current sense input to the PFC Gain Modulator 12 PFC OUT PFC driver output 4 VRMS PFC Gain Modulator RMS line voltage compensation input 13 VCC Positive supply 14 5 SS Connection point for the PWM soft start capacitor VREF Buffered output for the internal 7.5V reference 15 6 VDC PWM voltage feedback input VFB PFC transconductance voltage error amplifier input 7 RAMP 1 Oscillator timing node; timing set by RTCT 16 VEAO PFC transconductance voltage error amplifier output 8 RAMP 2 When in current mode, this pin functions as the current sense input; when in voltage mode, it is the PWM modulation ramp input. 2 REV. 1.0.2 3/7/2001 ML4800 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC .............................................................................................. 18V ISENSE Voltage ................................................. -5V to 0.7V Voltage on Any Other Pin ...... GND - 0.3V to VCCZ + 0.3V IREF ........................................................................................... 10mA IAC Input Current .................................................... 10mA Peak PFC OUT Current, Source or Sink ....................... 1A Peak PWM OUT Current, Source or Sink .................... 1A PFC OUT, PWM OUT Energy Per Cycle ................... 1.5µJ Junction Temperature .............................................. 150°C Storage Temperature Range ...................... -65°C to 150°C Lead Temperature (Soldering, 10 sec) ..................... 260°C Thermal Resistance (θJA) Plastic DIP .......................................................... 80°C/W Plastic SOIC ...................................................... 105°C/W OPERATING CONDITIONS Temperature Range ML4800CX .................................................... 0°C to 70°C ML4800IX .................................................. -40°C to 85°C ELECTRICAL CHARACTERISTICS Unless otherwise specified, VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 5 V VOLTAGE ERROR AMPLIFIER Transconductance 0 VNON INV = VINV, VEAO = 3.75V Feedback Reference Voltage Input Bias Current 30 65 90 µ 2.43 2.5 2.57 V -0.5 -1.0 µA Note 2 Output High Voltage Ω Input Voltage Range 6.0 Output Low Voltage 6.7 0.1 V 0.4 V Source Current VIN = ±0.5V, VOUT = 6V -40 -140 µA Sink Current VIN = ±0.5V, VOUT = 1.5V 40 140 µA 50 60 dB 50 60 dB Open Loop Gain Power Supply Rejection Ratio 11V < VCC < 16.5V CURRENT ERROR AMPLIFIER Transconductance -1.5 VNON INV = VINV, VEAO = 3.75V Input Offset Voltage V 50 100 150 µ 0 4 15 mV -0.5 -1.0 µA Input Bias Current Output High Voltage 2 Ω Input Voltage Range 6.0 Output Low Voltage 6.7 0.65 V 1.0 V Source Current VIN = ±0.5V, VOUT = 6V -40 -104 µA Sink Current VIN = ±0.5V, VOUT = 1.5V 40 160 µA 60 70 dB 60 75 dB Threshold Voltage 2.65 2.75 2.85 V Hysteresis 175 250 325 mV Open Loop Gain Power Supply Rejection Ratio 11V < VCC < 16.5V OVP COMPARATOR REV. 1.0.2 3/7/2001 3 ML4800 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 2.65 2.75 2.85 V 2 4 ms 0.4 0.5 0.6 V Threshold Voltage -0.9 -1.0 -1.1 V (PFC ILIMIT VTH - Gain Modulator Output) 120 220 TRI-FAULT DETECT Fault Detect HIGH Time to Fault Detect HIGH VFB = VFAULT DETECT LOW to VFB = OPEN. 470pF from VFB to GND Fault Detect LOW PFC ILIMIT COMPARATOR Delay to Output mV 150 300 ns 1.0 1.05 V Input Bias Current ±0.3 ±1 µA Delay to Output 150 300 ns DC ILIMIT COMPARATOR Threshold Voltage 0.95 VIN OK COMPARATOR Threshold Voltage 2.35 2.45 2.55 V Hysteresis 0.8 1.0 1.2 V IAC = 100µA, VRMS = VFB = 0V 0.60 0.80 1.05 IAC = 50µA, VRMS = 1.2V, VFB = 0V 1.8 2.0 2.40 IAC = 50µA, VRMS = 1.8V, VFB = 0V 0.85 1.0 1.25 IAC = 100µA, VRMS = 3.3V, VFB = 0V 0.20 0.30 0.40 GAIN MODULATOR Gain (Note 3) Bandwidth IAC = 100µA Output Voltage IAC = 350µA, VRMS = 1V, VFB = 0V 10 MHz 0.60 0.75 0.9 V 71 76 81 kHz OSCILLATOR Initial Accuracy TA = 25°C Voltage Stability 11V < VCC < 16.5V Temperature Stability Total Variation % 2 % 68 84 kHz Ramp Valley to Peak Voltage 2.5 PFC Dead Time 250 330 ns 5.5 7.5 mA CT Discharge Current 4 Line, Temp 1 VRAMP 2 = 0V, VRAMP 1 = 2.5V 3.5 V REV. 1.0.2 3/7/2001 ML4800 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 7.4 7.5 7.6 V REFERENCE Output Voltage TA = 25°C, I(VREF) = 1mA Line Regulation 11V <VCC <16.5V 10 25 mV Load Regulation 0mA <I(VREF) <10mA; TA = 0ºC to 70ºC 10 20 mV 0mA < I(VREF) < 5mA; TA = –40ºC to 85ºC 10 20 mV Temperature Stability 0.4 7.35 % Total Variation Line, Load, Temp Long Term Stability TJ = 125°C, 1000 Hours Minimum Duty Cycle VIEAO > 4.0V Maximum Duty Cycle VIEAO < 1.2V Output Low Voltage IOUT = -20mA 0.4 0.8 V IOUT = -100mA 0.7 2.0 V IOUT = 10mA, VCC = 9V 0.4 0.8 V 5 7.65 V 25 mV 0 % PFC Output High Voltage Rise/Fall Time 90 95 % IOUT = 20mA VCC – 0.8V V IOUT = 100mA VCC - 2V V CL = 1000pF 50 ns PWM Duty Cycle Range Output Low Voltage Output High Voltage 0-44 0-47 0-49 % IOUT = -20mA 0.4 0.8 V IOUT = -100mA 0.7 2.0 V IOUT = 10mA, VCC = 9V 0.4 0.8 V IOUT = 20mA VCC – 0.8V V IOUT = 100mA VCC - 2V V Rise/Fall Time CL = 1000pF 50 ns Start-up Current VCC = 12V, CL = 0 200 350 µA Operating Current 14V, CL = 0 5.5 7 mA SUPPLY Undervoltage Lockout Threshold 12.4 13 13.6 V Undervoltage Lockout Hysteresis 2.5 2.8 3.1 V Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: Includes all bias currents to other circuits connected to the VFB pin. Note 3: Gain = K x 5.3V; K = (IGAINMOD - IOFFSET) x [IAC (VEAO - 0.625)]-1; VEAOMAX=5V. REV. 1.0.2 3/7/2001 5 ML4800 TYPICAL PERFORMANCE CHARACTERISTICS 180 Ω TRANSCONDUCTANCE (µ ) 160 140 120 100 80 60 40 20 0 0 1 3 2 5 4 VFB (V) Voltage Error Amplifier (VEA) Transconductance (gm) 180 480 VARIABLE GAIN BLOCK CONSTANT (K) Ω TRANSCONDUCTANCE (µ ) 160 140 120 100 80 60 40 20 0 –500 0 500 420 360 300 240 180 120 60 0 0 1 Current Error Amplifier (IEA) Transconductance (gm) 4 5 VRMS(V) Gain Modulator Transfer Characteristic (K) K= 6 3 2 IEA INPUT VOLTAGE (mV) 2I 7 5 mV GAINMOD−84µA 0 –1 . IAC × 5− 0625 REV. 1.0.2 3/7/2001 ML4800 FUNCTIONAL DESCRIPTION The ML4800 consists of an average current controlled, continuous boost Power Factor Corrector (PFC) front end and a synchronized Pulse Width Modulator (PWM) back end. The PWM can be used in either current or voltage mode. In voltage mode, feedforward from the PFC output buss can be used to improve the PWM’s line regulation. In either mode, the PWM stage uses conventional trailingedge duty cycle modulation, while the PFC uses leadingedge modulation. This patented leading/trailing edge modulation technique results in a higher usable PFC error amplifier bandwidth, and can significantly reduce the size of the PFC DC buss capacitor. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the ML4800 runs at the same frequency as the PFC. In addition to power factor correction, a number of protection features have been built into the ML4800. These include soft-start, PFC overvoltage protection, peak current limiting, brownout protection, duty cycle limiting, and under-voltage lockout. must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VACrms. The other condition is that the current drawn from the line at any given instant must be proportional to the line voltage. Establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver satisfies the first of these requirements. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation causes the current error amplifier to command a power stage current that varies directly with the input voltage. In order to prevent ripple, which will necessarily appear at the output of the boost circuit (typically about 10VAC on a 385V DC level), from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC such to be proportional to 1/VIN2, which linearizes the transfer function of the system as the AC input voltage varies. Since the boost converter topology in the ML4800 PFC is of the current-averaging type, no slope compensation is required. POWER FACTOR CORRECTION PFC SECTION Power factor correction makes a nonlinear load look like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). A common class of nonlinear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peak-charging effect, which occurs on the input filter capacitor in these supplies, causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current inphase with the line voltage. Such supplies present a power factor to the line of less than one (i.e. they cause significant current harmonics of the power line frequency to appear at their input). If the input current drawn by such a supply (or any other nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved. Gain Modulator To hold the input current draw of a device drawing power from the AC line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. The PFC section of the ML4800 uses a boost-mode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage. No bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line frequency) from zero volts to the peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current drawn from the power line is proportional to the input line voltage. One of these conditions is that the output voltage of the boost converter REV. 1.0.2 3/7/2001 Figure 1 shows a block diagram of the PFC section of the ML4800. The gain modulator is the heart of the PFC, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and PFC output voltage. There are three inputs to the gain modulator. These are: 1) A current representing the instantaneous input voltage (amplitude and waveshape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current. 2) A voltage proportional to the long-term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The gain modulator’s output is inversely proportional to VRMS2 (except at unusually low values of VRMS where special gain contouring takes over, to limit power dissipation of the circuit components under heavy brownout conditions). The relationship between VRMS and gain is called K, and is illustrated in the Typical Performance Characteristics. 3) The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variations in this voltage. 7 ML4800 FUNCTIONAL DESCRIPTION (Continued) The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual-ground (negative) input of the current error amplifier. In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC from the power line. The general form for the output of the gain modulator is: IGAINMOD = IAC × VEAO × 1V VRMS 2 (1) More More exactly, exactly, the output current of the gain modulator is given given by: IGAINMOD = K × (VEAO − 0.625V ) × IAC the gain modulator will cause the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator’s output decreases, the output duty cycle will decrease, to achieve a less negative voltage on the ISENSE pin. Cycle-By-Cycle Current Limiter The ISENSE pin, as well as being a part of the current feedback loop, is a direct input to the cycle-by-cycle current limiter for the PFC section. Should the input voltage at this pin ever be more negative than -1V, the output of the PFC will be disabled until the protection flipflop is reset by the clock pulse at the start of the next PFC power cycle. where K is in units of V-1. TriFault DetectTM Note that the output current of the gain modulator is limited to 500µA. To improve power supply reliability, reduce system component count, and simplify compliance to UL 1950 safety standards, the ML4800 includes TriFault Detect. This feature monitors VFB (Pin 15) for certain PFC fault conditions. Current Error Amplifier The current error amplifier’s output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the ISENSE pin. The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. In higher power applications, two current transformers are sometimes used, one to monitor the ID of the boost MOSFET(s) and one to monitor the IF of the boost diode. As stated above, the inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from 16 15 2.5V VEA – 0.5V IEA 1.6kΩ + + – IAC 4 ISENSE Overvoltage Protection The OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. A resistor divider from the high voltage DC output of the PFC is fed to VFB. When the voltage on VFB exceeds 2.75V, the PFC output driver is 1 2 VRMS TriFault detect is an entirely internal circuit. It requires no external components to serve its protective function. IEAO VEAO VFB In the case of a feedback path failure, the output of the PFC could go out of safe operating limits. With such a failure, VFB will go outside of its normal operating area. Should VFB go too low, too high, or open, TriFault Detect senses the error and terminates the PFC output drive. + – OVP TRI-FAULT + 2.75V – + –1V GAIN MODULATOR Q + R Q S Q R Q – 1.6kΩ PFC ILIMIT 3 RAMP 1 7 S – PFC OUT 12 OSCILLATOR Figure 1. PFC Section Block Diagram 8 REV. 1.0.2 3/7/2001 ML4800 FUNCTIONAL DESCRIPTION (Continued) shut down. The PWM section will continue to operate. The OVP comparator has 250mV of hysteresis, and the PFC will not restart until the voltage at VFB drops below 2.50V. The VFB should be set at a level where the active and passive external power components and the ML4800 are within their safe operating voltages, but not so low as to interfere with the boost voltage regulation loop. Error Amplifier Compensation The PWM loading of the PFC can be modeled as a negative resistor; an increase in input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 2 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: as the reference voltage comes up from zero volts, it creates a differentiated voltage on IEAO which prevents the PFC from immediately demanding a full duty cycle on its boost converter. There are two major concerns when compensating the voltage loop error amplifier; stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier’s open-loop crossover frequency should be 1/2 that of the line frequency, or 23Hz for a 47Hz line (lowest anticipated international power frequency). The gain vs. input voltage of the ML4800’s voltage error amplifier has a specially shaped non-linearity such that under steady-state operating conditions the transconductance of the error amplifier is at a local minimum. Rapid perturbations in line or load conditions will cause the input to the voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier will increase significantly, as shown in the Typical Performance Characteristics. This raises the gainbandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristic. The current amplifier compensation is similar to that of the voltage error amplifier with the exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. It should also be limited to less than 1/6th that of the switching frequency, e.g. 16.7kHz for a 100kHz switching frequency. There is a modest degree of gain contouring applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current-loop perturbations. However, the boost inductor will usually be the dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than that of the voltage error amplifier. This is illustrated in the Typical Performance Characteristics. For more information on compensating the current and voltage control loops, see Application Notes 33 and 34. Application Note 16 also contains valuable information for the design of this class of PFC. VREF VBIAS RBIAS PFC OUTPUT 16 1 IEAO VEAO VFB 15 2.5V VCC VEA – IEA + + – IAC ML4800 + – 0.22µF CERAMIC 15V ZENER GND 2 VRMS 4 GAIN MODULATOR ISENSE 3 Figure 2. Compensation Network Connections for the Voltage and Current Error Amplifiers REV. 1.0.2 3/7/2001 Figure 3. External Component Connections to VCC 9 ML4800 FUNCTIONAL DESCRIPTION (Continued) Oscillator (RAMP 1) The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock: fOSC = 1 t RAMP + t DEADTIME (2) The dead time of the oscillator is derived from the following equation: t RAMP = C T × R T × In . VREF − 125 . VREF − 375 (3) at VREF = 7.5V: t RAMP = C T × R T × 0.51 The dead time of the oscillator may be determined using: t DEADTIME = 2.5V × C T = 450 × C T 55 . mA (4) The dead time is so small (tRAMP >> tDEADTIME) that the operating frequency can typically be approximated by: fOSC = 1 (5) t RAMP EXAMPLE: For the application circuit shown in the data sheet, with the oscillator running at: fOSC = 100kHz = 1 t RAMP Solving for RT x CT yields 1.96 x 10-4. Selecting standard components values, CT = 390pF, and RT = 51.1kΩ. The dead time of the oscillator adds to the Maximum PWM Duty Cycle (it is an input to the Duty Cycle Limiter). With zero oscillator dead time, the Maximum PWM Duty Cycle is typically 45%. In many applications, care should be taken that CT not be made so large as to extend the Maximum Duty Cycle beyond 50%. This can be accomplished by using a stable 390pF capacitor for CT. PWM SECTION Pulse Width Modulator The PWM section of the ML4800 is straightforward, but there are several points which should be noted. Foremost among these is its inherent synchronization to the PFC section of the device, from which it also derives its basic timing. The PWM is capable of current-mode or voltage mode operation. In current-mode applications, the PWM ramp (RAMP 2) is usually derived directly from a current 10 sensing resistor or current transformer in the primary of the output stage, and is thereby representative of the current flowing in the converter’s output stage. DC ILIMIT, which provides cycle-by-cycle current limiting, is typically connected to RAMP 2 in such applications. For voltage-mode operation or certain specialized applications, RAMP 2 can be connected to a separate RC timing network to generate a voltage ramp against which VDC will be compared. Under these conditions, the use of voltage feedforward from the PFC buss can assist in line regulation accuracy and response. As in current mode operation, the DC ILIMIT input would is used for output stage overcurrent protection. No voltage error amplifier is included in the PWM stage of the ML4800, as this function is generally performed on the output side of the PWM’s isolation boundary. To facilitate the design of optocoupler feedback circuitry, an offset has been built into the PWM’s RAMP 2 input which allows VDC to command a zero percent duty cycle for input voltages below 1.25V. PWM Current Limit The DC ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output of the PWM will be disabled until the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. VIN OK Comparator The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if this voltage on VFB is less than its nominal 2.45V. Once this voltage reaches 2.45V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start begins. PWM Control (RAMP 2) When the PWM section is used in current mode, RAMP 2 is generally used as the sampling point for a voltage representing the current in the primary of the PWM’s output transformer, derived either by a current sensing resistor or a current transformer. In voltage mode, it is the input for a ramp voltage generated by a second set of timing components (RRAMP2, CRAMP2), that will have a minimum value of zero volts and should have a peak value of approximately 5V. In voltage mode operation, feedforward from the PFC output buss is an excellent way to derive the timing ramp for the PWM stage. Soft Start Start-up of the PWM is controlled by the selection of the external capacitor at SS. A current source of 25µA supplies the charging current for the capacitor, and start-up of the PWM begins at 1.25V. Start-up delay can be programmed by the following equation: REV. 1.0.2 3/7/2001 ML4800 FUNCTIONAL DESCRIPTION (Continued) C SS = t DELAY × 25µA . V 125 while at the same time delivering 13V nominal gate drive at the PWM OUT and PFC OUT outputs. If using a Zener diode for this function, it is important to limit the current through the Zener to avoid overheating or destroying it. This can be easily done with a single resistor in series with the Vcc pin, returned to a bias supply of typically 18V to 20V. The resistor’s value must be chosen to meet the operating current requirement of the ML4800 itself (8.5mA, max.) plus the current required by the two gate driver outputs. (6) where CSS is the required soft start capacitance, and tDELAY is the desired start-up delay. It is important that the time constant of the PWM soft-start allow the PFC time to generate sufficient output power for the PWM section. The PWM start-up delay should be at least 5ms. EXAMPLE: With a VBIAS of 20V, a VCC of 15V and the ML4800 driving a total gate charge of 90nC at 100kHz (e.g., 1 IRF840 MOSFET and 2 IRF820 MOSFETs), the gate driver current required is: Solving for the minimum value of CSS: C SS = 5ms × 25µA = 100nF . V 125 (6a) Caution should be exercised when using this minimum soft start capacitance value because premature charging of the SS capacitor and activation of the PWM section can result if VFB is in the hysteresis band of the VIN OK comparator at start-up. The magnitude of VFB at start-up is related both to line voltage and nominal PFC output voltage. Typically, a 1.0µF soft start capacitor will allow time for VFB and PFC out to reach their nominal values prior to activation of the PWM section at line voltages between 90Vrms and 265Vrms. IGATEDRIVE = 100kHz × 90nC = 9mA RBIAS = RBIAS = I2 I1 + 20V −15V = 250Ω 6mA + 9mA + 5mA The ML4800 should be locally bypassed with a 1.0µF ceramic capacitor. In most applications, an electrolytic capacitor of between 47µF and 220µF is also required across the part, both for filtering and as part of the start-up bootstrap circuitry. The ML4800 is a voltage-fed part. It requires an external 15V, ±10% (or better) shunt voltage regulator, or some other VCC regulator, to regulate the voltage supplied to the part at 15V nominal. This allows low power dissipation SW2 (8) Choose RBIAS = 240Ω. Generating VCC L1 VBIAS − VCC ICC + IG + Iz (7) I3 I4 VIN RL SW1 DC C1 RAMP VEAO REF U3 + –EA TIME DFF RAMP OSC U4 CLK + – U1 R Q D U2 Q CLK VSW1 TIME Figure 4. Typical Trailing Edge Control Scheme REV. 1.0.2 3/7/2001 11 ML4800 LEADING/TRAILING MODULATION Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. The error amplifier output voltage is then compared with the modulating ramp. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned OFF. When the switch is ON, the inductor current will ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure 4 shows a typical trailing edge control scheme. One of the advantages of this control technique is that it requires only one system clock. Switch 1 (SW1) turns off and switch 2 (SW2) turns on at the same instant to minimize the momentary “no-load” period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC’s output ripple voltage can be reduced by as much as 30% using this method. In the case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during the OFF time of the switch. Figure 5 shows a leading edge control scheme. TYPICAL APPLICATIONS SW2 L1 I2 I1 + Figure 6 is the application circuit for a complete 100W power factor corrected power supply, designed using the methods and general topology detailed in Application Note 33. I3 I4 VIN RL SW1 DC C1 RAMP VEAO REF U3 + EA – RAMP OSC U4 CLK VEAO + – CMP U1 TIME DFF R Q D U2 Q CLK VSW1 TIME Figure 5. Typical Leading Edge Control Scheme 12 REV. 1.0.2 3/7/2001 REV. 1.0.2 3/7/2001 R6 1.2Ω NOTE: R5 1.2Ω ISENSE AC INPUT 85 TO 260V F1 3.15A D15 1N914 D13 1N914 D14 1N914 C19 1.0µF R4 13.2kΩ C3 R3 0.22µF 100kΩ C2 0.47µF R8 1.2Ω R2 357kΩ R1 357kΩ BR1 4A, 600V KBL06 R10 249kΩ C26 47µF R9 249kΩ R27 82kΩ C18 470pF R20 22Ω R38 42.2kΩ D2 15V 8 7 6 5 4 3 2 1 RAMP 2 RAMP1 VDC SS VRMS ISENSE IAC IEAO VFB PFC OUT VCC VREF DC ILMIT GND PWM OUT U1 C5 100µF 9 10 11 12 13 14 15 16 C28 220pF C12 10µF 35V C4 4.7nF VDC C6 1.5nF C7 150pF R28 240Ω Q1 ML4800 R12 68.1k R16 10kΩ C11 220pF Q1G D1 8A HFA08TB60 D8, D10; IN5818 D3, D5, D6, D12; BYV26C D11; MBR2545CT L1; PREMIER MAGNETICS TSD-1047 L2; PREMIER MAGNETICS VTP-05007 L3; PREMIER MAGNETICS TSD-904 T1; PREMIER MAGNETICS PMGD-03 T2; PREMIER MAGNETICS TSD-735 UNUSED DESIGNATORS; C14, C16, C17, C27, C29, C33, D3, D9, R42, R43, R36, R35 RT/CT R39 33Ω R7 1.2Ω C1 0.47µF L1 D8 R14 383kΩ R13 383kΩ T1A R15 4.99kΩ Q3 D5 600V R22 2.2Ω C8 150µF R11 412kΩ PWM ILIMIT Q2 C13 0.22µF REF D4 5.1V R37 1kΩ C15 1.0µF VCC R23 220Ω R21 2.2Ω Q3G D7 16V R24 10kΩ R19 33Ω D10 C20 0.47µF R18 33Ω R17 3Ω C31 330pF VFB T1B C25 0.1µF Q2G D12 J8 D11B D11A PRI GND C9 15nF R26 10kΩ R25 10kΩ Q4 D6 600V T2C L2 C10 10µF C21 1500µF U2 R30 1.5kΩ R29 1.2kΩ U3 TL431C VDC R40 470Ω C24 0.47µF VBUSS R32 8.66kΩ C30 1000µF R33 2.26kΩ C23 10nF R31 10kΩ R44 10kΩ C22 10µF C32 0.47µF L3 12V RETURN 12V RET R34 240Ω 12V, 100W 12V ML4800 Figure 6. 100W Power Factor Corrected Power Supply, Designed Using Micro Linear Application Note 33 13 ML4800 ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE ML4800CP ML4800CS 0°C to 70°C 0°C to 70°C 16-Pin PDIP (P16) 16-Pin Narrow SOIC (S16N) ML4800IP ML4800IS -40°C to 85°C -40°C to 85°C 16-Pin PDIP (P16) 16-Pin Narrow SOIC (S16N) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 14 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2000 Fairchild Semiconductor Corporation REV. 1.0.2 3/7/2001