www.fairchildsemi.com FAN4800 Low Start-Up Current PFC/PWM Controller Combos Features General Description • • • • • The FAN4800 is a controller for power factor corrected, switched mode power supplies. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with the IEC-1000-3-2 specifications. Intended as a Bi-CMOS version of the industry-standard ML4800, the FAN4800 includes circuits for the implementation of leading edge, average current, boost type power factor correction and a trailing edge, pulse width PWM (Pulse Width Modulator). A gate driver with 1A capabilities minimizes the need for external driver circuits. Low power requirements improve efficiency and reduce component costs. • • • • • • • • • • • Low start-up current(100µA typ.) Low operating current(2.5mA typ.) Low total harmonic distortion, high power factor Pin-compatible upgrade for the ML4800 Average current, continuous, or discontinuous boost leading edge PFC Slew rate enhanced transconductance error amplifier for ultra-fast PFC response Internally synchronized leading edge PFC and trailing edge PWM Reduction of ripple current in the storage capacitor between the PFC and PWM sections PWM configurable for current mode or voltage mode operation Additional folded-back current limit for PWM section 20V BiCMOS process VIN OK guaranteed turn on PWM at 2.25V Vcc OVP Comparator, Low Power Detect Comparator Current-Fed gain modulator for improved noise immunity Brown out control, over-voltage protection, UVLO, soft start, and Reference OK Available in a 16-DIP Package Applications • • • • • • • • Desktop PC Power Supply Internet Server Power Supply Un-interruptible Power Supply UPS Battery Charger DC Motor Power Supply Monitor Power Supply Telecom System Power Supply Distributed Power An over voltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brownout protection. The PWM section can be operated in current or voltage mode, at up to 250kHz, and includes an accurate 50% duty cycle limit to prevent transformer saturation. The FAN4800 includes a folded-back current limit for the PWM section to provide a short circuit protection function. 16-DIP Rev. 1.0.0 ©2005 Fairchild Semiconductor Corporation FAN4800 Internal Block Diagram VEAO 16 IEAO 1 VFB 15 0.3V 4 3 7 7.5V REFERENCE 2.78V S IAC GAIN MODULATOR 14 PFC OUT PFC CMP 3.5k Q R -1V VRMS VREF TRI-FAULT 0.5V 3.5k 2 Vcc PFC OVP Vcc OVP Vcc 17.9V Low Power Detector 2.5V 13 POWER FACTOR CORRECTOR PFC ILIMIT S Q 12 R ISENSE RAMP1 OSCILLATOR CLK 8 PFC OUT PWM DUTY DUTY CYCLE LIMIT 350 RAMP2 PWM OUT PWM CMP 0.95V 6 VDC Vcc PWM OUT SS CMP S 20uA 1.0V 5 350 SS Q VFB 2.25V VIN OK DC ILIMIT GND VREF 9 Q DC ILIMIT PULSE WIDTH MODULATOR 2 11 R S R Vcc UVLO 10 FAN4800 Pin Configuration 1616 - Pin PDIP 14 VREF 14 13 VCC 13 4 V REF Vcc V RMS 12 11 10 DC ILIMIT 9 9 GND 10 DC ILIMIT 8 GND 7 RAMP2 RAMP 2 PWM OUT 12 11 6 RAMP1 RAMP 1 PFCOUT PWMOUT 5 PFC OUT SS V DC V FB 15 3 FAN6800 ISENSE 15 V FB 16 16 2 IAC VEAO VEAO 1 IEAO Pin Descriptions Pin No. Symbol 1 IEAO 2 IAC 3 ISENSE 4 VRMS 5 SS 6 VDC 7 RAMP1 (RtCt) 8 Description PFC transconductance current error amplifier output PFC gain control reference input Current sense input to the PFC current limit comparator Input for PFC RMS line voltage compensation Connection point for the PWM soft start capacitor PWM voltage feedback input Oscillator timing node; timing set by RT, CT RAMP2 In current mode, this pin functions as the current sense input; in voltage mode, it is the (PWM RAMP) PWM input from the PFC output (feed forward ramp) 9 DC ILIMIT 10 GND PWM current limit comparator input Ground 11 PWM OUT PWM driver output 12 PFC OUT PFC driver output 13 VCC Positive supply 14 VREF Buffered output for the internal 7.5V reference 15 VFB PFC transconductance voltage error amplifier input 16 VEAO PFC transconductance voltage error amplifier output 3 FAN4800 Absolute Maximum Ratings Absolute maximum ratings are those values beyond which the device could be permanently damaged. Parameter Min. Max. Unit VCC - 20 V IEAO 0 5.5 V ISENSE Voltage -5 0.7 V GND-0.3 VCC+0.3 V IREF - 10 mA IAC Input Current - 1 mA Peak PFC OUT Current, Source or Sink - 1 A Peak PWM OUT Current, Source or Sink - 1 A PFC OUT, PWM OUT Energy per Cycle - 1.5 µJ Junction Temperature - 150 °C Storage Temperature Range -65 150 °C Operating Temperature Range Voltage on Any Other Pin -40 125 °C Lead Temperature (Soldering,10 sec.) - 260 °C Thermal Resistance(θJA) Plastic DIP - 80 °C/W Electrical Characteristics Unless otherwise stated, these specifications apply: VCC=15V, RT=52.3KΩ, CT=470pF, TA= -40°C to 125°C Parameter Symbol Test Conditions Min. Typ. Max. Unit VOLTAGE ERROR AMPLIFIER 4 Input Voltage Range Vfb Note3 0 - 6 V Transconductance gm1 - 50 70 90 µmho Feedback Reference Voltage Vref(PFC) 2.45 2.5 2.55 V TA =25°C Input Bias Current Ib(Veao) Note1 -1.0 -0.05 - µΑ Output High Voltage Veao(H) - 5.8 6.0 - V Output Low Voltage Veao(L) - - 0.1 0.4 V Sink Current Isink(V) TA =25°C, VFB = 3V VEAO = 6.0V - -35 -20 µA Source Current Isource(V) TA =25°C, VFB = 1.5V VEAO = 1.5V 30 40 - µA Open Loop Gain Gv Note2, Note3 50 60 - dB Power Supply Rejection Ratio PSRR1 11V < VCC < 16.5V(Note3) 50 60 - dB FAN4800 Electrical Characteristics (Continued) Unless otherwise stated, these specifications apply: VCC=+15V, RT=52.3KΩ, CT=470pF, TA= -40°C to 125°C. Parameter Symbol Test Conditions Min. Typ. Max. Unit Vieao Note3 -1.5 - 0.7 V gm2 - 50 85 100 µmho Voffset TA =25°C - - 25 mV Ibeao Note3 -1 - - µA Output High Voltage Ieao(H) - 4.0 4.25 - V Output Low Voltage Ieao(L) - - 1.0 1.2 V Sink Current Isink(I) - -65 -35 µA 35 75 - µA CURRENT ERROR AMPLIFIER Input Voltage Range Transconductance Input Offset Voltage Input Bias Current ISENSE = +0.5, IEAO = 4.0V ISENSE = -0.5, IEAO = 1.5V Source Current Isource(I) Open Loop Gain Gi Note3 60 70 - dB PSRR2 11V < VCC <16.5V(Note3) 60 75 - dB Vovp TA =25°C 2.70 2.78 2.9 V HY(ovp) TA =25°C 230 - 350 mV Vth(lp) TA =25°C 0.15 0.3 0.4 V Vcc_ovp TA =25°C 17.5 17.9 18.5 V HY(Vcc_ovp) TA =25°C 1.40 1.5 1.65 V - 2 4 ms Power Supply Rejection Ratio PFC OVP COMPARATOR Threshold Voltage Hysteresis LOW POWER DETECT COMPARATOR Threshold Voltage VCC OVP COMPARATOR Threshold Voltage Hysteresis TRI-FAULT DETECT Time to Fault Detect High Fault Detect Low Td(F) VFB=VFault Detect LOW to VFB=Open. 470pF from VFB to GND(Note3) F(L) - 0.4 0.5 0.6 V Vth(cs) - -1.10 -1.00 -0.90 V 5 100 - mV PFC ILIMIT COMPARATOR Threshold Voltage (PFC ILIMIT VTH - Gain Modulator Output) Delay to Output(Note 3) Vth(cs)-Vgm - Td(pfc_off) - - 250 - ns Vth(DC) - 0.95 1.0 1.05 V Td(pwm_off) - - 250 - ns Threshold Voltage Vth(OK) - 2.10 - 2.45 V Hysteresis HY(OK) - 0.8 1.0 1.2 V DC ILIMIT COMPARATOR Threshold Voltage Delay to Output(Note 3) VIN OK COMPARATOR 5 FAN4800 Electrical Characteristics (Continued) Unless otherwise stated, these specifications apply: VCC=15V, RT=52.3KΩ, CT=470pF, TA= -40°C to 125°C. Parameter Symbol Test Conditions Min. Typ. Max. Unit GAIN MODULATOR G1 IAC =100µA, VRMS =0, VFB=1V TA =25°C 0.70 0.84 0.95 G2 IAC =100µA, VRMS =1.1V, VFB=1V TA =25°C 1.80 2.00 2.20 G3 IAC =150µA, VRMS =1.8V, VFB=1V TA =25°C 0.90 1.00 1.10 G4 IAC =300µA, VRMS =3.3V, VFB=1V TA =25°C 0.25 0.32 0.40 - 10 - MHz 0.80 1.00 1.20 V Gain (Note 2) Band Width Output Voltage = 3.5kΩ * (ISENSE - IOFFSET) BW Vo(gm) IAC =100µA(Note3) IAC =250µA, VRMS =1.1V, VFB=2V TA =25°C OSCILLATOR Initial Accuracy Fosc1 TA =25°C 68 - 81 kHz Voltage Stability ∆Fosc1 11V < VCC < 16.5V - 1 - % Temperature Stability ∆Fosc2 - - 2 - % Total Variation Fosc2 84 kHz Ramp Valley to Peak Voltage Vramp Note3 - 2.75 - V PFC Dead Time Tdead - - 685 - ns VRAMP2 = 0V, VRAMP1 = 2.5V 6.5 - 15 mA TA =25°C, I(VREF) = 1mA CT Discharge Current Idis Line, Temp 66 REFERENCE Output Voltage Vref1 7.4 7.5 7.6 V Line Regulation ∆Vref1 11V < VCC < 16.5V - 10 25 mV Load Regulation ∆Vref2 0mA < I(VREF) < 7mA - 10 20 mV Temperature Stability ∆Vref4 - - 0.4 - % Total Variation Vref2 Line, Load, Temp(Note3) 7.35 - 7.65 V Long Term Stability ∆Vref5 TJ = 125°C, 1000hours(Note3) 5 - 25 mV PFC Minimum Duty Cycle Dmin VIEAO > 4.0V - - 0 % Maximum Duty Cycle Dmax VIEAO < 1.2V 92 95 - % Output Low Rdson Output Low Voltage Output High Rdson Rise/Fall Time 6 Ron(low)1 IOUT = -20mA at TA =25°C - - 15 Ω Ron(low)2 IOUT = -100mA at TA =25°C - - 15 Ω IOUT = -10mA, VCC = 9V at TA =25°C (Note3) - 0.4 0.8 V Ron(high)1 IOUT = 20mA at TA =25°C - 15 20 Ω Ron(high)2 IOUT = 100mA at TA =25°C - 15 20 Ω CL = 1000pF(Note3) - 50 - ns Vol1 Tr(pfc) FAN4800 Electrical Characteristics (Continued) Unless otherwise stated, these specifications apply: VCC=+15V, RT=52.3KΩ, CT=470pF, TA= -40°C to 125°C. Parameter Symbol Test Conditions Min. Typ. Max. Unit - PWM Duty Cycle Range Output Low Rdson Output Low Voltage Output High Rdson 0-42 0-47 0-49 % Ron(low)3 D IOUT = -20mA at TA =25°C - - 15 Ω Ron(low)4 IOUT = -100mA at TA =25°C - - 15 Ω IOUT = -10mA, VCC = 9V TA =25°C - 0.4 0.8 V Vol2 Ron(high)3 IOUT = 20mA at TA =25°C - 15 20 Ω Ron(high)4 IOUT = 100mA at TA =25°C - 15 20 Ω CL = 1000pF(Note3) - 50 - ns 0.8 0.95 1.2 V Rise/Fall Time Tr(pwm) PWM Comparator Level Shift PWM(ls) - SUPPLY Start-up Current Ist VCC = 12V, CL = 0pF - 100 200 µA Operating Current Iop 14V, CL = 0pF - 2.5 7.0 mA 12.74 13 13.26 V 2.80 3.0 3.20 V Under Voltage Lockout Threshold Vth(start) Under Voltage Lockout Hysteresis Vth(hys) - Note1: Includes all bias currents to other circuits connected to the VFB pin. Note2: Gain = K × 5.375V; K = (ISENSE-IOFFSET) × [ IAC × (VEAO-0.625) ] -1; VEAOMAX = 6V Note3: This parameter, although guaranteed by design, is not 100% production tested. 7 FAN4800 Typical Performance Characteristics Figure A Voltage Error Amplifier(gmv) Transconductance Figure B Current Error Amplifier(gmi) Transconductance Figure C Gain Modulator Transfer Characteristic (K) K= 8 I GAINMOD − I OFFSET mV −1 I AC × (6 − 0.625 ) Figure D GAIN Gain = I SENSE − I OFFSET I AC FAN4800 Functional Description input line voltage. The FAN4800 consists of an average current controlled, continuous boost Power Factor Correction (PFC) front end and a synchronized Pulse Width Modulator(PWM) back end. The PWM can be used in either current or voltage mode. In voltage mode, feed forward from the PFC output bus can be used to improve the PWM’s line regulation. In either mode, the PWM stage uses conventional trailing edge duty cycle modulation. This patented leading/trailing edge modulation technique results in a higher usable PFC error amplifier bandwidth, and can significantly reduce the size of the PFC DC bus capacitor. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VACrms. The second condition is that the current drawn from the line at any given instant must be proportional to the line voltage. Establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier, and switching output driver satisfies the first of these requirements. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation causes the current error amplifier to command a power stage current that varies directly with the input voltage. To prevent ripple, which will necessarily appear at the output of boost circuit (typically about 10VAC on a 385VDC level), from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC section to be proportional to 1/VIN2, which linearizes the transfer function of the system as the AC input voltage The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the FAN4800 runs at the same frequency as the PFC. In addition to power factor correction, a number of protection features are built into the FAN4800. These include soft-start, PFC over voltage protection, peak current limiting, brownout protection, duty cycle limiting, and under voltage lockout (UVLO). Power Factor Correction Power Factor Correction treats a nonlinear load like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). A common class of nonlinear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peak charging effect, which occurs on the input filter capacitor in these supplies, causes brief high amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. Such supplies present a power factor to the line of less than one(i.e. they cause significant current harmonics of the power line frequency to appear at their input). If the input current drawn by such a supply (or any other nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the To hold the input current draw of a device drawing power from the AC line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. The PFC section of the FAN4800 uses a boost mode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage. No bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line frequency) from zero volts to the peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current drawn from the power line is proportional to the Since the boost converter topology in the FAN4800 PFC is the current averaging type, no slope compensation is required. PFC Section Gain Modulator Figure 1 shows a block diagram of the PFC section of the FAN4800. The gain modulator is the heart of the PFC, as the circuit block controls the response of the current loop to line voltage waveform and frequency, RMS line voltage, and PFC output voltages. There are three inputs to the gain modulator. These are: 1. A current representing the instantaneous input voltage (amplitude and wave shape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current. 2. A voltage proportional to the long term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The output of the gain modulator is inversely proportional to VRMS2(except at unusually low values of VRMS where special gain contouring takes over, to limit power dissipation of the circuit components under heavy brownout conditions). The relationship between VRMS and gain is called K, and is illustrated in the Figure C of the Typical Performance Characteristics. 9 FAN4800 3. The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variations in this voltage. The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual ground (negative) input of the current error amplifier. In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC from the power line. The general form of the output of the gain modulator is: I AC × VEAO I GAINMOD = ---------------------------------- × 1V 2 V RMS More precisely, the output current of the gain modulator is given by: I GAINMOD = K × ( VEAO – 0.625 ) × I AC where K is in units of V-1 Note that the output current of the gain modulator is limited around 228.47µA and the maximum output voltage of the gain modulator is limited to 228.47µA* 3.5K = 0.8V. This 0.8V will also determine the maximum input power. However, IGAINMOD cannot be measured directly from ISENSE. ISENSE = IGAINMOD-IOFFSET and IOFFSET can only be measured when VEAO is less than 0.5V and IGAINMOD is 0A. Typical IOFFSET is around 60µA. Selecting RAC for IAC pin IAC pin is the input of the gain modulator. IAC is also a current mirror input and it requires current input. Selecting a proper resistor RAC, will provide a good sine wave current derived from the line voltage and also help program the maximum input power and minimum input line voltage. RAC=Vin peak * 7.9K. For example, if the minimum line voltage is 80VAC, the RAC=80*1.414*7.9K=894Kohm. Current Error Amplifier, IEAO The current error amplifier’s output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the ISENSE pin. The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. As stated above, the inverting input of the current error 10 amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC , an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator’s output decreases, the output duty cycle will decrease, to achieve a less negative voltage on the ISENSE pin. Cycle-By-Cycle Current Limiter and Selecting Rs As well as being a part of the current feedback loop, the ISENSE pin is a direct input to the cycle-by-cycle current limiter for the PFC section. If the input voltage at this pin is ever less than -1V, the output of the PFC will be disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle. Rs is the sensing resistor of the PFC boost converter. During the steady state, line input current*Rs equals IGAINMOD*3.5K. Since the maximum output voltage of the gain modulator is IGAINMOD max*3.5K=0.8V during the steady state, Rs*line input current will be limited to below 0.8V as well. Therefore, to choose Rs, we use the following equation: R S = 0.8V × ( V INPEAK ) ⁄ ( 2 × Line Input Power ) For example, if the minimum input voltage is 80VAC, and the maximum input RMS power is 200Watt, RS = (0.8V * 80V * 1.414)/(2*200)=0.226ohm. PFC OVP In the FAN4800, the PFC OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load changes suddenly. A resistor divider from the high voltage DC output of the PFC is fed to VFB. When the voltage on VFB exceeds 2.78V, the PFC output driver is shut down. The PWM section will continue to operate. The OVP comparator has 280mV of hysteresis, and the PFC will not restart until the voltage at VFB drops below 2.50V. Also, Vcc OVP can serve as a redundant PFC OVP protection. VCC OVP and threshold is 17.9V with 1.5V hysteresis. FAN4800 VE A O 16 IE A O V FB 15 0.3V Lo w Po w er D e tecto r 4 3 7 PF C O VP V cc O VP 2.78V 17.9V IA C S Q P FC O U T P FC C M P 3.5k 14 R -1V G A IN M O D U LAT O R V RE F 7.5V RE FEREN C E T R I-F AU LT 0.5V 3.5k V RM S 13 V cc P O W ER FAC T O R C O R R EC TO R V cc 2.5V 2 1 PFC I LIM IT S Q 12 R I SE NS E RAMP1 O SC ILLA TO R C LK Figure 1. PFC Section Block Diagram Error Amplifier Compensation The PWM loading of the PFC can be modeled as a negative resistor because an increase in the input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 2 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: As the reference voltage increases from zero volts, it creates a differentiated voltage on IEAO which prevents the PFC from immediately demanding a full duty cycle on its boost converter. PFC Voltage Loop There are two major concerns when compensating the voltage loop error amplifier, VEAO: Stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier’s open loop crossover frequency should be 1/ 2 that of the line frequency, or 23Hz for 47Hz line (lowest anticipated international power frequency). The gain vs. input voltage of the FAN4800’s voltage error amplifier, VEAO has a specially shaped non-linearity so that under steady state operating conditions the transconductance of the error amplifier is at a local minimum. Rapid perturbation in line or load conditions will cause the input to the voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier will increase significantly, as shown in the Figure A of the Typical Performance Characteristics. This raises the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with conventional linear gain characteristics. The Voltage Loop Gain(S) is given by: ∆V ∆V ∆V EAO FB OUT = --------------------- × --------------------- × --------------------∆V ∆V ∆V FB OUT EAO P IN × 2.5V ≈ ---------------------------------------------------------------------------------------- × GM × Z V C 2 V OUTDC × ∆V ×S×C EAO DC where Zc : Compensation network for the voltage loop GMv: Transconductance of VEAO PIN: Average PFC input power VZOUTDC: PFC boost output voltage; typical designed value is 380V. CDC: PFC boost output capacitor PFC Current Loop The compensation of the current amplifier, IEAO, is similar to that of the voltage error amplifier, VEAO, with the exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. It should also be limited to less than 1/6th of the switching frequency, e.g. 16.7kHz for a 100kHz switching frequency. The Current Loop Gain(S) is given by: ∆V ∆D ∆I ISENSE OFF EAO = -------------------------------- × --------------------- × -------------------------------∆D OFF ∆I EAO ∆V ISENSE V ×R OUTDC S ≈ ----------------------------------------- × GM × Z I CI S × L × 2.5V where ZCI: Compensation network for the current loop GMI: Transconductance of IEAO VOUTDC: PFC boost output voltage; typical designed value is 380V. The equation uses the worst condition to 11 FAN4800 calculate the ZCI Rs: Sensing resistor of the boost converter 2.5V: Amplitude of the PFC leading modulation ramp design the pole of ISENSE filter at Fpfc/6, one sixth of the PFC switching frequency. Therefore, the boost inductor can be reduced 6 times without disturbing the stability. Thus the capacitor of the ISENSE Filter, CFILTER, will be around 283nF. L: boost inductor A modest degree of gain contouring is applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current loop perturbations. However, the boost inductor will usually be the dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than that of the voltage error amplifier. This is illustrated in the Figure A of the Typical Performance Characteristics. VBIAS RBIAS Vcc 0.22uF Ceramic 15V Zener FAN4800 Vref GND Figure 3. External Component Connection to Vcc PFC Output VEAO 16 IEAO 1 Osillator(RAMP1) The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock: VFB 15 2.5V f 3.5k 2 4 3 1 = -------------------------------------------------------------t +t RAMP DEADTIME IAC VRMS Gain Modulator 3.5k PFC CMP The dead time of the oscillator is derived from the following equation: ISENSE Figure 2. Compensation Network Connection for the Voltage and Current Error Amplifiers ISENSE filter, the RC filter between Rs and IENSE: There are two reasons to add a filter at ISENSE pin: 1) Protection: During start up or in-rush current conditions, it will have a large voltage cross, Rs, which is the sensing resistor of the PFC boost converter. It requires the ISENSE filter to attenuate the energy. 2) To reduce L, the Boost Inductor: The ISENSE filter also can reduce the Boost Inductor value since the ISENSE filter behaves like an integrator before ISENSE pin which is the input of the current error amplifier, IEAO. The ISENSE filter is an RC filter. The resistor value of the ISENSE filter is between 100ohm and 50ohm because IOFFSET X Rs can generate an offset voltage of IEAO. Selecting an RFILTER which is equal to 50ohm, will keep the offset of the IEAO less than 5mV. Usually, we 12 OSC t V REF – 1.00 = C × R × In ---------------------------------- RAMP T T V REF – 3.75 at VREF =7.5V and tRAMP = CT * RT* 0.55 The dead time of the oscillator may be determined using: t DEADTIME 2.75V = ------------------------ × C = 227 × C T T 12.11mA The dead time is so small (tRAMP>>tDEAD TIME) that the operating frequency can typically be approximated by: f OSC 1 = -------------------t RAMP FAN4800 PWM Current Limit EXAMPLE: For the application circuit shown in the data sheet, with the oscillator running at: f OSC 1 = 100kHz = -------------------t RAMP solving for CT * RT yields 1.96 * 10-4. CT is 390pF, and RT is 51.1kohm, selecting standard components values. The DC ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. Besides, when the DC ILIMIT triggers the cycle-by-cycle current, it also softly discharges the voltage of soft-start capacitor. It will limit PWM duty cycle mode. Therefore, the power dissipation will be reduced during the dead short condition. VIN OK Comparator The dead time of the oscillator adds to the maximum PWM duty cycle (it is an input to the Duty Cycle Limiter). With zero oscillator dead time, the maximum PWM duty cycle is typically 47%. Take care not to make CT too large which could extend the maximum duty cycle beyond 50%. This can be accomplished by using a stable 390pF capacitor for CT. The VIN OK Comparator monitors the DC output of the PFC and inhibits the PWM if this voltage on VFB is less than its nominal 2.25V. Once this voltage reaches 2.25V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft start begins. PWM Section PWM Control (RAMP2) Pulse Width Modulator The operation of the PWM section of the FAN4800 is straightforward, but there are several points that should be noted. Foremost among these is the inherent synchronization of PWM with the PFC section of the device, from which it also derives its basic timing. The PWM is capable of current mode or voltage mode operation. In current mode applications, the PWM ramp (RAMP2) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage, and is thereby representative of the current flowing in the converter’s output stage. DC ILIMIT, which provides cycle-by-cycle current limiting, is typically connected to RAMP2 in such applications. For voltage mode operation, and certain specialized applications, RAMP2 can be connected to a separate RC timing network to generate a voltage ramp against which VDC will be compared. Under these conditions, the use of voltage feed-forward from the PFC buss can assist in line regulation accuracy and response. As in current mode operation, the DC ILIMIT input is used for output stage over current protection. When the PWM section is used in current mode, RAMP2 is generally used as the sampling point for a voltage representing the current in the primary of the PWM’s output transformer. The voltage is derived either from a current sensing resistor or a current transformer. In voltage mode, RAMP2 is the input for a ramp voltage generated by a second set of timing components (RRAMP2, CRAMP2), that will have a minimum value of zero volts and a peak value of approximately 5V. In voltage mode operation, feed-forward from the PFC output buss is an excellent way to derive the timing ramp for the PWM stage. No voltage error amplifier is included in the PWM stage of the FAN4800, as this function is generally performed on the output side of the PWM’s isolation boundary. To facilitate the design of opto-coupler feedback circuitry, an offset has been built into the PWM’s RAMP2 input that allows VDC to command a zero percent duty cycle for input voltages below typical 0.95V. 13 FAN4800 Soft Start PWM start-up is controlled by selection of the external capacitor at SS. A current source of 20mA supplies the charging current for the capacitor, and start-up of the PWM begins at 0.95V. Start-up delay can be programmed by the following equation: C SS =t 20µA × ---------------DELAY 0.95V EXAMPLE: To obtain a desired VBIAS voltage of 18V, a VCC of 15V, and the FAN4800 driving a total gate charge of 90nC at 100kHz (e.g. 1 IRF840 MOSFET and 2 IRF820 MOSFET), the gate driver current required is: I GATEDRIVE = 100kHz × 90nC = 9mA R where Css is the required soft start capacitance, and the tDELAY is the desired start-up delay. It is important that the time constant of the PWM soft start allows the PFC time to generate sufficient output power for the PWM section. The PWM start-up delay should be at least 5ms. Solving for the minimum value of Css: C SS 20µA = 5ms × ---------------- = 100nF 0.95V Use caution when using this minimum soft start capacitance value because it can cause premature charging of the SS capacitor and activation of the PWM section if VFB is in the hysteresis band of the VIN OK comparator at start-up. The magnitude of VFB at start-up is related both to line voltage and nominal PFC output voltage. Typically, a 1.0mF soft-start capacitor will allow time for VFB and PFCOUT to reach their nominal values prior to activation of the PWM section at line voltages between 90Vrms and 265Vrms. Generating Vcc After turning on the FAN4800 at 13V, the operating voltage can vary from 10V to 17.9V. The threshold voltage of the Vcc OVP comparator is 17.9V. and its hysteresis is 1.5V. When Vcc reaches 17.9V, PFC OUT will be low, and the PWM section will not be disturbed. There are two ways to generate Vcc. One way is to use auxiliary power supply around 15V, and the other way is to use bootstrap winding to self-bias the FAN4800 system. The bootstrap winding can be either taped from the PFC boost choke or from the transformer of the DC-to-DC stage. The ratio of the bootstrap’s winding transformer for the bootstrap should be set between 18V and 15V. A filter network is recommended between Vcc(pin 13)and bootstrap winding. The resistor of the filter can be set as following. R FILTER × I vcc ∼ 2V, I vcc × fsw =I op + ( Q PFCFET + Q PWMFET ) Iop = 2.5mA ( typ. ) If anything goes wrong, and Vcc goes beyond 17.9V, the PFC gate(pin 12) drive goes low and the PWM gate drive (pin 11) remains working. The resistor’s value must be chosen to meet the operating current requirement of the FAN4800 itself (5mA, max.) in addition to the current required by the two gate driver outputs. 14 BIAS R BIAS V –V BIAS CC = -------------------------------------I +I CC G 18V – 15V = -------------------------------5mA + 9mA ChooseR BIAS = 214Ω Bypass the FAN4800 locally with a 1.0 mF ceramic capacitor. In most applications, an electrolytic capacitor of between 47mF and 220mF is also required across the part , both for filtering and as a part of the start-up bootstrap circuitry. FAN4800 Leading/Trailing Modulation lation is determined during off-time of the switch. Figure 5 shows a leading edge control scheme. Conventional PWM techniques employ trailing edge modulation in which the switch turns on right after the trailing edge of the system clock. The error amplifier output is then compared with the modulating ramp up. The effective duty cycle of the trailing edge modulation is determined during the on-time of the switch. Figure 4 shows a typical trailing edge control scheme. One of the advantages of this control technique is that it requires only one system clock. Switch 1(SW 1) turns off and switch 2(SW2) turns on at the same instant to minimize the momentary no-load period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC’s output ripple voltage can be reduced by as much as 30% using the leading edge modulation method. In the case of leading edge modulation, the switch is turned off exactly at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch is turned on. The effective duty-cycle of the leading edge modu- L1 SW 2 I2 I3 R AM P I1 + I4 RL V IN C1 DC V E AO SW 1 REF U3 T IM E VE A O EA D FF CMP R RAMP OSC U1 Q U2 D C LK Q C LK U4 T IM E Figure 4. Typical Trailing Edge Control Scheme L1 SW 2 I2 I1 I3 RAM P I4 RL + VIN C1 DC VE AO SW 1 U3 TIM E VE A O EA D FF CMP RE F RA M P O SC U4 R U1 D Q U2 C LK Q C LK TIM E Figure 5. Typical Leading Edge Control Scheme 15 16 RAMP1 R5D 1.2 D13 1N5401 D12 1N5401 R31 100 R5C R5A R5B 1.2 1.2 1.2 ISENSE C1 0.68uF F1 3.15A R4 15.4K R3 110K C19 C18 1.0uF 470pF C2 0.47uF C3 0.1uF R2B 453K R2A 453K BR1 4A,600V KBL06 C26 100nF C11 10nF R1B 453K + C26 330uF R1A 453K R27 75K 8 7 6 5 4 3 2 1 D9 MBRS 140 Q1 IRF840A RAMP2 RAMP1 VDC SS VRMS ISENSE IAC IEAO DC ILIMIT GND PWM OUT PFC OUT Vcc VREF VFB VEAO 9 10 11 12 13 14 15 16 C6/1.5nF C7/NOT USED R28 240 C4 10nF D1 15L9R460P2 FAN4800 R12 71.5K R10 6.2K R6 41.2K R21 22 L1 D2/1N5406 + C17 220pF C12 + 10uF 35V C6 100uF VFB T1A R15 3 C20 1uF R14 33 D4 R9 1K C15 C16 C13 C14 10nF1uF 0.1uF1uF REF C8 68nF R11 845K C9 10nF R13 10K PRI GND C10 10uF R16 10K D11B MBR2545CT D11A MBR2545CT RAMP2/DCILIM Q4 MMBT3904 R20B 2.2 T2 T2C D6 RGF1J D5 RGF1J Q3 IRF820A MMBZ5245B Vcc R19 220 R20A 2.2 D7 MMBZ5245B R30 4.7K Q2 IRF820A C31 D8 1nF MBRS 140 R8 D10 2.37K MBRS 140 T1B C25 R7B 178K 0.1uF R7A Q2G R17 178K 33 D3 RGF1J VDC U3 TL431A C23 100nF R26 10K R25 2.26K + C22 4.7uF R24 1.2K C21 1800uF R23 1.5K + R22 8.66K 12V, 100W 12V 12V RET R18 220 12V RETUR L1; PREMIER MAGNETICS TSD-1047 L2; PREMIER MAGNETICS VTP-05007 T1; PREMIER MAGNETICS PMGO-03 T2; PREMIER MAGNETICS TSO-735 U2 MOC8112 C24 1uF L2 NOTE: VDC/+380V FAN4800 Application Circuit (Current Mode) R5 1.2 R6 1.2 D12 1N4148 D11 1N4148 R27 82k R10 249k C27 47uF R9 249k C11 220pF C15 C16 1.0uF 470pF C2 0.47uF R4 13.2K R3 100K R2 357K R1 357K BR1 4A,600V KBL06 C3 0.22uF D10 1N4148 R8 1.2 R36 33 R7 1.2 RT/CT C1 0.47uF F1 3.15A DC ILIMIT R35 61.9k RAMP2 GND PWM OUT PFC OUT Vcc VREF VFB VEAO FAN4800 9 10 11 12 13 14 15 16 C6 1.5nF C7 150pF R16 10K R12 68.1K RAMP1 VDC SS VRMS ISENSE IAC IEAO C17 470pF 8 7 6 5 4 3 2 1 C4 4.7nF D1 8A FES16JT R28 D2 240 15V 1N4744 Q1 IRF840A R38 42.2K R20 22 L1 C18 220pF C12 10uF 35V C5 100uF D8 R14 383K C25 0.1uF R13 383K Q2 IRF820A R17 3 D9 C19 330pF VFB C14 1.0uF Q4 2N3904 C9 15nF C13 C8 0.22uF 150pF R11 412K REF R22 2.2 T2 T2C D6 600V D5 600V Q3 IRF820A 1N4733A Vcc D4 5.1V R37 1K R21 2.2 R23 220 C20 0.47uF R18 33 D7 16V R24 10K R19 33 T1A R15 4.99K T1B Q2G D3 J8 C10 10uF R26 10K PRI GND R25 10K D13B D13A C24 0.47uF L2 VBUSS R30 1.5K VDC U3 TL431A R39 470 C23 10nF R31 10K R40 10K R29 1.2K C21 1500uF L3 R33 2.26K C22 10uF C26 0.47uF R32 8.66K 12V RET 12V RETURN R34 240 C28 1000uF 12V 100W 12V D7, D8, D9; 1N9668 D3, D5, D6; UF4005 D13; MBR2545CT L1; PREMIER MAGNETICS TSD-1047 L2; PREMIER MAGNETICS VTP-05007 L3; PREMIER MAGNETICS TSD-904 T1; PREMIER MAGNETICS PMGO-03 T2; PREMIER MAGNETICS TSO-735 U2 MOC8112 NOTE: FAN4800 Application Circuit (Voltage Mode) 17 FAN4800 Mechanical Dimensions Package 16-DIP #9 7.62 0.300 2.54 0.100 3.25 ±0.20 0.128 ±0.008 5.08 MAX 0.200 +0.10 0~15° 18 0.25 –0.05 +0.004 0.010 –0.002 0.38 0.014 MIN 3.30 ±0.30 0.130 ±0.012 1.50 ±0.10 0.059 ±0.004 #8 0.46 ±0.10 0.018 ±0.004 #16 19.80 MAX 0.780 #1 19.40 ±0.20 0.764 ±0.008 ( 0.81 ) 0.032 6.40 ±0.20 0.252 ±0.008 FAN4800 Ordering Information Product Number Package Operating Temperature FAN4800IN 16-Pin PDIP -40°C ~ +125°C DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 10/10/05 0.0m 001 Stock#DSxxxxxxxx 2005 Fairchild Semiconductor Corporation