FSAL200 Wide Bandwidth Quad 2:1 Analog Multiplexer / Demultiplexer Switch Features Description ■ Typical 6Ω switch connection between two ports ■ Minimal propagation delay through the switch ■ Low ICC ■ Zero bounce in flow-through mode ■ Control inputs compatible with TTL level ■ Rail-to-rail signal handling ■ Low insertion loss ■ Route communications signals include: • • • • • • • 10/100 Ethernet 100VG-AnyLAN ATM25 SONET OCI 51.8 Mbps USB1.1 T1/E1 Token Ring 4/16 Mbps The Fairchild Switch FSAL200 is a rail-to-rail quad 2:1 high-speed CMOS TTL-compatible analog multiplexer/ demultiplexer switch. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. When OE is LOW, the select pin connects the A Port to the selected B Port output. When OE is HIGH, the switch is OPEN and a high-impedance state exists between the two ports. Ordering Information Part Number Package Number Pb-Free Package FSAL200QSC MQA16 Yes 16-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide FSAL200MTC MTC16 Yes 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Packing Method This device is also available in tape and reel. To order, append X to the part number. © 2002 - 2006 Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.0 www.fairchildsemi.com FSAL200 Wide Bandwidth Quad 2:1 Analog Multiplexer / Demultiplexer Switch June 2006 Analog Symbol Connection Diagram Truth Table S OE Function X HIGH Disconnect LOW LOW A=B1 HIGH LOW A=B2 Pin Descriptions Pin Name Function OE Switch Enable S Select Input A, B1, B2 Data Port © 2002 - 2006 Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.0 www.fairchildsemi.com 2 Absolute Maximum Ratings The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines the conditions for actual device operation. Symbol VCC VS Parameter Min. Max. Unit Supply Voltage -0.5 7.0 V DC Switch Voltage(1) -0.5 0.5 V -0.5 7.0 V -50 mA (1) VIN DC Input Voltage IIK DC Input Diode Current @ (IIK) VIN < 0V IOUT ICC/IGND DC Output Current 120 mA DC VCC or Ground Current ±100 mA +150 °C 0.5 W -40 85 °C Min. Max. Unit 3.0 5.5 V TSTG Storage Temperature Range -65 PD Power Dissipation @ ±85°C TA Ambient Temperature with Power Applied Recommended Operating Conditions(2) Symbol Parameter VCC Supply Voltage Operating VIN Control Input Voltage 0 VCC V VIN Switch Input Voltage 0 VCC V Output Voltage 0 VCC V -40 +85 °C Control Input Vcc = 2.3V - 3.6V 0 10 ns/V Control Input Vcc = 4.5V - 5.5V 0 5 ns/V 350 °C/W VOUT TA Operating Temperature Input RIse and Fall Time tr, tf OJA Thermal Resistance 1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. 2. Control input must be held HIGH or LOW; it must not float. © 2002 - 2006 Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.0 www.fairchildsemi.com 3 DC Electrical Characteristics VCC Symbol Parameter VIH HIGH-Level Input Voltage VIL LOW-Level Input Voltage IOZ RON IIN ICC OFF State Leakage Current (3) Switch On Resistance Conditions 0 £ VIN £5.5V Rflat Min. 4.5 - 5.5 2.0 Typ. Max. Units V 3.0 - 3.6 2.0 4.5 - 5.5 -0.5 0.8 3.0 - 3.6 -0.5 0.8 0 - 5.5 V 100 nA Ω ION = 10 - 30 mA 4.5 - 5.5 6 12 3.0 - 3.6 15 22 VIN = VCC or GND 5.5 ±1 VIN = VCC or GND 3.6 ±1 Quiescent Supply Current VIN = VCC or GND 5.5 1 mA All Channels ON or OFF IOUT = 0 VCC V 0.4 2 Ω 1 3 Control Input Leakage Current On Resistance Match Between Channels IO (V) ION = 10 - 30 mA Analog Signal Range ΔRON TA =-40°C to+85°C (3,4) Output Current On Resistance Flatness(3,5) VCC 0 IA= -30 mA, VBn = 3.15 4.5 - 5.5 IA = -10 mA, VBn 2.1 3.0 - 3.6 Bn, Bn, S = 0V to 5V 4.5 - 5.5 100 3.0 - 3.6 80 mA mA A, B1, B2 = 0V to 5V 4.5 - 5.5 3 A, B1, B2 = 0V to 5V 3.0 - 3.6 7 Ω 3. Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two (A or B Ports). 4. ΔRON = RON maximum - RON minimum measured at identical VCC, temperature, and voltage levels. 5. Flatness is defined as the difference between the maximum and minimum value of On Resistance over the specified range of conditions. © 2002 - 2006 Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.0 www.fairchildsemi.com 4 AC Electrical Characteristics Symbol tON tOFF OIRR TA = -40°C to +85°C (V) Min. Typ. Max. Units Turn-On Time VBn = 3V 4.5 - 5.5 10 20 ns Figure 1 S to Output VBn = 1.5V 3.0 - 3.6 28 40 ns Figure 2 Turn-Off Time VBn = 3V 4.5 - 5.5 5 10 ns Figure 1 ns Figure 2 pC Figure 3 Parameter S to Output Q VCC Conditions VBn = 1.5V Charge Injection (6) (7) Off Isolation 20 Figure 3.0 - 3.6 4 CL = 0.1 nF, VGEN = 0V 5.0 7 RGEN = 0Ω 3.3 3 RL = 100Ω 4.5 - 5.5 -55 dB Figure 4 3.0 - 3.6 -75 dB Figure 4 4.5 - 5.5 -70 dB Figure 5 3.0 - 3.6 -75 dB Figure 5 f = 30 MHz RL = 50Ω f = 1 MHz Xtalk RL = 100Ω Crosstalk f = 30 MHz RL = 50Ω f = 1 MHz BW -3dB Bandwidth RL = 100Ω 4.5 - 5.5 137 MHz Figure 8 RL = 50Ω 3.0 - 3.6 110 MHz Figure 8 D ΔRON/RL Distortion(6) RL = 100Ω 4.5 - 5.5 2 % 3.0 - 3.6 3 Conditions Typ. 6. Guaranteed by design. 7. Off Isolation = 20 log10 [VA / VBn]. Capacitance(8) Symbol Parameter Max. Units. Figure CIN Control Pin Input Capacitance VCC = 0V 2.3 pF CIO-B B Port Off Capacitance VCC = 5.0V and 3.0V 8 pF Figure 6 A Port Off Capacitance VCC = 5.0V and 3.0V 13 pF Figure 7 Channel On Capacitance VCC = 5.0V and 3.0V 15 pF Figure 7 CON 8. TA = +25°C, f = 1 MHz. Capacitance is characterized, but not tested in production. © 2006 Fairchild Semiconductor Corporation Device Number Rev. 1.7.0 www.fairchildsemi.com 5 AC Loading and Waveforms Figure 1. AC Waveforms Figure 2. ton, toff Loading © 2002 - 2006 Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.0 www.fairchildsemi.com 6 Figure 3. Charge Injection Test Figure 4. Off Isolation Figure 7. Channel On Capacitance Figure 5. Crosstalk Figure 8. Bandwidth Figure 6. Channel Off Capacitance © 2006 Fairchild Semiconductor Corporation Device Number Rev. 1.7.0 www.fairchildsemi.com 7 Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 9. 16-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0/0150” Wide, Package Number MQA16 © 2002 - 2006 Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.0 www.fairchildsemi.com 8 Physical Dimensions (Continued) Dimensions are in inches (millimeters) unless otherwise noted. Figure 10. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide, Package Number MTC16 © 2006 Fairchild Semiconductor Corporation Device Number Rev. 1.7.0 www.fairchildsemi.com 9 © 2002 - 2006 Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.0 www.fairchildsemi.com 10