FSA3157B - Fairchild Semiconductor

FSA3157B
Low-Voltage SPDT Analog Switch or 2:1
Multiplexer / De-multiplexer Bus Switch
Features
Description
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The FSA3157B is a high-performance, Single-Pole /
Double-Throw (SPDT) analog switch or 2:1 multiplexer /
de-multiplexer bus switch.
Useful in Both Analog and Digital Applications
Ultra-Small, MicroPak™ Leadless Package
Low On Resistance: <10 Ω Typical at 3.3 V VCC
Broad VCC Operating Range: 1.65 V to 5.5 V
Rail-to-Rail Signal Handling
Power-Down, High-Impedance Control Input
Over-Voltage Tolerance of Control Input to 7.0 V
Break-Before-Make Enable Circuitry
The device is fabricated with advanced sub-micron
CMOS technology to achieve high-speed enable and
disable times and low on resistance. The break-beforemake select circuitry prevents disruption of signals on
the B Port due to both switches temporarily being
enabled during select pin switching. The device is
specified to operate over the 1.65 to 5.5 V VCC operating
range. The control input tolerates voltages up to 5.5 V,
independent of the VCC operating range.
250 MHz, 3 dB Bandwidth
Ordering Information
Part Number
Operating
Temperature
Range
Top
Mark
FSA3157BL6X
-40 to +85°C
7G
6-Lead, MicroPak™ 1.0 mm Wide Package
5000 Units on
Tape and Reel
FSA3157BFHX
-40 to +85°C
7G
6-Lead, MicroPak2™, 1x1 mm Body, .35 mm Pitch
5000 Units on
Tape and Reel
© 2007 Fairchild Semiconductor Corporation
FSA3157B • Rev. 1.0.5
Package
Packing
Method
www.fairchildsemi.com
FSA3157B — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-Multiplexer Bus Switch
December 2013
Figure 1. Logic Symbol
Figure 2. Analog Symbol
Pin Configuration
Figure 3. Pad Assignments
Function Table
Input (S)
Function
Logic Level LOW
B0 Connected to A
Logic Level HIGH
B1 Connected to A
Pin Descriptions
Pin#
Name
Description
1
B1
Data Ports
2
GND
Ground
3
B0
Data Ports
4
A
Data Ports
5
VCC
Power Supply
6
S
Control Input
© 2007 Fairchild Semiconductor Corporation
FSA3157B • Rev. 1.0.5
FSA3157B — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-Multiplexer Bus Switch
Analog Symbols
www.fairchildsemi.com
2
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the
recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to
stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress
ratings only.
Symbol
VCC
Parameter
Supply Voltage
(1)
Min.
Max.
Unit
-0.5
7.0
V
V
VS
DC Switch Voltage
-0.5
VCC+0.5
VIN
DC Input Voltage
(1)
-0.5
7.0
IIK
DC Input Diode Current at VIN < 0 V
-50
IOUT
ICC/IGND
TSTG
V
mA
DC Output Current
128
mA
DC VCC or Ground Current
±100
mA
+150
°C
TJ
Junction Temperature Under Bias
+150
°C
TL
Junction Lead Temperature (Soldering, 10 seconds)
+260
°C
PD
Power Dissipation at +85°C
180
mW
5
kV
ESD
Storage Temperature Range
Electrostatic Discharge Capability
-65
Human Body Model,
JESD22-A114
Note:
1. Input and output negative voltage ratings may be exceeded if input and output diode current ratings are observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding
them or designing to Absolute Maximum Ratings.
Symbol
VCC
Parameter
Supply Voltage Operating
(2)
VIN
Control Input Voltage
VIN
Switch Input Voltage
VOUT
TA
tr , tf
(2)
Output Voltage
(2)
Operating Temperature
Input Rise and Fall Time
Max.
Unit
1.65
5.50
V
0
VCC
V
0
VCC
v
0
VCC
V
°C
-40
+85
Control Input VCC=2.3 V–3.6 V
0
10
Control Input VCC=4.5 V–5.5 V
0
5
Note:
2. Control input must be held HIGH or LOW; it must not float.
© 2007 Fairchild Semiconductor Corporation
FSA3157B • Rev. 1.0.5
Min.
ns/V
FSA3157B — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-Multiplexer Bus Switch
Absolute Maximum Ratings
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3
Symbol
Parameter
Conditions
VCC (V)
TA=+25°C
Min.
Typ.
TA=-40 to +85°C
Max.
Min.
Max.
Units
High Level Input
Voltage
1.65 to 1.95
0.75 VCC
0.75 VCC
2.30 to 5.50
0.7 VCC
0.7 VCC
VIL
Low Level Input
Voltage
1.65 to 1.95
0.25 VCC
0.25 VCC
2.30 to 5.50
0.3 VCC
0.3 VCC
IIN
Input Leakage
Current
0 ≤ VIN ≤ 5.5 V
0 to 5.50
±0.05
±0.1
±1
µA
Off State Leakage
Current
0 ≤ A, B ≤ VCC
1.65 to 5.50
±0.05
±0.10
±1.00
µA
VIH
IOFF
V
VIN=0 V, IO=30 mA
3.0
7.0
7.0
5.0
12.0
12.0
VIN=4.5 V, IO=–30 mA
7.0
15.0
15.0
VIN=0 V, IO=24 mA
4.0
9.0
9.0
10.0
20.0
20.0
5.0
12.0
12.0
13.0
30.0
30.0
6.5
20.0
20.0
17.0
50.0
50.0
1
10
µA
VCC
V
VIN=2.4 V, IO=–30 mA
RON
Switch On
Resistance(3)
VIN=3 V, IO=–24 mA
VIN=0 V, IO=8 mA
VIN=2.3 V,IO=–8 mA
VIN=0 V, IO=4 mA
VIN=1.65 V, IO=–4 mA
ICC
RRANGE
∆RON
RFLAT
4.50
3.00
2.30
1.65
Quiescent Supply
VIN=VCC or
Current: All
GND IOUT=0
Channels On or Off
5.50
Analog Signal
Range
VCC
On Resistance
Over Signal
Range(3,7)
On Resistance
Match Between
Channels(3,4)
On Resistance
Flatness(3,4,6)
V
0
VCC
0
IA=–30 mA,
0 ≤ VBn ≤ VCC
4.50
25
IA=–24 mA,
0 ≤ VBn ≤ VCC
3.00
50
IA=–8 mA,
0 ≤ VBn ≤ VCC
2.30
100
IA=–4 mA,
0 ≤ VBn ≤ VCC
1.65
300
Ω
IA=–30 mA, VBn=3.15
4.50
IA=–24 mA, VBn= 2.1
3.00
0.20
IA=–8 mA, VBn=1.6
2.30
0.50
IA=–4 mA, VBn=1.15
1.65
0.50
IA=–30 mA,
0 ≤ VBn ≤ VCC
5.00
6
3.00
12
2.50
28
1.80
125
IA=–24 mA,
0 ≤ VBn ≤ VCC
IA=–8 mA,
0 ≤ VBn ≤ VCC
IA=–4 mA,
0 ≤ VBn ≤ VCC
Ω
0.15
Ω
Ω
FSA3157B — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-Multiplexer Bus Switch
Electrical Characteristics
Notes:
3. Measured by the voltage drop between the A and B pins at the indicated current through the switch.
On resistance is determined by the lower of the voltages on the two (A or B Ports).
4. Parameter is characterized, but not tested in production.
5. ∆RON = RON maximum – RON minimum measured at identical VCC, temperature, and voltage levels.
6. Flatness is defined as the difference between the maximum and minimum value of on resistance over the
specified range of conditions.
7. Guaranteed by design.
© 2007 Fairchild Semiconductor Corporation
FSA3157B • Rev. 1.0.5
www.fairchildsemi.com
4
Symbol
tPLH, tPLH
Parameter
Conditions
Propagation Delay
Bus-to-Bus(8)
VIN=OPEN
TA=+25°C
VCC (V)
Min.
Typ.
tPLZ, tPHZ
tBBM
Q
Output Enable Time
Turn-On Time (A to
Bn)
Output Disable Time
Turn-Off Time
(A Port to B Port)
VIN=2x VCC for
tPZL VIN=0 V
for tPZH
VIN=2x VCC for
tPLZ VIN=0 V
for tPHZ1
Break-Before-Make
Time(9)
Charge Injection(9)
Min.
Max.
1.65 to 1.95
3.5
3.5
2.30 to 2.70
1.2
1.2
3.00 to 3.60
0.8
0.8
4.05 to 5.50
tPZL, tPZH
TA=-40 to +85°C
Max.
0.3
0.3
1.65 to 1.95
7.0
23.0
24.0
2.30 to 2.70
3.5
13.0
14.0
3.00 to 3.60
2.5
6.9
7.6
4.50 to 5.50
1.7
5.2
5.7
1.65 to 1.95
3.0
12.5
13.0
2.30 to 2.70
2.0
7.0
7.5
3.00 to 3.60
1.5
5.0
5.3
4.50 to 5.50
0.8
3.5
1.65 to 1.95
0.5
0.5
2.30 to 2.70
0.5
0.5
3.00 to 3.60
0.5
0.5
4.50 to 5.50
0.5
0.5
CL=0.1 nF,
VGEN=0 V
5.00
7
RGEN=0 Ω
3.30
3
Units
Figure
ns
Figure 10
Figure 11
ns
Figure 10
Figure 11
ns
Figure 10
Figure 11
ns
Figure 12
pC
Figure 13
3.8
OIRR
Off Isolation(10)
RL=50 Ω,
f=10 MHz
1.65 to 5.50
-57
dB
Figure 14
Xtalk
Crosstalk
RL=50 Ω,
f=10 MHz
1.65 to 5.50
-54
dB
Figure 15
BW
-3 dB Bandwidth
RL=50 Ω
1.65 to 5.50
250
MHz
Figure 18
THD
Total Harmonic
Distortion(9)
RL=600 Ω,
0.5 VPP,
f=600 Hz to
20 KHz
5.00
.011
%
Notes:
8. This parameter is guaranteed by design, but not tested. The bus switch contributes no propagation delay other
than the RC delay of the on resistance of the switch and the 50pF load capacitance when driven by an ideal
voltage source (zero output impedance).
9. Guaranteed by design.
10. Off Isolation = 20 log10 [VA / VBn].
Capacitance
TA = +25°C, f=1MHz. Capacitance is characterized, but not tested in production.
Symbol
CIN
CIO-B
CIOA-ON
Parameter
Conditions
Typical
Unit
Figure
Control Pin Input Capacitance
VCC=0 V
2.3
pF
B Port Off Capacitance
VCC=5.0 V
6.5
pF
Figure 16
A Port Capacitance, Switch Enabled
VCC=5.0 V
18.5
pF
Figure 17
© 2007 Fairchild Semiconductor Corporation
FSA3157B • Rev. 1.0.5
FSA3157B — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-Multiplexer Bus Switch
AC Electrical Characteristics
www.fairchildsemi.com
5
Figure 4. Off Isolation, VCC-1.65 V
Figure 5. Off Isolation, VCC-5.5 V
Figure 6. Crosstalk, VCC=1.65 V
Figure 7. Crosstalk, VCC=5.5 V
Figure 8. Bandwidth, VCC=1.65 V
Figure 9. Bandwidth, VCC=5.5 V
© 2007 Fairchild Semiconductor Corporation
FSA3157B • Rev. 1.0.5
FSA3157B — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-Multiplexer Bus Switch
Typical Performance Characteristics
www.fairchildsemi.com
6
Figure 10. AC Test Circuit
Figure 11. AC Waveforms
FSA3157B — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-Multiplexer Bus Switch
AC Loading and Waveforms
Figure 12. Break-Before-Make Interval Timing
© 2007 Fairchild Semiconductor Corporation
FSA3157B • Rev. 1.0.5
www.fairchildsemi.com
7
Figure 13. Charge Injection Test
Figure 14. Off Isolation
Figure 15. Crosstalk
Figure 16. Channel Off Capacitance
Figure 17. Channel On Capacitance
FSA3157B — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-Multiplexer Bus Switch
AC Loading and Waveforms (Continued)
Figure 18. Bandwidth
© 2007 Fairchild Semiconductor Corporation
FSA3157B • Rev. 1.0.5
www.fairchildsemi.com
8
2X
0.05 C
1.45
B
2X
(1)
0.05 C
(0.254)
(0.49)
5X
1.00
(0.75)
(0.52)
1X
A
TOP VIEW
PIN 1 IDENTIFIER
5
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
0.25
0.15 6X
1.0
DETAIL A
0.10
0.05
0.45
0.35
0.10
0.00 6X
C B A
C
0.40
0.30
0.35 5X
0.25
0.40 5X
0.30
0.5
(0.05)
6X
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
(0.13)
4X
BOTTOM VIEW
Notes:
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 19.
6-Lead, MicroPak™ 1.0 mm Wide Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
FSA3157B — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-Multiplexer Bus Switch
Physical Dimensions
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.
Package Designator
L6X
© 2007 Fairchild Semiconductor Corporation
FSA3157B • Rev. 1.0.5
Tape Section
Cavity Number
Cavity Status
Cover Type Status
Leader (Start End)
125 (Typical)
Empty
Sealed
Carrier
5000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
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9
0.89
0.35
0.05 C
1.00
2X
B
A
5X 0.40
PIN 1
MIN 250uM
0.66
1.00
1X 0.45
6X 0.19
0.05 C
TOP VIEW
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
2X
0.90
0.05 C
0.35
0.55MAX
C
5X 0.52
SIDE VIEW
0.73
(0.08) 4X
1
DETAIL A
2
1X 0.57
0.09
0.19 6X
3
0.20 6X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
(0.05) 6X
5X 0.35
0.25
6
5
4
0.60
0.35
(0.08)
4X
0.10
.05 C
C B A
0.40
0.30
BOTTOM VIEW
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
DESIGN.
E. DRAWING FILENAME AND REVISION: MGF06AREV3
Figure 20.
0.075X45°
CHAMFER
DETAIL A
PIN 1 LEAD SCALE: 2X
6-Lead, MicroPak2™, 1x1 mm Body, .35 mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
FSA3157B — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-Multiplexer Bus Switch
Physical Dimensions
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.
Package Designator
FHX
© 2007 Fairchild Semiconductor Corporation
FSA3157B • Rev. 1.0.5
Tape Section
Cavity Number
Cavity Status
Cover Type Status
Leader (Start End)
125 (Typical)
Empty
Sealed
Carrier
5000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
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10
FSA3157B — Low-Voltage SPDT Analog Switch or 2:1 Multiplexer / De-Multiplexer Bus Switch
11
www.fairchildsemi.com
© 2007 Fairchild Semiconductor Corporation
FSA3157B • Rev. 1.0.5