FUJITSU MB40C328PFV

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-28216-2E
ASSP For Video Applications
CMOS
8-bit 100 MSPS A/D Converter
MB40C328
■ DESCRIPTION
MB40C328 is a high-speed A/D converter using a fast CMOS technology.
■ FEATURES
•
•
•
•
•
•
•
•
•
Resolution
:
Linearity error
:
Maximum conversion rate
:
Power supply voltage
:
Digital input/output voltage range :
Analog input voltage range
:
Analog input capacitance
:
Power dissipation
:
Additional features
:
• Package
8 bit
±0.40% (standard)
100 MSPS (minimum)
3.3 V single (standard)
CMOS level compatible
0 to 3.0 V (2 Vp-p)
22 pF (standard)
210 mW (standard)
Reference voltage generator circuit: VREFT = 3.0 V, VREFB = 1.0 V
High impedance output, power down function
1:2 demultiplex output enable (RESET action enable)
1/2 deviding clock output
Cross sampling at 50 MHz (two-phase CLK) enable (CLKA, CLKB)
: LQFP48 (7 mm × 7 mm, lead pitch 0.5 mm)
■ PACKAGE
48-pin plastic LQFP
(FPT-48P-M05)
MB40C328
VR3
VREFT
VRT
AVDD
AVSS
DVDD
CLKOA
DVSS
DA0 (LSB)
DA1
DA2
DA3
48
47
46
45
44
43
42
41
40
39
38
37
■ PIN ASSIGNMENT
VR2
1
36
DA4
VR1
2
35
DA5
AVDD
3
34
DA6
AVSS
4
33
DA7 (MSB)
VREFB
5
32
DVSS
VRB
6
31
CLKA
AVSS
7
30
CLKB
(TOP VIEW)
2
22
23
24
DB3
DB2
DB1
DB4
25
21
12
DB5
AVSS
20
DB0 (LSB)
DB6
26
19
11
(MSB) DB7
CE
18
DVDD
DVSS
27
17
10
CLKOB
CKSEL
16
RESET
DVDD
28
15
9
DSEL
AVDD
14
CLK
OE
29
13
8
AVDD
VINA
MB40C328
■ PIN DESCRIPTION
Pin No.
Symbol
Description
3, 9, 13, 45
AVDD
Analog power supply (+3.3 V)
16, 27, 43
DVDD
Digital power supply (+3.3 V)
4, 7, 12, 44
AVSS
Analog power supply ground pin (0 V)
18, 32, 41
DVSS
Digital power supply ground pin (0 V)
33 to 40
DA7 to DA0
Digital output pin (Port A) DA7: MSB, DA0: LSB
19 to 26
DB7 to DB0
Digital output pin (Port B) DB7: MSB, DB0: LSB
11
CE
Power down at CE input “H” (internal pull-up resistor)
14
OE
Digital output (Both Port A, B) and clock output (CLKOA, CLKOB) are high
impedance at OE input “H”.
10
CKSEL
15
DSEL
28
RESET
29
CLK
31
CLKA
A ch clock input pin (max 50 MHz)
30
CLKB
B ch clock input pin (max 50 MHz)
42
CLKOA
Clock output pin (See ■ TIMING CHART 1 to 4)
17
CLKOB
Clock output pin (See ■ TIMING CHART 1 to 4)
8
VINA
Analog input pin
Input range is VRT to VRB (0 V to 3.0 V: 2 Vp-p)
2
1
48
VR1
VR2
VR3
Reference 1/4 voltage output pin (Add 0.1 µF for AVSS)
Reference 1/2 voltage output pin (Add 0.1 µF for AVSS)
Reference 3/4 voltage output pin (Add 0.1 µF for AVSS)
46
VRT
Reference voltage input pin on top side
47
VREFT
6
VRB
5
VREFB
Mode of operation setting input pin (Refer to ■ MODE SETTING)
Dividing circuit reset input pin (See ■ TIMING CHART 2, 3)
Clock input pin (max 100 MHz)
Reference voltage output pin
By connecting to VRT, 0.9 × AVDD (.=. 3 V) is generated.
Reference voltage input pin on bottom side
Reference voltage output pin
By connecting to VRB, 0.3 × AVDD (.=. 1 V) is generated.
The values in parentheses are standard.
■ PRECAUTIONS ON USE
• Be sure to ground the pins of AVDD, DVDD, VRT, VRB, VR1, VR2, and VR3 via high-frequency capacitor.
Place the high-frequency capacitor as close as possible to the pin.
• To avoid generation of undesired current owing to indetermination of internal logic, set CE to “H” at powering
on and input more than five clock pulses just after operation (CE: “H” → “L”).
3
MB40C328
■ BLOCK DIAGRAM
CKSEL DSEL
VINA
CLKOA
AVDD
DVDD
VREFT
AVDD
Mode
setting
VRT
Timing
circuit
CLKA
CLK
CLK
select
VR3
VR2
VR1
B ch
CLKB
A output
buffer
DA0 to DA7
B output
buffer
DB0 to DB7
Output selector
FF
A ch
FF
Timing
circuit
VRB
AVDD
AVSS
RESET
4
CE
CLKOB
AVSS
DVSS
OE
VREFB
MB40C328
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input/output voltage
Storage temperature
Symbol
Rating
Unit
Min.
Max.
–0.3
+4.0
V
VINA, VRT, VRB,
VREFT, VREFB,
VR1, VR2, VR3, CE,
CKSEL
–0.3
AVDD+0.3*
V
DA0 to DA7, DB0 to DB7,
CLKOA, CLKOB,
CLKA, CLKB,
CLK, DSEL, OE,
RESET
–0.3
DVDD+0.3*
V
TSTG
–55
+125
°C
AVDD, DVDD
* : Do not exceed +4.0 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
5
MB40C328
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Min.
Typ.
Max.
Unit
Power supply voltage
AVDD, DVDD
3.00
3.30
3.60
V
Analog input voltage
VINA
VRB
—
VRT
V
Analog reference voltage: T
VRT
—
—
3.00
V
Analog reference voltage: B
VRB
0.00
—
—
V
VRT – VRB
1.90
2.00
2.10
V
DVDD – 0.5
—
—
V
AVDD – 0.5
—
—
V
—
—
0.5
V
—
—
0.5
V
Analog reference voltage range
Digital “H” level
input voltage
Digital “L” level input
voltage
OE, DSEL, RESET,
CLK, CLKA, CLKB
VIHD
CKSEL, CE
OE, DSEL, RESET,
CLK, CLKA, CLKB
VILD
CKSEL, CE
Digital input current
IID
–20
—
5
µA
Single-phase clock frequency
fCLK
0.1
—
100
MHz
Two-phase clock frequency
fCLKA, fCLKB
0.1
—
50
MHz
Minimum clock pulse width (single-phase)
tWS+, tWS–
4.0
5.0
—
ns
Minimum clock pulse width (two-phase)
tWD+, tWD–
8.0
10.0
—
ns
tr, tf
—
2.0
—
ns
RESET signal setup time
ts
3.0
—
—
ns
RESET signal hold time
th
3.0
—
—
ns
Operating temperature range
Ta
–20
—
70
°C
Clock pulse rising/falling time
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
6
MB40C328
■ ELECTRICAL CHARACTERISTICS
• DC Characteristics in Analog Section
(AVDD = DVDD = 3.00 V to 3.60 V, Ta = –20°C to +70°C)
Parameter
Symbol
Value
Min.
Typ.
Max.
Unit
Resolution
—
—
8
—
bit
Linearity error
LE
—
±0.40
±0.6
%
Differential linearity error
DLE
—
±0.20
±0.36
%
Analog input capacity
CINA
—
22
—
pF
Reference voltage: T
VREFT
0.88 × AVDD
0.91 × AVDD
0.94 × AVDD
V
Reference voltage: B
VREFB
0.27 × AVDD
0.3 × AVDD
0.33 × AVDD
V
IRB
–15
–10
—
mA
Analog supply current
AIDD
—
42.0
85.0
mA
Digital supply current
DIDD
—
20.0
40.0
mA
ISB
—
100
—
mA
Reference current
Standby current
• DC Characteristics in Digital Section
(AVDD = DVDD = 3.00 V to 3.60 V, Ta = –20°C to +70°C)
Parameter
Symbol
Value
Min.
Typ.
Max.
Unit
Digital “H” level output voltage
VOHD
DVDD – 0.4
—
DVDD
V
Digital “L” level output voltage
VOLD
—
—
0.4
V
Digital “H” level output current
IOHD
–400
—
—
µA
Digital “L” level output current
IOLD
—
—
1.6
mA
7
MB40C328
• Switching Characteristics
(AVDD = DVDD = 3.00 V to 3.60 V, Ta = –20°C to +70°C)
Parameter
Value
Symbol
Min.
Typ.
Max.
Unit
Maximum conversion rate
fS
100
—
—
MSPS
Aperture time
tAD
—
1.7
—
ns
tpdS
2.5
6.0
9.0
ns
tpdSO
tWS+ + 2.5
tWS+ + 6.0
tWS+ + 10
ns
tpdM1
2.5
5.5
10
ns
tpdM1O
T + 2.5
T + 5.5
T + 10
ns
tpdM2
2.5
5.5
10
ns
tpdM2O
T + 2.5
T + 5.5
T + 10
ns
11
ns
Timing chart 1
Timing chart 2
Digital output
delay time
Timing chart 3
tpdD
Timing chart 4
2.5
tpdDO
WD+
t
+ 2.5
6.5
t
WD+
+ 6.5
t
WD+
+ 11
ns
■ DIGITAL OUTPUT BUFFER LOAD CIRCUIT
To the
measurement
point
Measurement point
CL = 18 pF
DVSS
Note: CL includes a stray capacitance of a probe and a fixture.
■ MODE SETTING
8
CKCEL
DCEL
Mode
Timing Chart
H
H
CLK input-straight output mode
Timing chart 1
H
L
CLK input-demultiplex output (in-phase) mode
Timing chart 2
L
H
CLK input-demultiplex output (two-phase) mode
Timing chart 3
L
L
Two-phase CLK input mode (CLKA, CLKB)
Timing chart 4
MB40C328
■ TIMING CHART 1
CLK input-straight output mode
•
•
•
•
•
•
•
CLK = 100 MHz (max)
CLKA = CLKB = “L” (DVSS)
CKSEL = “H” (AVDD)
DSEL = “H” (DVDD)
RESET = “H” (DVDD)
CE = “L” (AVSS)
OE = “L” (DVSS)
tr
VINA input
VOHD
DB0 to DB7
VOLD
N+1
N
1.5 V
N+2
N+3
N+4
tAD
N−7
N−6
N+5
N+6
tpdS (max)
tpdS (typ)
tpdS (min)
N−5
N−4
N−3
N−2
N−1
N+7
N
DVDD − 0.4 V
N+1
0.4 V
ALL “L” fix
tpdSO(max)
tpdSO(typ)
tpdSO(min)
VOHD
CLKOA
VOLD
VOHD
CLKOB
VOLD
tWS−
DVDDI − 0.5 V
0.5 V
N−1
VOHD
DA0 to DA7
VOLD
tWS+
tf
VIHD
CLK input
VIHD
DVDD − 0.4 V
0.4 V
ALL “L” fix
• VINA input — Sampling at CLK rising
• DA0 to DA7 — Output (after 5 CLK + tpdS from Sampling) at CLK rising
9
MB40C328
■ TIMING CHART 2
CLK input-demultiplex output (in-phase) mode
•
•
•
•
•
•
CLK = 100 MHz (max)
CLKA = CLKB = “L” (DVSS)
CKSEL = “H” (AVDD)
DSEL = “L” (DVSS)
CE = “L” (AVSS)
OE = “L” (DVSS)
tf
tr
VIHD
CLK input
VILD
tWS+ tWS−
T
DVDD − 0.5 V
0.5 V
N−1
N−2
N−1
N+1
N
VINA input
1.5 V
N+2
N+3
N+4
tAD
N−9
N−9
VOHD or N − 10 or N − 8
DA0 to DA7
VOLD
N − 10
N−7
or N − 8
N − 10 N − 8
N−5
or N − 6
N−3
or N − 4
N−6
or N − 7
N−4
or N − 5
N−8
VOHD or N − 11 or N − 9 or N − 9 or N − 7
DB0 to DB7
VOLD
VOHD
CLKOA
VOLD
VOHD
CLKOB
VOLD
tS
th
tS
1.5 V
• VINA input — Sampling at CLK rising
• DA0 to DA7 — Output (after 5 CLK + tpdM1 from Sampling) at CLK rising
• DB0 to DB7 — Output (after 6 CLK + tpdM1 from Sampling) at CLK rising
10
N+6
N+7
N+8
N+9
tpdM1(max)
tpdM1(typ)
tpdM1(min)
N+1
DVDD − 0.4 V
N−1
N+3
or N − 2
0.4V
tpdM1(max)
tpdM1(typ)
tpdM1(min)
N
N−2
DVDD − 0.4 V
N+2
or N − 3
0.4V
tpdM1O(max)
tpdM1O(typ)
tpdM1O(min)
DVDD − 0.4 V
0.4 V
ALL “L” fix
th
VIHD
RESET input
VILD
N+5
N + 10
MB40C328
■ TIMING CHART 3
CLK input-demultiplex output (two-phase) mode
•
•
•
•
•
•
CLK = 100 MHz (max)
CLKA = CLKB = “L” (DVSS)
CKSEL = “L” (AVSS)
DSEL = “H” (DVDD)
CE = “L” (AVSS)
OE = “L” (DVSS)
tr
tf
DVDD − 0.5 V
VIHD
CLK input
VILD
tWS+ tWS−
T
1.5 V
0.5 V
N−3
N−2
N−1
N
VINA input
N+1
N+2
N+3
N+4
N+5
tAD
N−9
tpdM2(max)
tpdM2(typ)
tpdM2(min)
N−9
VOHD or N − 10 or N − 8
DA0 to DA7
VOLD
N − 10
N−8
N−7
or N − 8
N−5
or N − 6
N−3
or N − 4
N−8
VOHD or N − 9 or N − 9 or N − 7
DB0 to DB7
VOLD
N−6
or N − 7
N−4
or N − 5
N−1
or N − 2
tpdM2(max)
tpdM2(typ)
tpdM2(min)
N−2
or N − 3
VOHD
CLKOA
VOLD
N+7
N+8
N+9
N+1
DVDD − 0.4 V
0.4 V
N + 10
N+3
N
DVDD−0.4 V
0.4 V
tpdM2O(max)
tpdM2O(typ)
tpdM2O(min)
N+2
DVDD − 0.4 V
0.4 V
tpdM2O(max)
tpdM2O(typ)
tpdM2O(min)
VOHD
CLKOB
VOLD
DVDD − 0.4 V
0.4 V
th
VIHD
RESET input
VILD
N+6
tS
th
tS
1.5 V
• VINA input — Sampling at CLK rising
• DA0 to DA7 — Output (after 5 CLK + tpdM2 from Sampling) at CLK rising
• DB0 to DB7 — Output (after 5 CLK + tpdM2 from Sampling) at CLK rising
11
MB40C328
■ TIMING CHART 4
Two-phase CLK input mode (CLKA, CLKB)
•
•
•
•
•
•
•
CLK = “L” (DVSS) or “H” (DVDD)
CLKA = CLKB = 50 MHz (max)
CKSEL = “L” (AVSS)
DSEL = “L” (DVSS)
RESET = “H” (DVDD) or “L” (DVSS)
CE = “L” (AVSS)
OE = “L” (DVSS)
tWD−
tWD+
tr
tf
VIHD
CLKA input
VILD
DVDD − 0.5 V
0.5 V
tWD+
tWD−
tr
tf
VIHD
CLKB input
VILD
DA0 to DA7
VINA input
VOHD
DA0 to DA7
VOLD
VOHD
DB0 to DB7
VOLD
1.5 V
DVDD − 0.5 V
0.5 V
N(Ach)
tAD
N + 1(Bch) N + 2(Ach) N + 3(Bch) N + 4(Ach) N + 5(Bch) N + 6(Ach) N + 7(Bch)
tAD
N−6
tpdD(max)
tpdD(typ)
tpdD(min)
N−4
N−5
N−2
N−3
N
DVDD−0.4 V
0.4 V
tpdD(max)
tpdD(typ)
tpdD(min)
N−1
tpdDO(max)
tpdDO(typ)
tpdDO(min)
VOHD
CLKOA
VOLD
VOHD
CLKOB
VOLD
• VINA input — Sampling (A ch) at CLKA falling
Sampling (B ch) at CLKB falling
• DA0 to DA7 — Output (after 2.5 CLK + tpdD from Sampling) at CLKA rising
• DB0 to DB7 — Output (after 2.5 CLK + tpdD from Sampling) at CLKB rising
12
1.5 V
N+1
DVDD − 0.4 V
0.4 V
DVDD − 0.4 V
0.4 V
tpdDO(max.)
tpdDO(typ)
tpdDO(min.)
DVDD − 0.4 V
0.4 V
MB40C328
DA3
DA2
DA1
VRT
CLKOA
DA0(LSB)
■ TYPICAL CONNECTION EXAMPLE
+
+
DA4 36
DA4
2 VR1
DA5 35
DA5
3 AVDD
DA6 34
DA6
4 AVSS
(MSB)DA7 33
5 VREFB
DVSS 32
6 VRB
(TOP VIEW)
7 AVSS
VINA
DA3 37
DA2 38
DA1 39
DVSS 41
(LSB)DA0 40
1 VR2
CLKOA 42
DVDD 43
AVSS 44
AVDD 45
VR3 48
VRB
VRT 46
+3.3 V
VREFT 47
+3.3 V
CLKA 31
CLKA
CLKB 30
CLKB
8 VINA
CLK 29
9 AVDD
CKSEL
RESET 28
10 CKSEL
20 DB6
21 DB5
22 DB4
23 DB3
24 DB2
DB5
DB4
DB3
DB2
DB1 25
DB6
19 DB7(MSB)
(MSB)DB7
18 DVSS
16 DVDD
17 CLKOB
CLKOB
0.1 µF
DSEL
OE
14 OE
12 AVSS
15 DSEL
(LSB)DB0 26
13 AVDD
CLK
RESET
DVDD 27
11 CE
CE
DA7(MSB)
DB0(LSB)
DB1
+ To avoid voltage fluctuation at operation of reference voltage generator circuit (VREFT, VREFB)
VREFT: 150 µF, VREFB: 330 µF
13
MB40C328
■ ORDERING INFORMATION
Part number
MB40C328PFV
14
Package
48-pin Plastic LQFP
(FPT-48P-M05)
Remark
MB40C328
■ PACKAGE DIMENSION
48-pin Plastic LQFP
(FPT-48P-M05)
Note ) Pins width and pins thickness include plating thickness.
9.00±0.20(.354±.008)SQ
7.00±0.10(.276±.004)SQ
36
25
37
24
0.08(.003)
INDEX
Details of "A" part
+0.20
1.50 –0.10
48
13
+.008
(Mounting height)
.059 –.004
"A"
LEAD No.
1
0.50±0.08
(.020±.003)
12
+0.08
0.18 –0.03
.007
+.003
–.001
0.08(.003)
M
0.145±0.055
(.006±.002)
0~8°
0.50±0.20
(.020±.008)
0.45/0.75
(.018/.030)
C
1998 FUJITSU LIMITED F48013S-3C-6
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
15
MB40C328
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka,
Nakahara-ku, Kawasaki-shi,
Kanagawa 211-8588, Japan
Tel: +81-44-754-3763
Fax: +81-44-754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, USA
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
F0001
 FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without
notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipments, industrial, communications, and
measurement equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
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prior authorization by Japanese government should be required
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