FUJITSU SEMICONDUCTOR DATA SHEET DS04-28219-1E ASSP For Video Applications CMOS 3 ch 8-bit 100 MSPS A/D Converter MB40C348 ■ DESCRIPTION MB40C348 is a high-speed 3ch A/D converter using a fast CMOS technology. ■ FEATURES • • • • • • • • • • • Resolution No. of AD channels Linearity error Maximum conversion rate Power supply voltage Digital input voltage range Digital output voltage range Amp. input voltage range Amp. gain Power dissipation Additional features • Package : 8 bit : 3 ch : ±0.40% (typical) : 100 MSPS (minimum) : 3.3 V (typical: internal circuit) : TTL level : 3.3 V CMOS level : 0.7 VP-P (typical) : 1.9 double fixed : 880 mW (typical) : PLL circuit Video Amp. circuit (1.9 double fixed gain) CLAMP circuit VRT Amp. circuit (RGB 3 ch common) VRB Amp. circuit (RGB 3 ch common) Overflow output High impedance output, power down function : LQFP120 (16 mm ×16mm, lead pitch : 0.5 mm) ■ PACKAGE 120-pin plastic LQFP (FPT-120P-M21) MB40C348 ■ PIN ASSIGNMENT 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 PVSS PVDD HSYNC HHOLD PVDD LPF PVSS RREF VREFT VRT VRTM VR3 AVSS AVDD DVDD DVSS OF DSYNC DSYNCB COUT EXPCLK EXPCLKB EXCLK ADCLKA ADCLKB CLK CLKB DVDD DVSS AVSS (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 BDB5 BDB4 BDB3 BDB2 BDB1 (LSB) BDB0 DVSS DVDD (MSB) BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 (LSB) BDA0 AVDD AVSS DVSS DVDD (MSB) GDB7 GDB6 GDB5 GDB4 GDB3 GDB2 GDB1 (LSB) GDB0 DVDD DVSS 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 RVIN VR2 GVIN CE BVIN VR1 VREF PCLP AVDD AVSS RADIN DSEL GADIN VESD BADIN VRBM VRB VREFB RVCLP GVCLP BVCLP AVSS AVDD CS CK DATA DVSS DVDD (MSB) BDB7 BDB6 (FPT-120P-M21) 2 RDA0 (LSB) RDA1 RDA2 RDA3 RDA4 RDA5 RDA6 RDA7 (MSB) DVDD DVSS AVSS AVDD RDB0 (LSB) RDB1 RDB2 RDB3 RDB4 RDB5 RDB6 RDB7 (MSB) DVDD DVSS GDA0 (LSB) GDA1 GDA2 GDA3 GDA4 GDA5 GDA6 GDA7 (MSB) MB40C348 ■ PIN DESCRIPTION Pin No. Symbol Description 9, 23, 47, 79, 107 AVDD Analog power supply (+3.3 V) 28, 38, 50, 59, 70, 82, 93, 106 DVDD Digital power supply (+3.3 V) 116, 119 PVDD PLL power supply (+3.3 V) 14 VESD Digital input power supply for protect device (+3.3 V or +5 V) 10, 22, 48, 80, 91, 108 AVSS Analog power supply ground pin (0 V) 27, 37, 49, 60, 69, 81, 92, 105 DVSS Digital power supply ground pin (0 V) 114, 120 PVSS PLL power supply ground pin (0 V) 1 3 5 RVIN GVIN BVIN 1.9 double Amp. input pin 11 13 15 RADIN GADIN BADIN A/D converter input pin Please set these pins to open usually. 19 20 21 RVCLP GVCLP BVCLP Clamp voltage setting input pin 110 VRTM Reference voltage output pin on top side 111 VRT Reference voltage input pin on top side 112 VREFT Reference voltage generator output pin on top side 16 VRBM Reference voltage output pin on bottom side 17 VRB Reference voltage input pin on bottom side 18 VREFB Reference voltage generator output pin on bottom side 6 2 109 VR1 VR2 VR3 Reference 1/4 voltage output pin (Add 0.1 µF for AVSS) Reference 1/2 voltage output pin (Add 0.1 µF for AVSS) Reference 3/4 voltage output pin (Add 0.1 µF for AVSS) 12 DSEL 25 CK 26 DATA 24 CS 98 EXCLK Mode of operation setting input pin (Refer to ■ MODE SETTING) Serial data transfer clock input pin Serial data input pin Chip select signal input pin It is possible to input to the shift register at CS falling The content of the shift register is executed at CS rising Clock input pin for A/D converter (CMOS level) Fix to “L” level when unused. Note: The values in parentheses are standard. (Continued) 3 MB40C348 (Continued) Pin No. Symbol Description 99 EXPCLKB Differential clock (positive-phase) input pin for A/D converter Fix to “H” level when unused. 100 EXPCLK Differential clock (negative-phase) input pin for A/D converter Fix to “L” level when unused. 8 PCLP 4 CE Power down at CE input “H” level (internal pull-up resistor) 113 RREF Internal current setting pin (Add 12kΩ for AVss) 103 DSYNC 102 DSYNCB 95 CLK 94 CLKB 97 ADCLKA 96 ADCLKB 83 to 90 61 to 68 39 to 46 RDA7 to RDA0 GDA7 to GDA0 BDA7 to BDA0 Digital output pin (Port A) RDA7, GDA7, BDA7 : MSB RDA0, GDA0, BDA0 : LSB 71 to 78 51 to 58 29 to 36 RDB7 to RDB0 GDB7 to GDB0 BDB7 to BDB0 Digital output pin (Port B) RDB7, GDB7, BDB7 : MSB RDB0, GDB0, BDB0 : LSB 101 COUT 115 LPF 117 HHOLD Phase detector operation is hold by input “H” level 118 HSYNC Horizontal sync signal input pin 7 VREF Internal voltage output pin (Add 3.3 µF for AVss) 104 OF Overflow output pin (“H” level output at overflow) Clamp pulse input pin Delay sync signal output pin Inverted delay sync signal output pin Clock output pin (See “ ■ TIMING DIAGRAM ”.) PLL counter output pin External capacitor / resistor connection pin Note: The values in parentheses are standard. 4 PECL level MB40C348 ■ BLOCK DIAGRAM VESD VREFT VREFB AVDD R DVDD VRTM VRT VRB VRBM VR1 VR2 VR3 VREF Amp. Block R OF PCLP RADIN × 3 ch AMP + CLAMP + A/D × 1.9 A ch 8 8 bit A/D RVIN Buffer 8 RDA0 ∼ RDA7 B ch 8 8 bit A/D 8 Buffer RDB0 ∼ RDB7 Buffer ADCLKA Buffer ADCLKB RVCLP PLL Block CE RESET AVSS 1/2 2 bit (0 ∼ 3 CLK) DVSS Buffer DSYNC Buffer DSYNCB DIV Buffer CLK 2 bit (1 ∼ 1/8) Buffer CLKB Delay CLK Delay 6 bit (32 divide, 2CLK) HSYNC POL PD CP VCO (1 bit) MUX Counter HHOLD 11 bit Shift (12 bit) COUT LPF EXPCLKB EXCLK EXPCLK PVSS PVDD CK DATA CS Filter 5 MB40C348 ■ ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Input/output voltage Storage temperature Symbol Rating Unit Min. Max. AVDD, DVDD, PVDD −0.3 +4.0 V VESD −0.3 +7.0 V RVIN, GVIN, BVIN, RADIN, GADIN, BADIN, RVCLP, GVCLP, BVCLP, VRT, VRTM, VREFT, VRB, VRBM, VREFB, VR1, VR2, VR3 VREF, RREF −0.3 AVDD+0.3*1 V RDA0 to RDA7, RDB0 to RDB7, GDA0 to GDA7, GDB0 to GDB7, BDA0 to BDA7, BDB0 to BDB7, DSYNC, DSYNCB, OF, COUT, CLK, CLKB, ADCLKA, ADCLKB −0.3 DVDD+0.3*1 V LPF −0.3 PVDD+0.3*1 V DSEL, CK, DATA, CS, EXPCLKB, EXPCLK, PCLP, CE, EXCLK, HHOLD, HSYNC −0.3 VESD+0.3*2 V TSTG −55 +125 °C *1 : Do not exceed +4.0 V. *2 : Do not exceed +7.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 6 MB40C348 ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Min. Typ. Max. AVDD, DVDD 3.00 3.30 3.60 V PVDD 3.00 3.30 3.60 V VESD 3.00 5.25 V A/D converter input voltage VADIN VRB VRT V Analog reference voltage : T VRT 2.2 AVDD − 0.6 V Analog reference voltage : B VRB 0.6 0.7 V VRT − VRB 1.0 1.5 1.8 V VIN (P-P) 0.5 0.9 VP-P Clamp input voltage VCLP 0.6 VRB 1.7 V Digital “H” level input voltage VIHD 2.5 VESD V Digital “L” level input voltage VILD 0 0.5 V Digital “H” level output current IOHD −400 µA Digital “L” level output current IOLD 1.6 mA PLL counter PC 100 4095 HSYNC input frequency range fHSYNC 10 100 kHz HHOLD set up time tsHHOLD 20 ns HHOLD hold time thHHOLD 20 ns Clamp pulse width tWCLP 0.5 µs tWCKL, tWCKH 100 ns DATA set up time tsDATA 30 ns DATA hold time thDATA 30 ns CS set up time tsCS 50 ns CS hold time thCS 50 ns tWCSH 100 ns Ta −20 70 °C Power supply voltage Analog reference voltage range Video Amp. input voltage CK clock pulse width CS “H” level hold time Operating temperature range WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 7 MB40C348 ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics in Analog Section • Power supply current (AVDD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, Ta = −20 °C to +70 °C) Value Parameter Symbol Unit Min. Typ. Max. Analog power supply current AIDD 170 290 mA Digital power supply current DIDD 80 90 mA Power supply current PLL section (@fVCOH = 162 MHz, Icp = 0.5 mA, DIV = 1/1) PIDD 16 20 mA ISB 10 mA Standby current • Block A/D Parameter (AVDD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, Ta = −20 °C to +70 °C) Value Symbol Unit Min. Typ. Value Resolution 8 bit Linearity error (DC Accuracy) LE −0.8 ±0.4 +0.8 % Differential linearity error (DC Accuracy) DLE −0.36 ±0.2 +0.65 % Reference voltage : T VREFT 0.63 ×AVDD 0.67 ×AVDD 0.70 ×AVDD V Reference voltage : B VREFB 0.18 ×AVDD 0.21 ×AVDD 0.24 ×AVDD V Analog reference voltage input current IRT, IRB 5 20 µA (AVDD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, Ta = −20 °C to +70 °C) Value Parameter Symbol Unit Min. Typ. Value • Video Amp. Block GAMP 1.8 1.9 2.0 VAMPOUT 0.5 AVDD − 0.6 V Video Amp. frequency width BW 170 MHz Video Amp. input capacity CVIN 5 pF Video Amp. gain Video Amp. output voltage range • CLAMP Block Parameter VCLP input current Clamp voltage • PLL Block (AVDD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, Ta = −20 °C to +70 °C) Value Symbol Unit Min. Typ. Value ICLP 5 20 µA VCLAMP VCLP − 0.1 VCLP VCLP + 0.1 V (AVDD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, Ta = −20 °C to +70 °C) Value Parameter Symbol Unit Min. Typ. Value CLK jitter (@fHSYNC = 68.68 kHz, fCLK = 94.5 MHz) 8 Ptj 1.0 1.5 ns MB40C348 2. DC Characteristics in Digital Section (AVDD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, Ta = −20 °C to +70 °C) Parameter Value Symbol Unit Min. Typ. Max. IID −20 5 µA Digital “H” level output voltage VOHD DVDD − 0.4 V Digital “L” level output voltage VOLD 0.4 V Digital input current 3. Switching Characteristics (AVDD = DVDD = PVDD = 3.0 V to 3.6 V, VESD = 3.0 V to 5.25 V, Ta = −20 °C to +70 °C) Parameter Value Symbol Min. Typ. Max. Unit A/D maximum conversion rate fS 100 MSPS Aperture time tAD 1.5 ns VCOL fVCOL 75 140 MHz VCOH fVCOH 85 162 MHz tpd (HSYNC-CLK) 1.0 2.0 4.0 ns Timing diagram 1 tpd (CLK-ADCLK1) 0.0 1.0 2.0 ns tpd (CLK-DATA1) 2.5 4.0 6.0 ns Timing diagram 2 tpd (CLK-ADCLK2) 0.0 1.0 2.0 ns tpd (CLK-DATA2) 2.5 4.0 6.0 ns tpd (CLK-DSYNC) 0.5 1.5 2.0 ns VCO oscillation frequency CLK output delay time Digital output delay time DSYNC output delay time ■ DIGITAL OUTPUT BUFFER LOAD CIRCUIT To the measurement point Measurement point CL = 15 pF DVSS Note: CL includes a stray capacitance of a probe and a fixture. ■ MODE SETTING Pin DSEL CE Setting Mode Timing Diagram H Straight output mode Timing diagram 1 L Demultiplex output (in-phase) mode Timing diagram 2 H All function power OFF L Operation mode 9 MB40C348 ■ SERIAL DATA SETTING (MSB Fast) (Address) (Data) LSB RES D0 MSB D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Function 1 1 0 0 0 0 0 0 0 0 1 0 Counter low ranking 8 bit 2 0 1 0 0 0 0 0 X X X X Counter high ranking 4 bit 1 1 0 0 0 0 0 0 0 1 0 CLK delay adjust*1 : td = N/ (32 ×fCLK) 1 1 0 0 0 0 0 0 0 1 0 HSYNC polarity : 0 = through, 1 = inversion 1 1 0 0 0 0 0 0 0 1 0 A/D converter output : 0 = operation, 1 = high impedance 0 0 1 0 0 0 0 0 0 1 0 CLK output : 0 = on, 1 = “L” 0 0 1 0 0 0 0 0 0 1 0 CLKB output : 0 = on, 1 = “L” 0 0 1 0 0 0 0 0 0 1 0 DSYNC output : 0 = on, 1 = “L” 0 0 1 0 0 0 0 0 0 1 0 DSYNCB output : 0 = on, 1 = “L” 0 0 1 0 0 0 0 0 0 1 0 ADCLKA output : 0 = on, 1 = “L” 0 0 1 0 0 0 0 0 0 1 0 ADCLKB output : 0 = on, 1 = “L” 0 0 1 0 0 0 0 0 0 1 0 DSYNC delay*2 : 0, 1, 2, 3 1 0 1 0 0 0 0 0 0 1 0 CLK change : 0 = VCO, 1 = External clock 1 0 1 0 0 0 0 0 0 1 0 External clock input : 0 = CMOS, 1 = PECL 1 0 1 0 0 0 0 0 0 1 0 Counter operation : 0 = on, 1 = off 1 0 1 0 0 0 0 0 0 1 0 Charge pump current*3 : 0.1 mA, 0.5 mA, 1 mA 1 0 1 0 0 0 0 0 0 1 0 VCO select : 0 = VCOL, 1 = VCOH 1 0 1 0 0 0 0 0 0 1 0 Divider setting*4 : 1, 1/2, 1/4, 1/8 3 4 5 *1 : Setting at 6bit, Resolution: 1/32 ×CLK, Setting range: 0 to 63/32 ×CLK *2, *3, *4 : See under table Setting DSYNC Delay*2 Charge pump current* Divider setting* 3 4 0 (0, 0) 1 (1, 0) 2 (0, 1) 3 (1, 1) 0 CLK 1 CLK 2 CLK 3 CLK 0.1 mA 0.5 mA 1.0 mA 1/1 1/2 1/4 1/8 Example: input at 16 bit MSB DATA input The invalid data (5 bit) CS input 10 LSB DATA (8 bit) Address (3 bit) MB40C348 ■ RECOMMEND VALUE OF SERIAL DATA SETTING XGA SVGA VGA PAL NTSC fCLK (MHz) fHSYNC (kHz) Counter Icp (mA) VCO select Divider fVCO (MHz) 94.500 68.677 1376 0.5 VCOH or VCOL 1/1 94.500 78.750 60.023 1312 0.5 VCOL 1/1 78.750 75.000 56.476 1328 0.5 VCOH 1/2 150.000 65.000 48.363 1344 0.5 VCOH or VCOL 1/2 130.000 56.250 53.674 1048 0.5 VCOH or VCOL 1/2 112.500 50.000 48.077 1040 0.5 VCOH or VCOL 1/2 100.000 49.500 46.875 1056 0.5 VCOH or VCOL 1/2 99.000 40.000 37.879 1056 0.5 VCOL 1/2 80.000 36.000 43.269 832 0.5 VCOH 1/4 144.000 31.500 37.861 832 0.5 VCOH or VCOL 1/4 126.000 25.175 31.469 800 0.5 VCOH or VCOL 1/4 100.700 25.149 31.436 800 0.5 VCOH or VCOL 1/4 100.596 29.375 15.625 1880 0.5 VCOH or VCOL 1/4 117.500 22.031 15.625 1410 0.5 VCOH or VCOL 1/4 88.125 14.688 15.625 940 0.5 VCOH or VCOL 1/8 117.500 24.545 15.734 1560 0.5 VCOH or VCOL 1/4 98.180 18.409 15.734 1170 0.5 VCOH 1/8 147.270 12.273 15.734 780 0.5 VCOH or VCOL 1/8 98.180 VCO select : VCOH (fVCO = 85 MHz to 162 MHz) VCOL (fVCO = 75 MHz to 140 MHz) fCLK = fHSYNC ×Counter fVCO = fHSYNC ×Counter/Divider 11 MB40C348 ■ TIMING DIAGRAM • Straight Output Mode (Timing Diagram 1) VIHD HSYNC input VILD tpd (HSYNC-CLK) VOHD CLK output CLKB output VOLD tpd (CLK-DSYNC) VOHD DSYNC output VOLD tpd (CLK-ADCLK1) VOHD ADCLKA output VOLD VOHD ADCLKB output VOLD N+1 N N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 ADIN input tAD tpd (CLK-DATA1) VOHD DA0 to DA7 output X X X X X X X X N N+1 N+2 N+3 X X N N+1 N+2 N+3 VOLD VOHD ALL “L” fix DB0 to DB7 output VOLD VOHD OF output X X X X X X VOLD • ADIN input : Sampling at CLK rising (at CLKB falling) • DA0 to DA7 : Output (after 5CLK + tpd(CLK−DATA1) from sampling) at CLK rising (at CLKB falling) 12 MB40C348 • Demultiplex Output (in-phase) Mode (Timing Diagram 2) VIHD HSYNC input VILD tpd (HSYNC-CLK) VOHD CLKB output CLK output VOLD tpd (CLK-DSYNC) VOHD DSYNC output VOLD tpd (CLK-ADCLK2) VOHD ADCLKA output VOLD VOHD ADCLKB output VOLD N+1 N N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 ADIN input tAD tpd (CLK-DATA2) VOHD DA0 to DA7 output X X X X X N N+2 X X X X X N+1 N+3 X X X X X N N+2 VOLD VOHD DB0 to DB7 output VOLD VOHD OF output VOLD • ADIN input : Sampling at CLK rising (at CLKB falling) • DA0 to DA7 : Output (after 6CLK + tpd(CLK−DATA2) from sampling) at CLK rising (at CLKB falling) • DB0 to DB7 : Output (after 5CLK + tpd(CLK−DATA2) from sampling) at CLK rising (at CLKB falling) 13 MB40C348 ■ CLAMP and Amp. OPERATION Amp./CLAMP circuit − + RVIN Image signal RVCLP Clamp pulse + 10 µF × 1.9 RADIN − R1 R2 Internal BIAS (0.6 ×AVDD) Example: Sync on G signal input > 0.7 Vp-p GVIN PCLP VRT 1.33 VP-P (fixed) GADIN GVCLP VRB Contrast adjust : controlling the voltage difference between VRT and VRB (typ : VRT − VRB = 1.33 V) Brightness adjust : controlling the voltage difference between VCLP and VRB. (typ : VCLP = VRB) 14 MB40C348 ■ CLAMP SIGNAL and HOLD SIGNAL HSYNC input thHHOLD tsHHOLD thHHOLD tsHHOLD HHOLD input tWCLP PCLP input CLK output ■ SERIAL DATA TRANSFER TIMING DATA input D10 D9 tWCKL tWCKH D8 D7 D1 D0 tsDATA thDATA CK input tsCS thCS tWCSH CS input 15 AVDD (+3.3 V) AVSS (0 V) + 100 µF Serial Data VRB/VCLP +3.3 V or +5 V DSEL 10 µF 10 µF 75 Ω10 µF 75 Ω 75 Ω CE + PCLP BVIN GVIN RVIN HSYNC 100 µF + 1 RVIN 2 VR2 3 GVIN 4 CE 5 BVIN 6 VR1 7 VREF 8 PCLP 9 AVDD 10 AVSS 11 RADIN 12 DSEL 13 GADIN 14 VESD 15 BADIN 16 VRBM 17 VRB 18 VREFB 19 RVCLP 20 GVCLP 21 BVCLP 22 AVSS 23 AVDD 24 CS 25 CK 26 DATA 27 DVSS 28 DVDD 29 BDB7 (MSB) 30 BDB6 VRT 12 kΩ 0.1 µF 1.6 kΩ (LSB) RDA0 90 RDA1 89 RDA2 88 RDA3 87 RDA4 86 RDA5 85 RDA6 84 (MSB) RDA7 83 DVDD 82 DVSS 81 AVSS 80 AVDD 79 (LSB) RDB0 78 RDB1 77 RDB2 76 RDB3 75 RDB4 74 RDB5 73 RDB6 72 (MSB) RDB7 71 DVDD 70 DVSS 69 (LSB) GDA0 68 GDA1 67 GDA2 66 GDA3 65 GDA4 64 GDA5 63 GDA6 62 (MSB) GDA7 61 (MB40C348) PVSS 120 PVDD 119 HSYNC 118 HHOLD 117 PVDD 116 LPF 115 PVSS 114 RREF 113 VREFT 112 VRT 111 VRTM 110 VR3 109 AVSS 108 AVDD 107 DVDD 106 DVSS 105 OF 104 DSYNC 103 DSYNCB 102 COUT 101 EXPCLK 100 EXPCLKB 99 EXCLK 98 ADCLKA 97 ADCLKB 96 CLK 95 CLKB 94 DVDD 93 DVSS 92 AVSS 91 16 + 31 BDB5 32 BDB4 33 BDB3 34 BDB2 35 BDB1 36 BDB0 (LSB) 37 DVSS 38 DVDD 39 BDA7 (MSB) 40 BDA6 41 BDA5 42 BDA4 43 BDA3 44 BDA2 45 BDA1 46 BDA0 (LSB) 47 AVDD 48 AVSS 49 DVSS 50 DVDD 51 GDB7 (MSB) 52 GDB6 53 GDB5 54 GDB4 55 GDB3 56 GDB2 57 GDB1 58 GDB0 (LSB) 59 DVDD 60 DVSS PVDD (+3.3 V) PVSS (0 V) HHOLD 0.001 µF + 100 µF DVDD (+3.3 V) DVSS (0 V) Note : Unexpresstion capacitance values are all 1 µF EXPCLK EXPCLKB EXCLK MB40C348 ■ TYPICAL APPLICATION + MB40C348 ■ USAGE PRECAUTIONS Be sure to ground the pins of AVDD, DVDD, PVDD, VESD, VRTM, VRBM, VR1,VR2, VR3, and VREF via high-frequency capacitor. Place the high-frequency capacitor as close as possible to the pin. ■ ORDERING INFORMATION Part number MB40C348PFV Package Remark 120-pin plastic LQFP (FPT-120P-M21) 17 MB40C348 ■ PACKAGE DIMENSION 120-pin plastic LQFP (FPT-120P-M21) 18.00±0.20(.709±.008)SQ 16.00±0.10(.630±.004)SQ 90 61 91 60 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 INDEX 120 LEAD No. 1 30 0.50(.020) C 18 0~8° "A" 31 1998 FUJITSU LIMITED F120033S-2C-2 0.22±0.05 (.009±.002) +0.05 0.08(.003) M 0.145 –0.03 +.002 .006 –.001 0.45/0.75 (.018/.030) 0.10±0.05 (.004±.002) (Stand off) 0.25(.010) Dimensions in mm (inches) . MB40C348 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0009 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.