FUJITSU SEMICONDUCTOR DATA SHEET DS05-50102-2E MCP (Multi-Chip Package) FLASH MEMORY CMOS 8M (× 8/× 16) FLASH MEMORY & 8M (× 8/× 16) FLASH MEMORY MB84VB2000-10/MB84VB2001-10 ■ FEATURES • Contain 2 chips of MBM29LV800A, and each chip have separate CE. • Power supply voltage of 2.7 to 3.6 V • High performance 100 ns maximum access time • Operating Temperature –40 to +85°C • Minimum 100,000 write/erase cycles • Sector erase architecture One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes × 2 chips Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture MB84VB2000: Top sector MB84VB2001: Bottom sector • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read data in another sector within the same device • Please refer to "MBM29LV800TA/BA" data sheet in detailed function Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. MB84VB2000-10/MB84VB2001-10 ■ BLOCK DIAGRAM VCC VSS RY/BY A0 to A18 A-1 RESET CE1 BYTE 8 M bit Flash Memory DQ0 to DQ15 VCC CE2 WE OE 2 VSS 8 M bit Flash Memory MB84VB2000-10/MB84VB2001-10 ■ CONNECTION DIAGRAM (Top View) A B C D E F G H 6 N.C. VSS DQ1 A1 A2 A4 N.C. A9 5 A10 DQ5 DQ2 A0 A3 A7 RY/BY A14 4 OE DQ7 DQ4 DQ0 A6 A18 RESET A15 3 A11 A8 A5 DQ8 DQ3 DQ12 A12 BYTE 2 A13 A17 CE2 CE1 DQ10 VCC DQ6 DQ15/A-1 1 WE N.C. A16 VSS DQ9 DQ11 DQ13 DQ14 Table 1 MB84VB2000/MB84VB2001 Pin Configuration Pin Function Input/ Output A-1, A0 to A18 Address Inputs (Common) I DQ0 to DQ15 Data Inputs/Outputs (Common) I/O CE1 Chip Enable 1 I CE2 Chip Enable 2 I OE Output Enable (Common) I WE Write Enable (Common) I RY/BY Ready/Busy Outputs (Common) O RESET Hardware Reset Pin/Sector Protection Unlock (Common) I BYTE Selects 8-bit or 16-bit mode (Common) I N.C. No Internal Connection — VSS Device Ground (Common) Power VCC Device Power Supply (Common) Power 3 MB84VB2000-10/MB84VB2001-10 ■ PRODUCT LINE UP Part No. Ordering Part No. MB84VB2000/MB84VB2001 VCC = 3.0 V +0.6 V –0.3 V -10 Max. Address Access Time (ns) 100 Max. CE Access Time (ns) 100 Max. OE Access Time (ns) 40 ■ LOGIC SYMBOL Table 2 MB84VB2000/MB84VB2001 User Bus Operations (BYTE = VIH) Operation (5) CE1 CE2 OE WE A0 A1 A6 A9 H L L H L H L L L VID Code H H L L H L H H L L VID Code H H L L H L H A0 A1 A6 A9 DOUT H Full Standby H H X X X X X X HIGH-Z H Output Disable X X H H X X X X HIGH-Z H H L H L A0 A1 A6 A9 DIN H L H H L L H L VID X H L H H L L H Temporary Sector Unprotection X Reset (Hardware)/Standby X Auto-Select Manufacture’s Code (1) Auto-Select Device Code (1) Read (3) Write (Program/Erase) Enable Sector Protection (2), (4) VID Verify Sector Protection (2), (4) 4 DQ0 to DQ15 RESET L H L H L VID Code H X X X X X X X X VID X X X X X X X HIGH-Z L MB84VB2000-10/MB84VB2001-10 Table 3 MB84VB2000/MB84VB2001 User Bus Operations (BYTE = VIL) OE WE DQ15/ A-1 A0 A1 A6 A9 DQ0 to DQ7 RESET L H L L L L VID Code H L H L H L L VID Code H L H A-1 A0 A1 A6 A9 DOUT H H X X X X X X X HIGH-Z H X X H H X X X X X HIGH-Z H H L H L A-1 A0 A1 A6 A9 DIN H L H Enable Sector Protection (2), (4) H L L L H L VID X H L H Verify Sector Protection (2), (4) H L L H Temporary Sector Unprotection X Reset (Hardware)/Standby X Operation (5) CE1 CE2 H L L H H L L H H L L H Full Standby H Output Disable Auto-Select Manufacture’s Code (1) Auto-Select Device Code (1) Read (3) Write (Program/Erase) VID Legend: L = VIL, H = VIH, X = VIL or VIH, L H L L H L VID Code H X X X X X X X X X VID X X X X X X X X HIGH-Z L = Pulse input. See DC Characteristics for voltage levels. Notes: 1.Manufacturer and device codes may also be accessed via a command register write sequence. See Table 7. 2.Refer to the section on Sector Protection. 3.WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 4.VCC = 3.3 V ±10% 5.Do not apply CE1 = CE2 = VIL at a time. 5 MB84VB2000-10/MB84VB2001-10 ■ FLEXIBLE SECTOR-ERASE ARCHITECTURE • One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes × 2. • Individual-sector, multiple-sector, or bulk-erase capability. (×8) (×16) FFFFFH 7FFFFH 16K byte/8K word (×16) FFFFFH 7FFFFH F0000H 78000H E0000H 70000H D0000H 68000H C0000H 60000H B0000H 58000H A0000H 50000H 90000H 48000H 80000H 40000H 70000H 38000H 60000H 30000H 50000H 28000H 40000H 20000H 30000H 18000H 20000H 10000H 10000H 08000H 08000H 04000H 06000H 03000H 04000H 02000H 00000H 00000H 64K byte/32K word FC000H 7E000H 8K byte/4K word 64K byte/32K word FA000H 7D000H 8K byte/4K word 64K byte/32K word F8000H 7C000H 32K byte/16K word 64K byte/32K word F0000H 78000H 64K byte/32K word 64K byte/32K word E0000H 70000H 64K byte/32K word 64K byte/32K word D0000H 68000H 64K byte/32K word 64K byte/32K word C0000H 60000H 64K byte/32K word 64K byte/32K word B0000H 58000H 64K byte/32K word 64K byte/32K word A0000H 50000H 64K byte/32K word 64K byte/32K word 90000H 48000H 64K byte/32K word 64K byte/32K word 80000H 40000H 64K byte/32K word 64K byte/32K word 70000H 38000H 64K byte/32K word 64K byte/32K word 60000H 30000H 64K byte/32K word 64K byte/32K word 50000H 28000H 64K byte/32K word 64K byte/32K word 40000H 20000H 64K byte/32K word 32K byte/16K word 30000H 18000H 64K byte/32K word 8K byte/4K word 20000H 10000H 64K byte/32K word 8K byte/4K word 10000H 08000H 64K byte/32K word 16K byte/8K word 00000H MB84VB2000 Sector Architecture 6 (×8) 00000H MB84VB2001 Sector Architecture MB84VB2000-10/MB84VB2001-10 ■ FUNCTIONAL DESCRIPTION Table 4 Sector Address Tables (MB84VB2000) Sector Address A18 A17 A16 A15 A14 A13 A12 Address Range (×8) Address Range (×16) SA0 0 0 0 0 X X X 00000H to 0FFFFH 00000H to 07FFFH SA1 0 0 0 1 X X X 10000H to 1FFFFH 08000H to 0FFFFH SA2 0 0 1 0 X X X 20000H to 2FFFFH 10000H to 17FFFH SA3 0 0 1 1 X X X 30000H to 3FFFFH 18000H to 1FFFFH SA4 0 1 0 0 X X X 40000H to 4FFFFH 20000H to 27FFFH SA5 0 1 0 1 X X X 50000H to 5FFFFH 28000H to 2FFFFH SA6 0 1 1 0 X X X 60000H to 6FFFFH 30000H to 37FFFH SA7 0 1 1 1 X X X 70000H to 7FFFFH 38000H to 3FFFFH SA8 1 0 0 0 X X X 80000H to 8FFFFH 40000H to 47FFFH SA9 1 0 0 1 X X X 90000H to 9FFFFH 48000H to 4FFFFH SA10 1 0 1 0 X X X A0000H to AFFFFH 50000H to 57FFFH SA11 1 0 1 1 X X X B0000H to BFFFFH 58000H to 5FFFFH SA12 1 1 0 0 X X X C0000H to CFFFFH 60000H to 67FFFH SA13 1 1 0 1 X X X D0000H to DFFFFH 68000H to 6FFFFH SA14 1 1 1 0 X X X E0000H to EFFFFH 70000H to 77FFFH SA15 1 1 1 1 0 X X F0000H to F7FFFH 78000H to 7BFFFH SA16 1 1 1 1 1 0 0 F8000H to F9FFFH 7C000H to 7CFFFH SA17 1 1 1 1 1 0 1 FA000H to FBFFFH 7D000H to 7DFFFH SA18 1 1 1 1 1 1 X FC000H to FFFFFH 7E000H to 7FFFFH 7 MB84VB2000-10/MB84VB2001-10 Table 5 Sector Address 8 Sector Address Tables (MB84VB2001) A18 A17 A16 A15 A14 A13 A12 Address Range (×8) Address Range (×16) SA0 0 0 0 0 0 0 X 00000H to 03FFFH 00000H to 01FFFH SA1 0 0 0 0 0 1 0 04000H to 05FFFH 02000H to 02FFFH SA2 0 0 0 0 0 1 1 06000H to 07FFFH 03000H to 03FFFH SA3 0 0 0 0 1 X X 08000H to 0FFFFH 04000H to 07FFFH SA4 0 0 0 1 X X X 10000H to 1FFFFH 08000H to 0FFFFH SA5 0 0 1 0 X X X 20000H to 2FFFFH 10000H to 17FFFH SA6 0 0 1 1 X X X 30000H to 3FFFFH 18000H to 1FFFFH SA7 0 1 0 0 X X X 40000H to 4FFFFH 20000H to 27FFFH SA8 0 1 0 1 X X X 50000H to 5FFFFH 28000H to 2FFFFH SA9 0 1 1 0 X X X 60000H to 6FFFFH 30000H to 37FFFH SA10 0 1 1 1 X X X 70000H to 7FFFFH 38000H to 3FFFFH SA11 1 0 0 0 X X X 80000H to 8FFFFH 40000H to 47FFFH SA12 1 0 0 1 X X X 90000H to 9FFFFH 48000H to 4FFFFH SA13 1 0 1 0 X X X A0000H to AFFFFH 50000H to 57FFFH SA14 1 0 1 1 X X X B0000H to BFFFFH 58000H to 5FFFFH SA15 1 1 0 0 X X X C0000H to CFFFFH 60000H to 67FFFH SA16 1 1 0 1 X X X D0000H to DFFFFH 68000H to 6FFFFH SA17 1 1 1 0 X X X E0000H to EFFFFH 70000H to 77FFFH SA18 1 1 1 1 X X X F0000H to FFFFFH 78000H to 7FFFFH MB84VB2000-10/MB84VB2001-10 Table 6.1 Flash Memory Autoselect Codes Type Manufacture’s Code A6 A1 A0 A-1*1 Code (HEX) VIL VIL VIL VIL 04H VIL DAH VIL VIL VIH X 22DAH VIL 5BH X 225BH Byte MB84VB2000 Word Device Code Byte MB84VB2001 VIL VIL VIH Word *1: A-1 is for Byte mode. Table 6.2 Expanded Autoselect Code Table Type Code Manufacture’s Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 04H A-1/0 (B) DAH (W) 22DAH (B) 5BH (W) 225BH A-1 0 0 0 0 0 0 0 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 0 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 MB84VB2000 Device Code 0 A-1 0 1 0 0 0 1 0 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z MB84VB2001 0 0 1 0 0 0 1 0 (B): Byte mode (W): Word mode 9 MB84VB2000-10/MB84VB2001-10 Table 7 Command Sequence Flash Memory Command Definitions Fourth Bus Bus First Bus Second Bus Third Bus Fifth Bus Sixth Bus Write Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Cycles Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Read/Reset 1 Read/Reset 3 Autoselect 3 Program 4 Chip Erase 6 Sector Erase 6 XXXH F0H 555H AAAH 555H AAAH 555H AAAH 555H AAAH 555H AAAH AAH AAH AAH AAH AAH — 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H — 55H 55H 55H 55H 55H — 555H AAAH 555H AAAH 555H AAAH 555H AAAH 555H AAAH — — — — — — — F0H RA RD — — — — 90H — — — — — — A0H PA PD — — — — 80H 80H 555H AAAH 555H AAAH AAH AAH 2AAH 555H 2AAH 555H 55H 55H 555H AAAH SA Sector Erase Suspend Erase can be suspended during sector erase with Addr. (“H” or “L”). Data (B0H) Sector Erase Resume Erase can be resumed after suspend with Addr. (“H” or “L”). Data (30H) Set to Fast Mode 3 555H Fast Program (Note) 2 Reset from Fast Mode (Note) 2 Extended Sector Protect 4 AAAH XXXH XXXH XXXH XXXH XXXH AAH A0H 90H 60H 2AAH 555H PA XXXH XXXH SPA 55H 555H AAAH 10H 30H 20H — — — — — — PD — — — — — — — — F0H — — — — — — — — 60H SPA 40H SPA SD — — — — Address bits A11 to A17 = X = “H” or “L” for all address commands except or Program Address (PA) and Sector Address (SA). Bus operations are defined in Tables 2 and 3. The system should generate the following address patterns: Word Mode: 555H or 2AAH to addresses A0 to A10 Byte Mode: AAAH or 555H to addresses A-1 and A0 to A10 Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. RA =Address of the memory location to be read PA =Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA =Address of the sector to be erased. The combination of A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. RD =Data read from location RA during read operation. PD =Data to be programmed at location PA. Data is latched on the falling edge of write pulse. SPA:Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0). SD:Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected sector addresses. 10 MB84VB2000-10/MB84VB2001-10 ■ ABSOLUTE MAXIMUM RATINGS Storage Temperature .................................................................................................. –55°C to +125°C Ambient Temperature with Power Applied .................................................................. –25°C to +85°C Voltage with Respect to Ground All pins (Note) .......................................................... –0.3 V to VCC + 0.5 V VCCf/VCCs Supply (Note) .............................................................................................. –0.3 V to +4.6 V Note: Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCCf + 0.5 V or VCCs + 0.5 V. During voltage transitions, outputs may positive overshoot to VCC + 2.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING RANGES Commercial Devices Ambient Temperature (TA) .........................................................................–40°C to +85°C VCC Supply Voltages ..................................................................................+2.7 V to +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 11 MB84VB2000-10/MB84VB2001-10 ■ DC CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min. Max. Unit ILI Input Leakage Current VIN = VSS to VCC, VCC = VCC Max. –1.0 +1.0 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max. –1.0 +1.0 µA ILIT A9, OE, RESET Inputs Leakage Current VCC = VCC Max. A9, OE, RESET = 12.5 V — 70 µA CE = VIL, OE = VIH, f = 10 MHz ICC1 Byte 22 — Word mA 25 VCC Active Current (Note 1, 5) CE = VIL, OE = VIH, f = 5 MHz Byte 12 — Word mA 15 ICC2 VCC Active Current (Note 2, 5) CE = VIL, OE = VIH — 35 mA ICC3 VCC Current (Standby) (Note 5) VCC = VCC Max., CE = VCC ± 0.3 V, RESET = VCC ± 0.3 V — 5 µA ICC4 VCC Current (Standby, Reset) (Note 5) VCC = VCC Max., RESET = VSS ± 0.3 V — 5 µA ICC5 VCC Current (Automatic Sleep Mode) (Note 3, 5) VCC = VCC Max., CE = VSS ± 0.3 V, RESET = VCC ± 0.3 V VIN = VCC ± 0.3 V or VSS ± 0.3 V — 5 µA VIL Input Low Level — –0.5 0.6 V VIH Input High Level — 2.0 VCC + 0.3 V VID Voltage for Autoselect and Sector Protection (A9, OE, RESET) (Note 4) — 11.5 12.5 V VOL Output Low Voltage Level IOL = 4.0 mA, VCC = VCC Min. — 0.45 V IOH = –2.0 mA, VCC = VCC Min. 2.4 — V IOH = –100 µA, VCC = VCC Min. VCC – 0.4 — V 2.3 2.5 V VOH1 Output High Voltage Level VOH2 VLKO Low VCC Lock-Out Voltage — Notes: 1.The ICC current listed includes both the DC operating current and the frequency dependent component (at 10 MHz). 2.ICC active while Embedded Algorithm (program or erase) is in progress. 3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. (VID – VCC) do not exceed 9 V. 5. Total power consumption is (condition of Flash 1) + (condition of Flash 2). 12 MB84VB2000-10/MB84VB2001-10 ■ AC CHARACTERISTICS • CE Timing Parameter Symbols JEDEC Standard — tCCR Description CE Recover Time Test Setup — -10 Unit 0 ns Min. • Read Only Operations Characteristics Parameter Symbols Description JEDEC Standard tAVAV tRC Read Cycle Time tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay tGLQV tOE Output Enable to Output Delay tEHQZ tDF tGHQZ -10 (Note) Test Setup Unit Min. Max. 100 — ns CE = VIL OE = VIL — 100 ns OE = VIL — 100 ns — — 40 ns Chip Enable to Output High-Z — — 30 ns tDF Output Enable to Output High-Z — — 30 ns tAXQX tOH Output Hold Time from Addresses, CE or OE, Whichever Occurs First — 0 — ns — tREADY RESET Pin Low to Read Mode — — 20 µs — tELFL tELFH CE or BYTE Switching Low or High — — 5 ns — Note: Test Conditions–Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Input: 1.5 V Output: 1.5 V 13 MB84VB2000-10/MB84VB2001-10 • Erase/Program Operations Parameter Symbols Description JEDEC Standard tAVAV tWC Write Cycle Time tAVWL tAS tAVEL Unit Min. Typ. Max. 100 — — ns Address Setup Time (WE to Addr.) 0 — — ns tAS Address Setup Time (CE to Addr.) 0 — — ns tWLAX tAH Address Hold Time (WE to Addr.) 50 — — ns tELAX tAH Address Hold Time (CE to Addr.) 50 — — ns tDVWH tDS Data Setup Time 50 — — ns tWHDX tDH Data Hold Time 0 — — ns — tOES Output Enable Setup Time 0 — — ns — tOEH Output Enable Hold Time Read 0 — — ns Toggle and Data Polling 10 — — ns tGHEL tGHEL Read Recover Time Before Write (OE to CE) 0 — — ns tGHWL tGHWL Read Recover Time Before Write (OE to WE) 0 — — ns tWLEL tWS WE Setup Time (CE to WE) 0 — — ns tELWL tCS CE Setup Time (WE to CE) 0 — — ns tEHWH tWH WE Hold Time (CE to WE) 0 — — ns tWHEH tCH CE Hold Time (WE to CE) 0 — — ns tWLWH tWP Write Pulse Width 50 — — ns tELEH tCP CE Pulse Width 50 — — ns tWHWL tWPH Write Pulse Width High 30 — — ns tEHEL tCPH CE Pulse Width High 30 — — ns tWHWH1 tWHWH1 Byte Programming Operation — 8 — µs tWHWH2 tWHWH2 Sector Erase Operation (Note 1) — 1 15 sec — tVCS VCC Setup Time 50 — — µs — tVIDR Rise Time to VID (Note 2) 500 — — ns — tVLHT Voltage Transition Time (Note 2) 4 — — µs — tWPP Write Pulse Width (Note 2) 100 — — µs — tOESP OE Setup Time to WE Active (Note 2) 4 — — µs — tCSP CE Setup Time to WE Active (Note 2) 4 — — µs — tRB Recover Time from RY/BY 0 — — ns — tRP RESET Pulse Width 500 — — ns — tRH RESET Hold Time Before Read 200 — — ns — tEOE Delay Time from Embedded Output Enable — — 100 ns — tBUSY Program/Erase Valid to RY/BY Delay — — 90 ns — tFLQZ BYTE Switching Low to Output High-Z — — 30 ns — tFLQV BYTE Switching High to Output Active 30 — — ns Notes: 1. This does not include the preprogramming time. 2. This timing is for Sector Protection operation. 14 -10 MB84VB2000-10/MB84VB2001-10 ■ SWITCHING WAVEFORMS CE1 tCCR tCCR CE2 Figure 1 Timing Diagram for Alternating Flash to Flash 15 MB84VB2000-10/MB84VB2001-10 tRC Addresses Addresses Stable tACC CE tOE tDF OE tOEH WE tCE HIGH-Z DQ HIGH-Z Output Valid tRC Addresses Stable Addresses tACC tRH RESET tOH DQ HIGH-Z Figure 2 16 Output Valid AC Waveforms for Read Operations MB84VB2000-10/MB84VB2001-10 Data Polling 3rd Bus Cycle Addresses 555H PA tWC tAS PA tRC tAH CE CE tCH tCS tCE OE OE tGHWL tWP tWPH tOE tWHWH1 WE WE tOH tDS tDH A0H Data PD DQ77 DQ DOUT DOUT Notes: 1.PA is address of the memory location to be programmed. 2.PD is data to be programmed at byte address. 3.DQ7 is the output of the complement of the data written to the device. 4.DOUT is the output of the data written to the device. 5.Figure indicates last two bus cycles out of four bus cycle sequence. 6.These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) Figure 3 Alternate WE Controlled Program Operation Timings 17 MB84VB2000-10/MB84VB2001-10 DataPolling Polling Data 3rd Bus Cycle Addresses PA 555H tWC tAS PA tAH WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS tDH Data A0H PD DQ77 DOUT Notes: 1.PA is address of the memory location to be programmed. 2.PD is data to be programmed at byte address. 3.DQ7 is the output of the complement of the data written to the device. 4.DOUT is the output of the data written to the device. 5.Figure indicates last two bus cycles out of four bus cycle sequence. 6.These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) Figure 4 18 Alternate CE Controlled Program Operation Timings MB84VB2000-10/MB84VB2001-10 Addresses 2AAH 555H tWC tAS 555H 555H 2AAH SA* tAH CE CE tCS tCH OE OE tGHWL tWP tWPH WE WE tDS AAH Data tDH 55H 80H AAH 55H 10H/ 30H tVCS VCC * : SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAH (Byte) for Chip Erase. Note: These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.) Figure 5 AC Waveforms Chip/Sector Erase Operations 19 MB84VB2000-10/MB84VB2001-10 CE CE tCH tOE tDF OE OE tOEH WE WE tCE * DQ7 Data High-Z DQ7 = Valid Data DQ DQ7 7 tWHWH1 or 2 DQ0 to DQ6 Data DQ0 to DQ6 = Output Flag High-Z DQ0 to DQ6 Valid Data tEOE * : DQ7 = Valid Data (The device has completed the Embedded operation.) Figure 6 AC Waveforms for Data Polling during Embedded Algorithm Operations CE CE tOEH WE WE tOES OE OE * DQ6 Data DQ6 = Toggle DQ6 = Stop Toggling DQ6 = Toggle Valid tOE * : DQ6 stops toggling.(The device has completed the Embedded operation.) Figure 7 20 AC Waveforms for Toggle Bit during Embedded Algorithm Operations MB84VB2000-10/MB84VB2001-10 CE CE The rising rising edge edge of of the the last last WE WE signal signal The WE WE Entire programming or erase operations RY/BY tBUSY Figure 8 RY/BY Timing Diagram during Write/Erase Operations WE WE RESET RESET tRP tRB RY/BY tREADY Figure 9 RESET, RY/BY Timing Diagram 21 MB84VB2000-10/MB84VB2001-10 CE BYTE Data Output (DQ0 to DQ7) DQ0 to DQ14 tELFH DQ15/A-1 Data Output (DQ0 to DQ14) tFHQV DQ15 A-1 Figure 10 Timing Diagram for Word Mode Configuration CE BYTE DQ0 to DQ14 tELFL DQ15/A-1 Data Output (DQ0 to DQ7) Data Output (DQ0 to DQ14) DQ15 A-1 tFLQZ Figure 11 Timing Diagram for Byte Mode Configuration The falling edge of the last WE signal CE or WE Input Valid BYTE tSET (tAS) Figure 12 22 tHOLD (tAH) BYTE Timing Diagram for Write Operations MB84VB2000-10/MB84VB2001-10 A18, A17, A16 A15, A14 A13, A12 SAX SAY A0 A1 A6 12 V 3V A9 tVLHT 12 V 3V OE OE tVLHT tVLHT tVLHT tWPP WE WE tOESP tCSP CE CE Data 01H tVCS tOE VCC SAX : Sector Address for initial sector SAY : Sector Address for next sector Note: A-1 is VIL on byte mode. Figure 13 AC Waveforms for Sector Protection Timing Diagram 23 MB84VB2000-10/MB84VB2001-10 FAST MODE ALGORITHM Start RESET = VID Wait to 4 µs Device is Operating in Temporary Sector Unprotection Mode No Extended Sector Protection Entry? Yes To Setup Sector Protection Write XXXH/60H PLSCNT = 1 To Sector Protection Write SPA/60H (A0 = VIL, A1 = VIH, A6 = VIL) Time Out 150 µs Increment PLSCNT To Verify Sector Protection Write SPA/40H (A0 = VIL, A1 = VIH, A6 = VIL) Setup Next Sector Address Read from Sector Address (A0 = VIL, A1 = VIH, A6 = VIL) No No PLSCNT = 25? Yes Data = 01H? Yes Remove VID from RESET Write Reset Command Device Failed Protection Other Sector ? No Yes Remove VID from RESET Write Reset Command Sector Protection Completed Figure 14 24 Extended Sector Protection Algorithm MB84VB2000-10/MB84VB2001-10 VCC tVIDR tVLHT tVCS 12 V 3V 3V RESET CE CE WE WE tVLHT tVLHT Program or Erase Command Sequence RY/BY RY/BY Figure 15 Enter Embedded Erasing WE WE Erase Suspend Erase Temporary Sector Unprotection Timing Diagram Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Toggle Toggle DQ2 and DQ6 DQ2 and DQ6 with OE OE with Note: DQ2 is read from the erase-suspended sector. Figure 16 DQ2 vs DQ6 25 MB84VB2000-10/MB84VB2001-10 ■ ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Unit Comments Min. Typ. Max. Sector Erase Time — 1 15 sec Word Programming Time — 16 5,200 µs Byte Programming Time — 8 3,600 µs Chip Programming Time (1M Byte) — 8.4 50 sec 100,000 — — cycles Erase/Program Cycle Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead ■ PIN CAPACITANCE Parameter Symbol Parameter Description Test Setup Typ. Max. Unit CIN Input Capacitance VIN = 0 TBD TBD pF COUT Output Capacitance VOUT = 0 TBD TBD pF CIN2 Control Pin Capacitance VIN = 0 TBD TBD pF Note: Test conditions TA = 25°C, f = 1.0 MHz ■ HANDLING OF PACKAGE Please hadle this package carefully since the sides of package are right angle. 26 MB84VB2000-10/MB84VB2001-10 ■ PACKAGE 48-pin plastic FBGA (BGA-48P-M06) ■ PACKAGE DIMENSIONS 48-pin plastic BGA (BGA-48P-M06) Note: The actual shape of corners may differ from the dimension. 11.00±0.15(.433±.006) 1.40±0.20 (.055±.008) 0.30±0.10 (.012±.004) 10.00±0.15 (.394±.006) 7.00±0.15(.276±.006) Ø0.40±0.10 (Ø.016±.004) 5.00±0.15 (.197±.006) 0.15(.006) 1st PIN INDEX 1.00±0.15 (.039±.006) INDEX Dimension in mm (inches). C 1998 FUJITSU LIMITED MCM-M001-2-3 27 MB84VB2000-10/MB84VB2001-10 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9804 FUJITSU LIMITED Printed in Japan 28 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.