FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-13106-2E
Linear IC Converter
CMOS
A/D Converter
(With 24-Channel Input at 10-bit Resolution)
MB88111
■ DESCRIPTION
The MB88111 is an analog-to-digital converter that converts its analog input to a 10-bit digital value and outputs it
as serial data.
The MB88111 employs a successive approximation method for A/D conversion. It has 24 input channels to be A/
D converted selectively by setting in an internal register.
Since the MB88111 can input and output 16-bit serial data in synchronization with the clock, it can be easily
connected to the serial I/O port in a 16-bit microcontroller.
■ FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
24-channel analog input
RC-type successive approximation system with a sample-and-hole circuit
10-bit resolution
Conversion speed within 50 µs (at a system clock rate of 1 MHz)
Digitally converted data output from the MSB
Digitally converted data output as 16-bit serial data
Clock-synchronous serial transfer system
Internal extended serial interface
Capable of triggering A/D conversion through an external pin
Capable of input through an 8-channel port
Serial data output format selectable using an external pin
10-bit monotonicity
No missing code
Power supply voltage ranging from 3.5 to 5.5 V
(Continued)
■ PACKAGES
44-pin, Plastic QFP
48 pin, Plastic SH-DIP
(FPT-44P-M11)
(DIP-48P-M01)
MB88111
(Continued)
• Operating temperature ranging from –40 to +50°C
• CMOS process
• Package options of 44-pin QFP and 48-pin SH-DIP
■ PIN ASSIGNMENT
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
(Top view)
33
32
31
30
29
28
27
26
25
24
23
AN7
34
22
AN19
AN6
35
21
AN20
AN5
36
20
AN21
AN4
37
19
AN22
AN3
38
18
AN23
AN2
39
17
AGND
AN1
40
16
AVRL
AN0
41
15
V SS
AVRH
42
14
TESTI
AV CC
43
13
N.C.
V CC
44
12
MOD
8
9
10
11
CS1
SIN
7
CS2X
CCLK
6
ATGX
SCK
5
IRQX
4
ENDC
3
SOT
2
ESIN
1
RSTX
INDEX
(FPT-44P-M11)
(Continued)
2
MB88111
(Continued)
(Top view)
AN1
1
AN0
2
AVRH
48
AN2
47
AN3
3
46
AN4
AV CC
4
45
AN5
V CC
5
44
AN6
N.C.
6
43
AN7
RSTX
7
42
N.C.
SCK
8
41
AN8
CCLK
9
40
AN9
SIN
10
39
AN10
ESIN
11
38
AN11
SOT
12
37
AN12
ENDC
13
36
AN13
IRQX
14
35
AN14
ATGX
15
34
AN15
CS2X
16
33
AN16
CS1
17
32
AN17
N.C.
18
31
AN18
MOD
19
30
N.C.
N.C.
20
29
AN19
TESTI
21
28
AN20
V SS
22
27
AN21
AVRL
23
26
AN22
AGND
24
25
AN23
INDEX
(DIP-48P-M01)
3
MB88111
■ PIN DESCRIPTION
Pin no.
QFP
41 to 26
DIP
Symbol
2 to 1, AN0 to AN15
48 to 43,
41 to 34
I/O
Circuit type
Descriptions
I
F
Analog input pins. The pin to be subject to conversion
is selected by the command input through the SIN pin.
Also, a series of pins from AN16 to AN23 can be used
as a port input.
25 to 18 33 to 31, AN16 to
29 to 25 AN23
G
12
19
MOD
I
A
Pin for selecting a serial data output mode:
“L”: Mode A for output from the SOT pin in
synchronization with the fall of the SCK signal.
“H”: Mode B for output from the SOT pin in
synchronization with the rise of the SCK signal.
11
10
17
16
CS1
CS2X
I
A
Input pins for selecting an extended serial interface
mode.
Setting the CS1 level to “H” and the CS2X level to “L”
enables A/D converted data transfer. Setting the CS1
level to “L” or the CS2X level to “H” clears the register
command without affecting A/D conversion. Serial
data input to the external extended serial input pin
ESIN is output to the SOT pin as it is. (See Section 7
“Extended Serial Interface” in “■ OPERATION.”)
4
10
SIN
I
B
Serial data input pin
This pin is a hysteresis input with a filter.
6
12
SOT
O
H
Serial data output pin
3
9
CCLK
I
B
System clock input pin
This pin is a hysteresis input.
2
8
SCK
I
B
Serial data transfer clock input pin
This pin is a hysteresis input with a filter.
9
15
ATGX
I
C
External trigger input pin. This pin incorporates a pullup resistor. The ATC command initiates A/D conversion
at the rise of the signal at this pin.
The pin is a hysteresis input.
8
14
IRQX
O
H
A/D conversion interrupt signal input pin. The signal
level becomes “L” upon completion of A/D conversion;
it becomes “H” upon reception of data to be converted.
7
13
ENDC
O
H
A/D conversion completion signal output pin. The
signal level becomes “H” upon completion of A/D
conversion; it becomes “L” upon reception of data to be
converted.
5
11
ESIN
I
A
Serial input extension input pin. When the CS1 level is
“L” or the CS2X level is “H,” data input to the ESIN pin
is output to the SOT pin as it is.
1
7
RSTX
I
D
Reset signal input pin. This pin incorporates a pull-up
resistor. Setting the signal level to “L” initializes the
internal circuit of the device.
This pin is a hysteresis input with a filter.
(Continued)
4
MB88111
(Continued)
Pin no.
Symbol
I/O
Circuit type
I
E
Test input pin. This pin incorporates a pull-down
resistor. Maintain the pin at “L” level during normal
use.
VCC
—
—
Digital circuit power supply pin
22
VSS
—
—
Digital circuit ground pin
43
4
AVCC
—
—
Analog circuit power supply pin
17
24
AGND
—
—
Analog circuit ground pin
42
3
AVRH
—
—
Reference (high) voltage input pin
16
23
AVRL
—
—
Reference (low) voltage input pin
13
6, 18,
20, 30,
42
N.C.
—
—
Non-connection pin
QFP
DIP
14
21
TESTI
44
5
15
Descriptions
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• CMOS input
B
• Hysteresis input
• CMOS input
C
• Input with pull-up resistor
• CMOS input
(Continued)
5
MB88111
(Continued)
Type
6
Circuit
Remarks
D
• Input with pull-up resistor
• Hysteresis input
• CMOS input
E
• Input with pull-down resistor
• CMOS input
F
• Analog input
G
• Analog input
• Hysteresis input
• CMOS input
H
• CMOS output
MB88111
■ BLOCK DIAGRAM
AGND
Multiplexer
AV CC
AN0
AVRH
AVRL
10-bit D/A converter
Sample-and-hold
circuit
AN15
Successive
approximation register
Port input
AN16
Comparator
AN23
ENDC
Control circuit
IRQX
SCK
ESIN
SIN
MOD
Interface control circuit
ATGX
Command register
Data register
CS2X
Output
select
circuit
CS1
SOT
RSTX
TESTI
CCLK
V CC
V SS
7
MB88111
■ FUNCTIONAL DESCRIPTION
1. SC (Serial Command) Register (Reset status: 0000H)
The SC register contains an A/D converter command and an input channel identification. Accessing this register
after releasing it from the reset status activates the A/D converter.
Note that this register accepts setting even during A/D conversion.
Note also that input of a command to the register must take an interval of at least 4 CCLKs after input of the
previous command.
MSB
bf
LSB
be
bd
bc
bb
ba
b9
b8
b7
b6
Channel
Command
b5
b4
b3
b2
b1
b0
Don't care
(1) Command bits
A string of command bits selects an A/D converter command such as STOP. Setting a command during execution
of another command cancels the command currently being executed.
bf
be
bd
Command name
Function
0
0
0
STOP
Stops A/D conversion (if it is being executed) and
initializes the A/D converter. This command has the same
effect as RSTX.
0
0
1
STC
Executes A/D conversion of the specified channel once.
(See Section 3 “STC (Standard Conversion) Command.”)
0
1
0
—
Unused (*)
0
1
1
—
Unused (*)
1
0
0
NOP
No-op command. Input of this command during A/D
conversion does not affect operation. If followed by this
command, the ATC command can transfer converted data
while holding the NOP command.
The basic operation of this command is the same as that
of the STC command. The ATC command can leave the
A/D conversion start timing to the external trigger pin
ATGX. (See Section 4 “ATC (Auto Trigger Conversion)
Command.”)
1
0
1
ATC
1
1
0
—
Unused (*)
1
1
1
—
Unused (*)
* : These command settings cause the STOP command to be executed.
8
MB88111
(2) Channel select bits
A string of channel select bits selects the pin to be subject to A/D conversion. This bit string is enabled only for
the STC or ATC command.
bc
bb
ba
b9
b8
Pin to be selected
bc
bb
ba
b9
b8
Pin to be selected
0
0
0
0
0
AN0
0
0
0
0
1
AN1
1
..
.
0
..
.
0
..
.
0
..
.
0
..
.
AN16
..
.
0
0
0
1
0
AN2
1
0
1
1
1
AN23
0
0
0
1
1
AN3
1
1
0
0
0
0
..
.
0
..
.
1
..
.
0
..
.
0
..
.
AN4
..
.
1
1
0
0
1
1
1
0
1
0
0
1
0
1
1
AN11
1
1
0
1
1
0
1
1
0
0
AN12
1
1
1
0
0
0
1
1
0
1
AN13
1
1
1
0
1
0
1
1
1
0
AN14
1
1
1
1
0
0
1
1
1
1
AN15
1
1
1
1
1
Undefined (*1)
Port input AN16 to
AN23 (*2)
*1: These settings of the bit string cause the STOP command to be executed.
*2: This setting is enabled only for the STC command. (See Section 5 “Port Input Command.”)
If this setting is made for the ATC command, the STOP command is executed.
2. Data Output Format
Upon completion of A/D conversion, the ENDC pin level becomes “H” and the IRQX pin level becomes “L.”
Execution of serial transfer at this time outputs data in the format illustrated below. The data output timing can
be selected by the MOD pin between the falling edge (mode A) or rising edge (mode B) of the SCK signal.
When the ENDC pin level is “L,” 0000H is output.
MSB
Bf
LSB
Be
Bd
Bc
Bb
Ba
B9
Converted data
B8
B7
B6
B5
ENDC
B4
B3
B2
B1
B0
A/D converted pin
ENDC (A/D conversion completion flag): This bit is set to “1” upon completion of A/D conversion. It is set to
“0” upon completion of serial transfer.
Note: SCK input upon low-to-high transition of the ENDC pin level should be avoided. Otherwise, data may not
be output correctly.
9
MB88111
3. STC (Standard Conversion) Command
Input of the STC command executes A/D conversion of the specified channel once.
Impletion of A/D conversion, the ENDC signal rises while the IRQX signal falls. Clock input to the SCK pin after
A/D conversion outputs data to the SOT pin. Upon completion of data output, the ENDC signal falls while the
IRQX signal rises. If the next command is STOP or NOP, the A/D conversion is terminated. If the STC command
is input during A/D conversion, the command currently being executed is cancelled and the STC command is
executed.
• Example of STC command execution (1)
STC command input during A/D conversion cancels the current command and executes A/D conversion of the
new specified channel. Output data at this time is 0000H.
16 Cycle
SCK
SIN
AN0
AN1
AN2
STOP
SOT
0000H
Data 0
0000H
Data 2
ENDC
IRQX
AN0 conversion
A/D
AN1 conversion
AN2 conversion
• Example of STC command execution (2)
NOP command input during A/D conversion does not affect operation. Output data at this time is 0000H. If A/
D conversion is completed during NOP command input, the ENDC and IRQX pin levels become “H” and “L”
respectively upon completion of the NOP command input.
16 Cycle
SCK
SIN
AN3
NOP
NOP
AN4
NOP
STOP
SOT
0000H
0000H
Data 3
0000H
0000H
Data 4
ENDC
IRQX
A/D
10
AN3 conversion
AN4 conversion
MB88111
4. ATC (Auto Trigger Conversion) Command
The ATC command is the same as the STC command in basic operation. This command can initiates A/D
conversion using the external trigger pin ATGX. The external trigger signal is sampled by 1 µs clock and filtered
by 1 clock. The external trigger signal input during A/D conversion is ignored. If the next command is the STOP
command, A/D conversion is terminated. If it is the NOP command, the ATC command is executed continuously.
The channel cannot be changed at this time. To change the channel, input the ATC command to that effect.
• Example of ATC command execution (1)
NOP command input during A/D conversion enables the same channel to be A/D converted.
An attempt to set the ATGX signal low during A/D conversion is ignored.
NOP command input during A/D conversion does not affect operation. Output data at this time is 0000H.
16 Cycle
SCK
SIN
AN5
NOP
AN6
NOP
STOP
SOT
0000H
Data 5
Data 5
0000H
Data 6
ENDC
IRQX
ATGX
A/D
AN5 conversion
AN5 conversion
AN6 conversion
• Example of ATC command execution (2)
Setting the ATGX signal low again after A/D conversion restarts A/D conversion.
In data output mode B, however, do not use the ATC command in this way, or data will not be output correctly.
If A/D conversion is completed during NOP command input, the ENDC and IRQX pin levels become “H” and
“L” respectively upon completion of the NOP command input.
16 Cycle
SCK
SIN
AN7
AN8
NOP
STOP
SOT
0000H
Data 7
0000H
Data 8
ENDC
IRQX
ATGX
A/D
AN7 conversion
AN7 conversion
AN7
conversion
AN8 conversion
11
MB88111
5. Port Input Command
The port input command executes I/O evaluation of 8-channel inputs from the AN16 to AN23 pins at a prescribed
threshold in 10 clock cycles and outputs the results as port input data. The processing sequence is activated
each time port input is selected by the STC command. Port input data is output in the following format:
MSB
Bf
LSB
Be
Bd
Bc
Bb
Ba
Evaluation data
B9
B8
B7
B6
“0”
B5
B4
ENDC
B3
B2
B1
B0
“1”
Evaluation data:
The evaluation values of AN23 to AN16 are output to bits Bf to B8.
Evaluation value
“H”: Vin ≥ 0.8 x Vcc
“L”: Vin ≤ 0.2 x Vcc
ENDC (A/D completion flag):
This bit is set to “1” upon completion of A/D conversion. It is set to “0” upon completion of serial transfer.
• Example of STC command execution (3) (Port input command)
16 Cycle
10 Cycle
16 Cycle
SCK
SIN
CH9
STOP
SOT
0000H
Data 9
ENDC
IRQX
AN16
to
AN23
A/D
12
Evaluation
MB88111
6. Serial Output Select Function
The MB88111 can select the serial data output timing between the rising edge or falling edge of the clock signal
according to the setting of the MOD pin.
Mode A (MOD = “L”)
SCK
MSB
SOT
Bf
Be
Bd
Bc
Bb
Ba
B9
B8
B7
B6
B5
B4
B3
B2
B1
LSB
B0
bf
be
bd
bc
bb
ba
b9
b8
b7
b6
b5
b4
b3
b2
b1
LSB
b0
MSB
SIN
Serial data is output at the falling edge of the SCK signal.
Note: A/D converted data is not guaranteed if the MOD pin is switched when the ENDC signal is active. Before
changing the output mode, make the ENDC inactive or set the RSTX pin level to “L” after switching the
MOD pin.
Mode B (MOD = “H”)
SCK
MSB
SOT
Bf
Be
Bd
Bc
Bb
Ba
B9
B8
B7
B6
B5
B4
B3
B2
B1
LSB
B0
MSB
SIN
bf
be
bd
bc
bb
ba
b9
b8
b7
b6
b5
b4
b3
b2
b1
LSB
b0
Serial data is output at the rising edge of the SCK signal.
Note: A/D converted data is not guaranteed if the MOD pin is switched when the ENDC signal is active. Before
changing the output mode, make the ENDC inactive or set the RSTX pin level to “L” after switching the MOD
pin. The first bit is output when the ENDC signal becomes “H.”
7. Extended Serial Interface
The MB88111 can select whether to output A/D converted data or to output data input to the ESIN pin by
controlling the CS1 and CS2X pins.
CS1
CS2X
SOT pin
H
L
A/D converted data
L
L
L
H
H
H
Connection to the ESIN pin
Note: A/D converted data is not guaranteed if the CS1 or CS2X setting is changed during SCK input.
13
MB88111
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AGND = 0 V)
Parameter
Symbol
Ratings
Conditions
VCC
Power supply voltage
AVCC
AVRH
Based on VSS
(Ta = +25°C)
Unit
Min.
Max.
–0.3
+7.0
V
–0.3
+7.0*
V
–0.3
+7.0*
V
Input voltage
VIN
–0.3
VCC + 0.3
V
Output voltage
VOUT
–0.3
VCC + 0.3
V
Power consumption
PD
—
—
150
mW
Storage temperature
Tstg
—
–55
+150
°C
* : VCC ≥ AVCC ≥ AVRH
2. Recommended Operating Conditions
Parameter
Power supply voltage
Operation temperature
* : VCC ≥ AVCC ≥ AVRH
14
Symbol
Values
Unit
Min.
Max.
VCC
AVCC
3.5*
5.5*
V
VCC
AGND
0
0
V
AVRH
AVCC × 0.8
AVCC
V
AVRL
0
AVCC × 0.2
V
Ta
–40
+105
°C
MB88111
3. DC Characteristics
(1) Digital section
Parameter
Pin name
Power supply voltage
Power supply current
Low-level input leakage
current
High-level input leakage
current
Low-level input voltage
High-level input voltage
Hysteresis width
Low-level output voltage
High-level output voltage
(VCC = +3.5 V to +5.5 V, VSS = AGND = 0 V, Ta = –40°C to +105°C)
Value
Symbol
Conditions
Unit
Min.
Typ.
Max.
VCC
—
3.5
5.0
5.5
V
ICC
Operation at
CLK = 1 MHz
(with no load)
—
0.5
1.5
mA
MOD, CCLK
CS1, CS2X
SCK, ESIN
SIN
IIZL1
VIN = VSS
–2
—
2
µA
ATGX
RSTX
IIZL2
VIN = VSS
VCC = 5.0 V
–200
–100
–50
µA
MOD, CCLK
CS1, CS2X
SCK, ESIN
SIN, ATGX
RSTX
IIZL1
VIN = VCC
–2
—
2
µA
MOD, ESIN
CS1, CS2X
VIL
—
VSS − 0.3
—
0.3 VCC
V
SCK, CCLK
SIN, ATGX
RSTX, *
VILS
—
VSS − 0.3
—
0.2 VCC
V
MOD, ESIN
CS1, CS2X
VIH
—
0.7 VCC
—
VCC + 0.3
V
SCK, CCLK
SIN, ATGX
RSTX, *
VIHS
—
0.8 VCC
—
VCC + 0.3
V
SCK, CCLK
SIN, ATGX
RSTX, *
VHYS
—
0.02 VCC
—
0.3 VCC
V
—
—
0.4
V
VCC − 0.4
—
—
V
VCC
SOT
IRQX
ENDC
VOL
IOL = 2.5 mA
VOH
IOH = –400 µA
* : AN16 to AN23 (port input mode)
15
MB88111
(2) Analog section
Parameter
(AVCC, VCC = +3.5 V to +5.5 V (VCC ≥ AVCC), VSS = AGND = 0 V, Ta = –40°C to +105°C)
Value
Pin name
Symbol
Conditions
Unit
Min.
Typ.
Max.
Resolution
—
—
—
10
—
bits
Monotonic increase
—
—
—
10
—
bits
Linearity error
—
—
—
—
±1
LSB
—
—
—
—
±1
LSB
Full-scale transition error
—
—
—
—
±1/2
LSB
Zero-transition error
—
—
—
—
±1/2
LSB
Total error
—
—
—
—
±2
LSB
—
CCLK = 1 MHz
—
—
50
µs
Differential linearity error
AN0 to AN23
Conversion time
—
Input clock frequency
CCLK
—
—
800
1000
1200
KHz
Supply current
AVCC
IA
—
—
3.0
6.0
mA
Reference voltage supply
current
AVRH
IR
—
—
150
300
µA
AVRH
—
—
0.8 AVCC
—
AVCC
V
AVRL
—
—
0
—
0.2 AVCC
V
—
—
AVRL
—
AVRH
V
—
—
–200
—
200
nA
Analog reference voltage
Analog input voltage
Multiplexer OFF-leakage
current
AN0 to AN23
• No missing code is guaranteed.
Notes: • If the output impedance of the external input is too high, the analog voltage sampling time may be
insufficient.
• In the power-on sequence, turn the power supply for the digital system first before turning that for the
analog system on.
Analog input equivalent circuit
Analog input
Comparator
R ON1
R ON2
⋅ RON1 = About 1.5 kΩ
⋅ RON2 =About 1.5 kΩ
⋅ C0 =About 15 pF
Note: The above values are reference values.
16
C0
MB88111
4. AC Characteristics
(AVCC, VCC = +3.5 V to +5.5 V (VCC ≥ AVCC), VSS = AGND = 0 V, Ta = –40°C to +105°C)
Values
Parameter
Symbol
Conditions
Unit
Min.
Max.
CCLK clock cycle time
fCLK
Low-level CCLK clock pulse width
tCKL
High-level CCLK clock pulse width
tCKH
fCLK = 1/fCLK
800
1200
KHz
—
400
—
ns
—
400
—
ns
—
–
10
ns
400
1200
KHz
CCLK clock rise time
tCr
CCLK clock fall time
tCf
SCK clock cycle time
fSCK
Low-level SCK clock pulse width
tSKL
—
400
—
ns
High-level SCK clock pulse width
tSKH
—
400
—
ns
—
–
10
ns
tSCK = 1/fSCK
SCK clock rise time
tSr
SCK clock fall time
tSf
SIN setup time
tSIS
—
50
—
ns
SIN hold time
tSIH
—
250
—
ns
Command interval
tCOM
CCLK = 1 MHz
4
—
µs
ENDC reset time
tENR
See “Load conditions.”
–
1
µs
RSTX pulse width
tRSH
—
100
—
ns
RSTX ↑ → SCK ↓ time
tRSS
—
1
—
µs
SCK ↑ → CS1 ↓ time
SCK ↑ → CS2X ↑ time
tCSS
—
500
—
ns
CS1 ↑ → SCK ↓ time
CS2X ↓ → SCK ↓ time
tCSH
—
500
—
ns
SOT output delay time (mode A)
tSODA
See “Load conditions.”
—
300
ns
SOT output delay time (mode B)
tSODB
See “Load conditions.”
—
300
ns
ENDC ↑ → SOT output (mode B)
tSOHB
See “Load conditions.”
—
200
ns
STC command A/D conversion time
tSTC
CCLK = 1 MHz
—
50
µs
ATC command A/D conversion time
tSATC
CCLK = 1 MHz
—
50
µs
ATGX setup time
tSATS
CCLK = 1 MHz
4
—
µs
ATGX hold time
tSATH
CCLK = 1 MHz
2
—
µs
Port input evaluation time
tPOT
CCLK = 1 MHz
—
10
µs
Port input setup time
tPTS
—
0
—
ns
Port input hold time
tPTH
—
0
—
ns
Extended serial HL propagation delay
tSHL
See “Load conditions.”
—
100
ns
Extended serial LH propagation delay
tSLH
See “Load conditions.”
—
100
ns
Noise filter width
tINF
—
15
—
ns
17
MB88111
AC Test Condition
Measurement point
C L = 50 pF
■ TIMING DIAGRAM
1. Input Clock Timing
t CLK
t CKH
CCLK
t Cf
t CKL
t Cr
t SCK
t SKH
SCK
t Sf
t SKL
Evaluation levels are 80% and 20% of the VCC.
18
t Sr
MB88111
2. Serial Data Input Timing
t RSH
RSTX
t RSS
SCK
t COM
t CSS
t CSH
CS1
(CS2X)
SIN
t SIS
b0
t SIH
bf
be
t ENR
ENDC
Evaluation levels are 80% and 20% of the VCC.
3. Serial Data Output Timing
Mode A
SCK
t SODA
SOT
Bf
Be
Evaluation levels are 80% and 20% of the VCC.
Mode B
SCK
t SODB
SOT
Bf
Be
t SOHB
ENDC
Evaluation levels are 80% and 20% of the VCC.
19
MB88111
4. A/D Conversion and Port Input Evaluation
STC command (normal mode)
SCK
SIN
b0
t STC
ENDC
Evaluation levels are 80% and 20% of the VCC.
ATC command
SCK
SIN
b0
t ATS
t ATH
ATGX
t ATC
ENDC
Evaluation levels are 80% and 20% of the VCC.
20
MB88111
STC command (port input mode)
SCK
SOT
b0
t PTS
AN16
to
AN23
t POT
t PTH
ENDC
Evaluation levels are 80% and 20% of the VCC.
5. Extended Serial Interface
ESIN
t SHL
t SLH
SOT
Evaluation levels are 80% and 20% of the VCC.
6. Noise Filter
t INF
t INF
Evaluation levels are 80% and 20% of the VCC.
21
MB88111
■
DEFINITIONS OF A/D CONVERTER TERMS
• Resolution
Analog transition identifiable by the A/D converter
• Linearity error
Deviation of the straight line drawn between the zero transition point (00 0000 0000 ↔ 00 0000 0001) and
the full-scale transition point (11 1111 1110 ↔ 11 1111 1111) of the device from actual conversion characteristics
• Differential linearity error
Deviation from the ideal input voltage required to shift output code by one LSB
• Total error
Difference between actual and logical values. This error is caused by a zero transition error, full-scale transition
error, linearity error, quantum error, and by noise.
Ideal I/O characteristics
3FF
3FF
3FE
3FE
3FD
004
3FD
1.5 LSB
Digital output
Digital output
Total error
VFST
(Ideal value)
VOT
(Ideal value)
003
002
Actual conversion
characteristics
{1 LSB×(N–1) +0.5 LSB}
004
002
1 LSB
(Ideal value)
001
VNT'
(Measured value)
003
Actual conversion
characteristics
Ideal characteristics
001
0.5 LSB
AVRL
AVRH
AVRL
Analog input
1 LSB (Ideal value) =
AVRH
Analog input
AVRH–AVRL
[v]
1024
V OT (Ideal value) = 0.5 LSB
[v]
V FST (Ideal value) = AVRH - 1.5 LSB
[v]
Total error of
digital output N =
VNT'– {1 LSB × (N–1) +0.5 LSB}
1 LSB
(Continued)
22
MB88111
(Continued)
Zero transition error
Full-scale transition error
Ideal characteristics
004
Actual conversion
characteristics
3FF
Actual conversion
characteristics
002
Actual conversion
characteristics
Digital output
Digital output
003
3FE
VFST'
(Measured value)
3FD
Actual conversion
characteristics
001
3FC
VOT'(Measured value)
AVRL
AVRH
Analog input
Analog input
VOT'–0.5 LSB
Zero transition error =
Full scale transition error =
VFST' – (AVRH–1.5 LSB)
1 LSB
1 LSB
Linearity error
3FF
3FE
Differential linearity error
Ideal characteristics
Actual conversion
characteristics
N+1
{ 1 L S B × ( N – 1 ) + V OT' }
Actual conversion
characteristics
VFST'
(Measured
value)
VNT'
(Measured
value)
Actual conversion
characteristics
004
003
Digital output
Digital output
3FD
N
N-1
V(N + 1)T'
VNT'
(Measured (Measured
value)
value)
002
Ideal characteristics
N-2
001
VOT' (Measured value)
AVRL
AVRH
Analog input
VNT' – {1 LSB' × (N–1)+V OT' }
Linearity error of
digital output N =
1 LSB'
1 LSB' =
VFST' – VOT'
1022
Actual conversion
characteristics
AVRL
AVRH
Analog input
Differential linearity
error of digital output N =
V(N+1)T' –VNT'
1 LSB'
–1
[V]
23
MB88111
■
ORDERING INFORMATION
Part number
24
Package
MB88111PFQ
44-pin, Plastic QFP
(FPT-44P-M11)
MB88111P-SH
48-pin, Plastic SH-DIP
(DIP-48P-M01)
Remarks
MB88111
■
PACKAGE DIMENSIONS
44-pin, Plastic QFP
(FPT-44P-M11)
14.40±0.40 SQ
(.567±.016)
10.00±0.20 SQ
(.394±.008)
33
2.35(.093)MAX
(Mounting height)
0.05(.002)MIN
(STAND OFF)
23
Details of "A" part
34
22
0.15(.006)
8.00
(.315)
REF
INDEX
0.20(.008)
11.60±0.30
(.457±.012)
0.18(.007)MAX
0.53(.021)MAX
"A"
44
12
Details of "B" part
LEAD No.
1
11
0.80(.0315)TYP
0.30±0.10
(.012±.004)
0.16(.006)
M
0.15±0.05
(.006±.002)
0~10°
"B"
1.40±0.30
(.055±.012)
0.10(.004)
C
Dimensions in mm (inches).
1994 FUJITSU LIMITED F44018S-1C-1
48-pin, Plastic SH-DIP
(DIP-48P-M01)
+0.20
43.69 –0.30
+.008
1.720 –.012
INDEX-1
13.80±0.25
(.543±.010)
INDEX-2
0.51(.020)MIN
5.25(.207)
MAX
0.25±0.05
(.010±.002)
3.00(.118)
MIN
+0.50
1.00 –0
+.020
.039 –0
1.778±0.18
(.070±.007)
1.778(.070)
MAX
C
1994 FUJITSU LIMITED D48002S-3C-3
0.45±0.10
(.018±.004)
15.24(.600)
TYP
15°MAX
40.894(1.610)REF
Dimensions in mm (inches).
25
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9703
FUJITSU LIMITED Printed in Japan
24