FUJITSU MICROELECTRONICS DATA SHEET DS07-16616-1E 32-bit Microcontroller CMOS FR60 MB91460H Series MB91F464HB ■ DESCRIPTION MB91460H series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control applications which require high-speed real-time processing, such as consumer devices and on-board vehicle systems. This series uses the FR60 CPU, which is compatible with the FR family* of CPUs. This series contains the LIN-USART and CAN controllers. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Microelectronics Limited. ■ FEATURES 1. FR60 CPU core • • • • • • • • • • 32-bit RISC, load/store architecture, five-stage pipeline 16-bit fixed-length instructions (basic instructions) Instruction execution speed: 1 instruction per cycle Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions suitable for embedded applications Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C language Register interlock function: Facilitating assembly-language coding Built-in multiplier with instruction-level support Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles Interrupts (save PC/PS) : 6 cycles (16 priority levels) Harvard architecture enabling program access and data access to be performed simultaneously Instructions compatible with the FR family For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ Copyright©2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.8 MB91460H Series 2. Internal peripheral resources • General-purpose ports : Maximum 108 ports • DMAC (DMA Controller) Maximum of 5 channels able to operate simultaneously 2 transfer sources (internal peripheral/software) Activation source can be selected using software Addressing mode specifies full 32-bit addresses (increment/decrement/fixed) Transfer mode (demand transfer/burst transfer/step transfer/block transfer) Transfer data size selectable from 8/16/32-bit Multi-byte transfer enabled (by software) DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H) • A/D converter (successive approximation type) 10-bit resolution: maximum 32 channels Conversion time: minimum 1 μs • External interrupt inputs : maximum 16 channels 3 channels shared with CAN RX or I2C pins • Bit search module (for REALOS) Function to search the first bit position of ‘’1’’, ‘’0’’, ‘’changed’’ from the MSB (most significant bit) within one word • LIN-USART (full duplex double buffer): 4 or 7 channels Clock synchronous/asynchronous selectable Sync-break detection Internal dedicated baud rate generator • I2C bus interface (supports 400 kbps): 2 channels Master/slave transmission and reception Arbitration function, clock synchronization function • CAN controller (C-CAN): 1 channel Maximum transfer speed: 1 Mbps 32 transmission/reception message buffers • Sound generator : 1 channel Tone frequency : PWM frequency divide-by-two (reload value + 1) • Alarm comparator : 1 channel Monitor external voltage Generate an interrupt in case of voltage lower/higher than the defined thresholds (reference voltage) • 16-bit PPG timer : maximum 16 channels • 16-bit reload timer: 8 channels • 16-bit free-run timer: 8 channels (1 channel each for ICU and OCU) • Input capture: maximum 8 channels (operates in conjunction with the free-run timer) • Output compare: maximum 8 channels (operates in conjunction with the free-run timer) • Up/Down counter: 2 channels (2*8-bit or 1*16-bit) • Watchdog timer • Real-time clock • Low-power consumption modes : Sleep/stop mode function • Low voltage detection circuit (Continued) 2 DS07-16616-1E MB91460H Series (Continued) • Clock supervisor Monitors the sub-clock (32 kHz) and the main clock (4 MHz) , and switches to a recovery clock (CR oscillator, etc.) when the oscillations stop. • Clock modulator • Clock monitor • Sub-clock calibration Corrects the real-time clock timer when operating with the 32 kHz or CR oscillator • Main oscillator stabilization timer Generates an interrupt in sub-clock mode after the stabilization wait time has elapsed on the 23-bit stabilization wait time counter • Sub-oscillator stabilization timer Generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization wait time counter 3. Package and technology • • • • Package : QFP-144 CMOS 180 nm technology Power supply range 3 V to 5 V (1.8 V internal logic provided by a step-down voltage converter) Operating temperature range: between - 40°C and + 105°C DS07-16616-1E 3 MB91460H Series ■ PRODUCT LINEUP Feature MB91FV460B MB91F464HB Max. core frequency (CLKB) 100 MHz 100 MHz Max. resource frequency (CLKP) 50 MHz 50 MHz Max. external bus frequency (CLKT) 50 MHz 50 MHz Max. CAN frequency (CLKCAN) 50 MHz 50 MHz Technology 0.18μm 0.18μm yes yes Watchdog Watchdog (RC osc. based) yes (disengageable) yes Bit Search yes yes Reset input (INITX) yes yes Clock Modulator yes yes Clock Monitor yes yes Low Power Mode yes yes DMA 5 ch 5 ch MPU (16 ch)*1 MPU (8 ch)*1 Internal Flash memory 2112KB + external emulation SRAM with 64bit read data 416 KByte yes yes D-RAM 64 KByte 24 KByte ID-RAM 64 KByte 16 KByte Flash-Cache (Instruction cache) 16 KByte 8 KByte 16 KByte Boot Flash + 1KB Boot ROM 4 KByte MMU/MPU Flash memory Flash Protection Boot-ROM / BI-ROM RTC 1 ch 1 ch Free Running Timer 12 ch 8 ch*2 ICU 10 ch MD_3=0: 8 ch MD_3=1: 4 ch*3 OCU 8 ch MD_3=0: 8 ch MD_3=1: 4 ch*4 Reload Timer 16 ch 8 ch*5 PPG 16-bit 32 ch MD_3=0: 16 ch MD_3=1: 8 ch*6 1 ch (old) + 1 ch (new) 1 ch (old) 4 ch (8-bit) / 2 ch (16-bit) MD_3=0: 2 ch (8-bit) / 1 ch (16bit) MD_3=1: NA*7 6 ch (128msg) 1 ch (32msg) 16 ch (FIFO) MD_3=0: 3 ch + 4 ch FIFO*8 MD_3=1: 4 ch FIFO 8 ch 2 ch yes (32bit addr, 32bit data) MD_3=0: no MD_3=1: yes (22bit addr, 16bit data) Sound Generator Up/Down Counter (8/16 bit) C_CAN LIN-USART I2C (400K) FR external bus 4 DS07-16616-1E MB91460H Series Feature MB91FV460B MB91F464HB External Interrupts 32 ch MD_3=0: 16 ch MD_3=1: 12 ch*9 NMI Interrupts 1 ch 1 ch 32 ch + 22 ch MD_3=0: 32 ch MD_3=1: 16 ch 2 ch 1 ch ADC (10-bit) Alarm Comparator Supply Supervisor (low voltage detection) yes yes Clock Supervisor yes yes 4 MHz 4 MHz Main clock oscillator Sub clock oscillator RC oscillator PLL 32kHz 32kHz 100kHz / 2MHz 100kHz / 2MHz x 25 x 25 DSU4 yes no EDSU yes (32 BP)*1 yes (16 BP)*1 Supply voltage 1.8V + 3V/5V 3V/5V Regulator Power consumption Temperature Range (Ta) Package no yes 1.5 W <1W 0..70 C -40..105 C BGA-896 QFP-144 Power on to PLL run < 20 ms < 20 ms Flash Download Time < 8 sec. typical < 5 sec. typical DS07-16616-1E 5 VSS5 P10_0/SYSCLK P09_0/CSX0 P09_1/CSX1 P08_0/WRX0 P08_4/RDX P08_7/RDY P08_1/WRX1 P24_1/INT1 P23_0/RX0/INT8 P23_1/TX0 P23_2/INT9 P23_3 P23_4INT10 P23_5 P23_6/INT11 P23_7 VDD5 VSS5 P22_0/INT12 P22_1 P22_2/INT13 P22_3 P22_4/SDA0/INT14 P22_5/SCL0 P22_6/SDA1/INT15 P22_7/SCL1 P16_0/PPG8 P16_1/PPG9 P16_2/PPG10 P16_3/PPG11 P16_4/PPG12/SGA P16_5/PPG13/SGO P16_6/PPG14 P16_7/PPG15/ATGX VDD5 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD35 P07_5/A5 P07_4/A4 P07_3/A3 P07_2/A2 P07_1/A1 P07_0/A0 P15_3/OCU3/TOT3 P15_2/OCU2/TOT2 P15_1/OCU1/TOT1 P15_0/OCU0/TOT0 P14_3/ICU3/TIN3/TTG3/11 P14_2/ICU2/TIN2/TTG2/10 P14_1/ICU1/TIN1/TTG1/9 P14_0/ICU0/TIN0/TTG0/8 P24_3/INT3 P24_2/INT2 VSS5 VDD5 P28_7/AN15 P28_6/AN14 P28_5/AN13 P28_4/AN12 P28_3/AN11 P28_2/AN10 P28_1/AN9 P28_0/AN8 P29_7/AN7 P29_6/AN6 P29_5/AN5 P29_4/AN4 P29_3/AN3 P29_2/AN2 P29_1/AN1 P29_0/AN0 VSS5 MB91460H Series ■ PIN ASSIGNMENT 1. MB91F464HB with MD_3=1 (TOP VIEW) VSS5 P07_6/A6 P07_7/A7 P06_0/A8 P06_1/A9 P06_2/A10 P06_3/A11 P06_4/A12 P06_5/A13 P06_6/A14 P06_7/A15 P05_0/A16 P05_1/A17 P05_2/A18 P05_3/A19 P05_4/A20 P05_5/A21 VDD35 VSS5 P01_0/D16 P01_1/D17 P01_2/D18 P01_3/D19 P01_4/D20 P01_5/D21 P01_6/D22 P01_7/D23 P00_0/D24 P00_1/D25 P00_2/D26 P00_3/D27 P00_4/D28 P00_5/D29 P00_6/D30 P00_7/D31 VDD35 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP-144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD5 AVCC5 AVRH5 AVSS5 ALARM_0 P18_6/SCK7/CK7 P18_5/SOT7 P18_4/SIN7 P18_2/SCK6/CK6 P18_1/SOT6 P18_0/SIN6 P19_6/SCK5/CK5 P19_5/SOT5 P19_4/SIN5 P19_2/SCK4/CK4 P19_1/SOT4 P19_0/SIN4 VSS5 VDD5 VDD5R VDD5R VCC18C VSS5 NMIX INITX X1A X0A VSS5 X0 X1 MD_3 MONCLK MD_2 MD_1 MD_0 VSS5 DS07-16616-1E VSS5 P20_0/SIN2/AIN0 P20_1/SOT2/BIN0 P20_2/SCK2/ZIN0/CK2 P20_4/SIN3/AIN1 P20_5/SOT3/BIN1 P20_6/SCK3/ZIN1/CK3 P24_0/INT0 P24_1/INT1 P23_0/RX0/INT8 P23_1/TX0 P23_2/INT9 P23_3 P23_4/INT10 P23_5 P23_6/INT11 P23_7 VDD5 VSS5 P22_0/INT12 P22_1 P22_2/INT13 P22_3 P22_4/SDA0/INT14 P22_5/SCL0 P22_6/SDA1/INT15 P22_7/SCL1 P16_0/PPG8 P16_1/PPG9 P16_2/PPG10 P16_3/PPG11 P16_4/PPG12/SGA P16_5/PPG13/SGO P16_6/PPG14 P16_7/PPG15/ATGX VDD5 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD35 P27_5/AN21 P27_4/AN20 P27_3/AN19 P27_2/AN18 P27_1/AN17 P27_0/AN16 P15_3/OCU3/TOT3 P15_2/OCU2/TOT2 P15_1/OCU1/TOT1 P15_0/OCU0/TOT0 P14_3/ICU3/TIN3/TTG3/11 P14_2/ICU2/TIN2/TTG2/10 P14_1/ICU1/TIN1/TTG1/9 P14_0/ICU0/TIN0/TTG0/8 P24_3/INT3 P24_2/INT2 VSS5 VDD5 P28_7/AN15 P28_6/AN14 P28_5/AN13 P28_4/AN12 P28_3/AN11 P28_2/AN10 P28_1/AN9 P28_0/AN8 P29_7/AN7 P29_6/AN6 P29_5/AN5 P29_4/AN4 P29_3/AN3 P29_2/AN2 P29_1/AN1 P29_0/AN0 VSS5 MB91460H Series 2. MB91F46HB with MD_3=0 (TOP VIEW) VSS5 P27_6/AN22 P27_7/AN23 P26_0/AN24 P26_1/AN25 P26_2/AN26 P26_3/AN27 P26_4/AN28 P26_5/AN29 P26_6/AN30 P26_7/AN31 P24_4/INT4 P24_5/INT5 P24_6/INT6 P24_7/INT7 P21_0/SIN0 P21_1/SOT0 VDD35 VSS5 P14_4/ICU4/TIN4/TTG12/4 P14_5/ICU5/TIN5/TTG13/5 P14_6/ICU6/TIN6/TTG14/6 P14_7/ICU7/TIN7/TTG15/7 P15_4/OCU4/TOT4 P15_5/OCU5/TOT5 P15_6/OCU6/TOT6 P15_7/OCU7/TOT7 P17_0/PPG0 P17_1/PPG1 P17_2/PPG2 P17_3/PPG3 P17_4/PPG4 P17_5/PPG5 P17_6/PPG6 P17_7/PPG7 VDD35 DS07-16616-1E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP-144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD5 AVCC5 AVRH5 AVSS5 ALARM_0 P18_6/SCK7/CK7 P18_5/SOT7 P18_4/SIN7 P18_2/SCK6/CK6 P18_1/SOT6 P18_0/SIN6 P19_6/SCK5/CK5 P19_5/SOT5 P19_4/SIN5 P19_2/SCK4/CK4 P19_1/SOT4 P19_0/SIN4 VSS5 VDD5 VDD5R VDD5R VCC18C VSS5 NMIX INITX X1A X0A VSS5 X0 X1 MD_3 MONCLK MD_2 MD_1 MD_0 VSS5 7 MB91460H Series ■ PIN DESCRIPTION 1. MB91F464HB with MD_3=1 Pin no. 2, 3 4 to 11 12 to 17 20 to 27 28 to 35 38 39 40 41 42 43 Pin name P07_6, P07_7 A6, A7 P06_0 to P06_7 A8 to A15 P05_0 to P05_5 A16 to A21 P01_0 to P01_7 D16 to D23 P00_0 to P00_7 D24 to D31 P10_0 SYSCLK P09_0 CSX0 P09_1 CSX1 P08_0 WRX0 P08_4 RDX P08_7 RDY I/O I/O circuit type* I/O B I/O B I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A P08_1 44 WRX1 P24_1 INT1 I/O A RX0 I/O A 8 P23_1 TX0 General-purpose input/output port Signal pins of external address bus (bit8 to bit15) General-purpose input/output port Signal pins of external address bus (bit16 to bit21) General-purpose input/output port Signal pins of external data bus (bit16 to bit23) General-purpose input/output port Signal pins of external data bus (bit24 to bit31) General-purpose input/output port External bus clock output pin General-purpose input/output port Chip select output pins General-purpose input/output port Chip select output pins General-purpose input/output port External write strobe output pins General-purpose input/output port External read strobe output pin General-purpose input/output port External ready input pin External write strobe output pins General-purpose input/output port External interrupt input pins General-purpose input/output port I/O A INT8 47 Signal pins of external address bus (bit6 to bit7) External interrupt input, can only be used in general-purpose IO port mode P23_0 46 General-purpose input/output port General-purpose input/output port INT0 45 Function RX input pin of CAN0 External interrupt input pins I/O A General-purpose input/output port TX output pin of CAN0 DS07-16616-1E MB91460H Series Pin no. 48 49 50 51 52 53 56 57 58 59 Pin name P23_2 INT9 P23_3 P23_4 INT10 P23_5 P23_6 INT11 P23_7 P22_0 INT12 P22_1 P22_2 INT13 P22_3 I/O I/O circuit type* I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A P22_4 60 SDA0 P22_5 SCL0 I/O C SDA1 I/O C 64 65 66 67 P22_7 SCL1 P16_0 PPG8 P16_1 PPG9 P16_2 PPG10 P16_3 PPG11 I/O C PPG12 SGA DS07-16616-1E General-purpose input/output port External interrupt input pin General-purpose input/output port General-purpose input/output port External interrupt input pin General-purpose input/output port General-purpose input/output port External interrupt input pin General-purpose input/output port General-purpose input/output port External interrupt input pin General-purpose input/output port I2C bus DATA input/output pin (open drain) General-purpose input/output port I2C bus clock input/output pin (open drain) I2C bus DATA input/output pin (open drain) External interrupt input pin I/O C I/O A I/O A I/O A I/O A P16_4 68 General-purpose input/output port General-purpose input/output port INT15 63 External interrupt input pins External interrupt input pin P22_6 62 General-purpose input/output port General-purpose input/output port INT14 61 Function General-purpose input/output port I2C bus clock input/output pin (open drain) General-purpose input/output port Output pins of PPG timer General-purpose input/output port Output pins of PPG timer General-purpose input/output port Output pins of PPG timer General-purpose input/output port Output pins of PPG timer General-purpose input/output port I/O A Output pins of PPG timer SGA output pin of sound generator 9 MB91460H Series Pin no. Pin name I/O I/O circuit type* P16_5 69 PPG13 General-purpose input/output port I/O A SGO 70 P16_6 PPG14 PPG15 Output pins of PPG timer SGO output pin of sound generator I/O A P16_7 71 Function General-purpose input/output port Output pins of PPG timer General-purpose input/output port I/O A ATGX Output pins of PPG timer A/D converter external trigger input pin 74 to 76 MD_0 to MD_2 I G Mode setting pins 77 MONCLK O M Clock monitor pin 78 MD_3 I H Mode setting pin 79 X1 — J1 Clock (oscillation) output 80 X0 — J1 Clock (oscillation) input 82 X0A — J2 Sub clock (oscillation) input 83 X1A — J2 Sub clock (oscillation) output 84 INITX I H External reset input pin 85 NMIX I H Non-maskable interrupt input pin I/O A I/O A 92 93 P19_0 SIN4 P19_1 SOT4 P19_2 94 SCK4 96 P19_4 SIN5 P19_5 SOT5 I/O A SCK5 I/O A I/O A 99 10 P18_0 SIN6 P18_1 SOT6 Data output pin of USART4 Clock input/output pin of USART4 General-purpose input/output port Data input pin of USART5 General-purpose input/output port Data output pin of USART5 General-purpose input/output port I/O A CK5 98 General-purpose input/output port External clock input pin of free-run timer 4 P19_6 97 Data input pin of USART4 General-purpose input/output port CK4 95 General-purpose input/output port Clock input/output pin of USART5 External clock input pin of free-run timer 5 I/O A I/O A General-purpose input/output port Data input pin of USART6 General-purpose input/output port Data output pin of USART6 DS07-16616-1E MB91460H Series Pin no. Pin name I/O I/O circuit type* P18_2 100 SCK6 General-purpose input/output port I/O A CK6 P18_4 101 SIN7 P18_5 102 SOT7 SCK7 I/O A I/O A 110 to 117 118 to 125 ALARM_0 P29_0 to P29_7 AN0 to AN7 P28_0 to P28_7 AN8 to AN15 P24_2 128 INT2 P24_3 129 INT3 I/O A ICU0 to ICU3 TIN0 to TIN3 I N I/O B I/O B I/O A I/O A I/O A P07_0 to P07_5 DS07-16616-1E A0 to A5 Clock input/output pin of USART7 Alarm comparator input pin General-purpose input/output port Analog input pins of A/D converter General-purpose input/output port Analog input pins of A/D converter General-purpose input/output port External interrupt input pin General-purpose input/output port External interrupt input pin Input capture input pins External trigger input pins of reload timer General-purpose input/output port I/O A TOT0 to TOT3 138 to 143 Data output pin of USART7 External trigger input pins of PPG timer P15_0 to P15_3 OCU0 to OCU3 General-purpose input/output port General-purpose input/output port TTG0/8 to TTG3/11 134 to 137 Data input pin of USART7 External clock input pin of free-run timer 7 P14_0 to P14_3 130 to 133 General-purpose input/output port General-purpose input/output port CK7 104 Clock input/output pin of USART6 External clock input pin of free-run timer 6 P18_6 103 Function Output compare output pins Reload timer output pins I/O B General-purpose input/output port Signal pins of external address bus (bit0 to bit5) 11 MB91460H Series [Power supply/Ground pins] Pin no. Pin name I/O Function 1, 19, 37, 55, 73, 81, 86, 91, 109, 127 VSS5 Ground pins 54, 72, 90, 108, 126 VDD5 Power supply pins 88, 89 VDD5R 105 AVSS5 107 AVCC5 Power supply pin for A/D converter 106 AVRH5 Reference power supply pin for A/D converter 87 VCC18C Capacitor connection pin for internal regulator 18, 36, 144 VDD35 12 Power supply pins for internal regulator Supply Analog ground pin for A/D converter Power supply pins for external bus part of I/O ring DS07-16616-1E MB91460H Series 2. MB91F464HB with MD_3=0 Pin no. 2 to 3 4 to 11 12 to 15 Pin name P27_6 to P27_7 AN22 to AN23 P26_0 to P26_7 AN24 to AN31 P24_4 to P24_7 INT4 to INT7 P21_0 16 SIN0 P21_1 17 SOT0 I/O I/O circuit type* I/O B I/O B I/O A I/O A I/O A P14_4 to P14_7 ICU4 to ICU7 20 to 23 TIN4 to TIN7 I/O A P17_0 to P17_7 PPG0 to PPG7 I/O A SIN2 I/O A I/O A I/O A ZIN0 I/O A I/O A BIN1 DS07-16616-1E External trigger input pins of reload timer Output compare output pins General-purpose input/output ports Output pins of PPG timer Data input pin of USART2 Data output pin of USART2 Clock input/output pin of USART2 Up/down counter input pin Data input pin of USART3 Up/down counter input pin P20_5 SOT3 Input capture input pins General-purpose input/output ports AIN1 42 Data output pin of USART0 External clock input pin of free-run timer 2 P20_4 SIN3 General-purpose input/output ports General-purpose input/output ports CK2 41 Data input pin of USART0 Up/down counter input pin P20_2 SCK2 General-purpose input/output ports General-purpose input/output ports BIN0 40 External interrupt input pins Up/down counter input pin P20_1 SOT2 General-purpose input/output ports General-purpose input/output ports AIN0 39 Analog input pins of A/D converter Reload timer output pins P20_0 38 General-purpose input/output ports General-purpose input/output ports TOT4 to TOT7 28 to 35 Analog input pins of A/D converter External trigger input pins of PPG timer P15_4 to P15_7 OCU4 to OCU7 General-purpose input/output ports General-purpose input/output ports TTG4/12 to TTG7/15 24 to 27 Function General-purpose input/output ports I/O A Data output pin of USART3 Up/down counter input pin 13 MB91460H Series Pin no. Pin name I/O I/O circuit type* P20_6 43 SCK3 ZIN1 General-purpose input/output ports I/O A CK3 44 45 P24_0 INT0 P24_1 INT1 RX0 I/O A I/O A 48 49 50 51 52 53 56 57 58 59 P23_1 TX0 P23_2 INT9 P23_3 P23_4 INT10 P23_5 P23_6 INT11 P23_7 P22_0 INT12 P22_1 P22_2 INT13 P22_3 I/O A SDA0 I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A I/O A P22_5 SCL0 I/O C SDA1 INT15 14 General-purpose input/output ports External interrupt input pin RX input pin of CAN0 General-purpose input/output port TX output pin of CAN0 General-purpose input/output port External interrupt input pins General-purpose input/output port General-purpose input/output port External interrupt input pin General-purpose input/output port General-purpose input/output port External interrupt input pin General-purpose input/output port General-purpose input/output port External interrupt input pin General-purpose input/output port General-purpose input/output port External interrupt input pin General-purpose input/output port I2C bus DATA input/output pin (open drain) External interrupt input pin I/O C P22_6 62 External interrupt input pin General-purpose input/output ports INT14 61 General-purpose input/output ports External interrupt input pins P22_4 60 Up/down counter input pin General-purpose input/output port INT8 47 Clock input/output pin of USART3 External clock input pin of free-run timer 3 P23_0 46 Function General-purpose input/output ports I2C bus clock input/output pin (open drain) General-purpose input/output ports I/O C I2C bus DATA input/output pin (open drain) External interrupt input pin DS07-16616-1E MB91460H Series Pin no. Pin name P22_7 63 64 to 67 SCL1 P16_0 to P16_3 PPG8 to PPG11 I/O I/O circuit type* I/O C I/O A P16_4 68 69 PPG12 I/O A I2C bus clock input/output pin (open drain) General-purpose input/output ports Output pins of PPG timer Output pins of PPG timer SGA SGA output pin of sound generator P16_5 General-purpose input/output ports PPG13 I/O A P16_6 PPG14 PPG15 Output pins of PPG timer SGO output pin of sound generator I/O A P16_7 71 General-purpose input/output ports General-purpose input/output ports SGO 70 Function General-purpose input/output ports Output pins of PPG timer General-purpose input/output ports I/O A ATGX Output pins of PPG timer A/D converter external trigger input pin 74 to 76 MD_0 to MD_2 I G Mode setting pins 77 MONCLK O M Clock monitor pin 78 MD_3 I H Mode setting pins 79 X1 — J1 Clock (oscillation) output 80 X0 — J1 Clock (oscillation) input 82 X0A — J2 Sub clock (oscillation) input 83 X1A — J2 Sub clock (oscillation) output 84 INITX I H External reset input pin 85 NMIX I H Non-maskable interrupt input pin I/O A I/O A 92 93 P19_0 SIN4 P19_1 SOT4 P19_2 94 SCK4 96 DS07-16616-1E P19_4 SIN5 P19_5 SOT5 Data input pin of USART4 General-purpose input/output ports Data output pin of USART4 General-purpose input/output ports I/O A CK4 95 General-purpose input/output ports Clock input/output pin of USART4 External clock input pin of free-run timer 4 I/O A I/O A General-purpose input/output ports Data input pin of USART5 General-purpose input/output ports Data output pin of USART5 15 MB91460H Series Pin no. Pin name I/O I/O circuit type* P19_6 97 SCK5 General-purpose input/output ports I/O A CK5 98 99 P18_0 SIN6 P18_1 SOT6 SCK6 I/O A I/O A 102 P18_4 SIN7 P18_5 SOT7 I/O A SCK7 I/O A I/O A 110 to 117 118 to 125 128 129 ALARM_0 P29_0 to P29_7 AN0 to AN7 P28_0 to P28_7 AN8 to AN15 P24_2 INT2 P24_3 INT3 I/O A ICU0 to ICU3 TIN0 to TIN3 I N I/O B I/O B I/O A I/O A I/O A P27_0 to P27_5 AN16 to AN21 Data input pin of USART7 General-purpose input/output ports Data output pin of USART7 Clock input/output pin of USART7 Alarm comparator input pin General-purpose input/output ports Analog input pins of A/D converter General-purpose input/output ports Analog input pins of A/D converter General-purpose input/output ports External interrupt input pin General-purpose input/output ports External interrupt input pin Input capture input pins External trigger input pins of reload timer General-purpose input/output ports I/O A TOT0 to TOT3 138 to 143 General-purpose input/output ports External trigger input pins of PPG timer P15_0 to P15_3 OCU0 to OCU3 Clock input/output pin of USART6 General-purpose input/output ports TTG0/8 to TTG3/11 134 to 137 Data output pin of USART6 External clock input pin of free-run timer 7 P14_0 to P14_3 130 to 133 General-purpose input/output ports General-purpose input/output ports CK7 104 Data input pin of USART6 External clock input pin of free-run timer 6 P18_6 103 General-purpose input/output ports General-purpose input/output ports CK6 101 Clock input/output pin of USART5 External clock input pin of free-run timer 5 P18_2 100 Function Output compare output pins Reload timer output pins I/O B General-purpose input/output ports Analog input pins of A/D converter * : For information about the I/O circuit type, refer to “■ I/O CIRCUIT TYPES”. 16 DS07-16616-1E MB91460H Series [Power supply/Ground pins] Pin no. Pin name I/O Function 1, 19, 37, 55, 73, 81, 86, 91, 109, 127 VSS5 Ground pins 54, 72, 90, 108, 126 VDD5 Power supply pins 88, 89 VDD5R 105 AVSS5 107 AVCC5 Power supply pin for A/D converter 106 AVRH5 Reference power supply pin for A/D converter 87 VCC18C Capacitor connection pin for internal regulator 18, 36, 144 VDD35 Power supply pins for internal regulator Supply Analog ground pin for A/D converter Power supply pins for external bus part of I/O ring * : For information about the I/O circuit type, refer to “■ I/O CIRCUIT TYPES”. DS07-16616-1E 17 MB91460H Series ■ I/O CIRCUIT TYPES Type Circuit A Remarks pull-up control driver strength control data line CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. pull- down control R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown B pull-up control driver strength control data line CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. Analog input pull- down control R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown analog input 18 DS07-16616-1E MB91460H Series Type Circuit C Remarks pull-up control data line CMOS level output (IOL = 3mA, IOH = -3mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. pull- down control R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown D pull-up control data line CMOS level output (IOL = 3mA, IOH = -3mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. Analog input pull- down control R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown analog input DS07-16616-1E 19 MB91460H Series Type Circuit E Remarks pull-up control driver strength control data line pull- down control CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA, and IOL = 30mA, IOH = -30mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown F pull-up control driver strength control data line pull- down control CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA, and IOL = 30mA, IOH = -30mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. Analog input R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown analog input 20 DS07-16616-1E MB91460H Series Type Circuit Remarks G R Hysteresis inputs H Mask ROM and EVA device: CMOS Hysteresis input pin Flash device: CMOS input pin 12 V withstand (for MD [2:0]) CMOS Hysteresis input pin Pull-up resistor value: 50 kΩ approx. Pull-up Resistor R Hysteresis inputs J1 X1 R 0 Xout 1 High-speed oscillation circuit: • Programmable between oscillation mode (external crystal or resonator connected to X0/X1 pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin) • Feedback resistor = approx. 2 * 0.5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled or in FCI mode. FCI R X0 FCI or osc disable J2 Xout X1A Low-speed oscillation circuit: • Feedback resistor = approx. 2 * 5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled. R R X0A osc disable DS07-16616-1E 21 MB91460H Series Type Circuit K Remarks pull-up control driver strength control data line pull- down control CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. LCD SEG/COM output R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown LCD SEG/COM L pull-up control driver strength control data line pull- down control CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function) TTL input with input shutdown function Programmable pull-up resistor: 50kΩ approx. Analog input LCD Voltage input R CMOS hysteresis type1 CMOS hysteresis type2 Automotive inputs TTL input standby control for input shutdown VLCD 22 DS07-16616-1E MB91460H Series Type Circuit Remarks M CMOS level tri-state output (IOL = 5mA, IOH = -5mA) tri-state control data line N Analog input pin with protection analog input line DS07-16616-1E 23 MB91460H Series ■ HANDLING DEVICES 1. Preventing Latch-up Latch-up may occur in a CMOS IC if a voltage higher than (VDD5, VDD35 or HVDD5 *1) or less than (VSS5 or HVSS5 *1) is applied to an input or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings. Note *1: HVDD5, HVSS5 are available only on devices having Stepper Motor Controller. 2. Handling of unused input pins If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistor (2KΩ to 10KΩ) or enable internal pullup or pulldown resisters (PPER/PPCR) before the input enable (PORTEN) is activated by software. The mode pins MD_x can be connected to VSS5 or VDD5 directly. Unused ALARM input pins can be connected to AVSS5 directly. 3. Power supply pins In MB91460 series, devices including multiple power supply pins and ground pins are designed as follows; pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latch-up. All of the power supply pins and ground pins must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. Furthermore, the power supply pins and ground pins of the MB91460 series must be connected to the current supply source via a low impedance. It is also recommended to connect a ceramic capacitor of approximately 0.1 μF as a bypass capacitor between power supply pin and ground pin near this device. This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 μF (use a X7R ceramic capacitor) to VCC18C pin for the regulator. 4. Crystal oscillator circuit Noise in proximity to the X0 (X0A) and X1 (X1A) pins can cause the device to operate abnormally. Printed circuit boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass capacitors connected to ground, are located near the device and ground. It is recommended that the printed circuit board layout be designed such that the X0 and X1 pins or X0A and X1A pins are surrounded by ground plane for the stable operation. Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this device. 5. Notes on using external clock When using the external clock, it is necessary to simultaneously supply the X0 (X0A) and the X1 (X1A) pins. In the described combination, X1 (X1A) should be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. At X0 and X1, a frequency up to 16 MHz is possible. (Continued) 24 DS07-16616-1E MB91460H Series (Continued) Example of using opposite phase supply X0 (X0A) X1 (X1A) 6. Mode pins (MD_x) These pins should be connected directly to the power supply or ground pins. To prevent the device from entering test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and power supply pin or ground pin on the printed circuit board as possible and connect them with low impedance. 7. Notes on operating in PLL clock mode If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may continue to operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this selfrunning operation cannot be guaranteed. 8. Pull-up control The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin. DS07-16616-1E 25 MB91460H Series ■ NOTES ON DEBUGGER 1. Execution of the RETI Command If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding interrupt handling routine will be executed repeatedly to the exclusion of other processing. This will prevent the main routine and the handlers for low priority level interrupts from being executed (For example, if the time-base timer interrupt is enabled, stepping over the RETI instruction will always break on the first line of the time-base timer interrupt handler). Disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debugging. 2. Break function If the range of addresses that cause a hardware break (including event breaks) is set to the address of the current system stack pointer or to an area that contains the stack pointer, execution will break after each instruction regardless of whether the user program actually contains data access instructions. To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the target of the hardware break (including an event breaks). 3. Operand break It may cause malfunctions if a stack pointer exists in the area which is set as the DSU operand break. Do not set the access to the areas containing the address of system stack pointer as a target of data event break. 4. Notes on PS register As the PS register is processed in advance by some instructions, when the debugger is being used, the exception handling may result in execution breaking in an interrupt handling routine or the displayed values of the flags in the PS register being updated. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, the operation before and after the EIT always proceeds according to specification. • The following behavior may occur if any of the following occurs in the instruction immediately after a DIV0U/DIV0S instruction: (a) a user interrupt or NMI is accepted; (b) single-step execution is performed; (c) execution breaks due to a data event or from the emulator menu. 1. D0 and D1 flags are updated in advance. 2. An EIT handling routine (user interrupt/NMI or emulator) is executed. 3. Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated to the same values as those in 1. • The following behavior occurs when an ORCCR, STILM, MOV Ri,PS instruction is executed to enable a user interrupt or NMI source while that interrupt is in the active state. 1. The PS register is updated in advance. 2. An EIT handling routine (user interrupt/NMI or emulator) is executed. 3. Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in 1. 26 DS07-16616-1E MB91460H Series ■ BLOCK DIAGRAM 1. MB91F464HB with MD_3=1 FR60 CPU core Flash-Cache 8 Kbytes I-bus 32 D-RAM 16 Kbytes Bit search Flash memory 416 Kbytes (MB91F464HB) D-bus 32 CAN 1 channel RX0 TX0 32 <-> 16 bus adapter ID-RAM 16 Kbytes External bus interface Bus converter RDX WRX0 to WRX1 SYSCLK RDY CSX0 to CSX1 A0 to A21 D16 to D31 DMAC 5 channels R-bus 16 Clock modulator TTG0/8 to TTG3/11 PPG8 to PPG15 TIN0 to TIN3 TOT0 to TOT3 CK4 to CK7 ICU0 to ICU3 Clock supervisor Clock monitor Clock control Interrupt controller PPG timer 8 channels Reload timer 8 channels Free-run timer 8 channels Input capture 4 channels External interrupt 12 channels MONCLK INT0 to INT3, INT8 to to INT15 LIN-USART 4 channels SIN4 to SIN7 SOT4 to SOT7 SCK4 to SCK7 I2C 2 channels SDA0 to SDA1 SCL0 to SCL1 Real time clock OCU0 to OCU3 ALARM_0 DS07-16616-1E Output compare 4 channels Alarm comparator 1 channel A/D converter 16 channels Sound generator 1 channel AN0 to AN15 ATGX SGA SGO 27 MB91460H Series 2. MB91F464HB with MD_3=0 FR60 CPU core Flash-Cache 8 Kbytes I-bus 32 D-RAM 16Kbytes Bit search Flash memory 416 Kbytes (MB91F464HB) D-bus 32 CAN 1 channel RX0 TX0 32 <-> 16 bus adapter ID-RAM 16 Kbytes Bus converter DMAC 5 channels R-bus 16 Clock modulator Clock supervisor Clock monitor Clock control Interrupt controller TTG0/8 to TTG7/15 PPG0 to PPG15 PPG timer 16 channels TIN0 to TIN7 TOT0 to TOT7 Reload timer 8 channels CK2 to CK7 ICU0 to ICU7 Free-run timer 8 channels Input capture 8 channels External interrupt 16 channels MONCLK INT0 to INT15 LIN-USART 7 channels SIN2 to SIN7,SIN0 SOT2 to SOT7,SOT0 SCK2 to SCK7 I2C 2 channels SDA0 to SDA1 SCL0 to SCL1 Real time clock OCU0 to OCU7 AIN0 to AIN1 BIN0 to BIN1 ZIN0 to ZIN1 ALARM_0 28 Output compare 8 channels Up/down counter 2 channels Alarm comparator 1 channel A/D converter 32 channels Sound generator 1 channel AN0 to AN31 ATGX SGA SGO DS07-16616-1E MB91460H Series ■ CPU AND CONTROL UNIT The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced instructions for embedded applications. 1. Features • Adoption of RISC architecture Basic instruction: 1 instruction per cycle • General-purpose registers: 32-bit × 16 registers • 4 Gbytes linear memory space • Multiplier installed 32-bit × 32-bit multiplication: 5 cycles 16-bit × 16-bit multiplication: 3 cycles • Enhanced interrupt processing function Quick response speed (6 cycles) Multiple-interrupt support Level mask function (16 levels) • Enhanced instructions for I/O operation Memory-to-memory transfer instruction Bit processing instruction Basic instruction word length: 16 bits • Low-power consumption Sleep mode/stop mode 2. Internal architecture • The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent of each other. • A 32-bit ↔ 16-bit buffer is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and peripheral resources. • A Harvard ↔ Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between the CPU and the bus controller. DS07-16616-1E 29 MB91460H Series 3. Programming model 3.1. Basic programming model 32 bits Initial value R0 XXXX XXXXH ... R1 ... ... General-purpose registers ... ... ... ... ... R12 R13 AC ... R14 FP XXXX XXXXH R15 SP 0000 0000H Program counter PC Program status PS Table base register TBR Return pointer RP System stack pointer SSP User stack pointer USP Multiply & divide registers MDH ILM SCR CCR MDL 30 DS07-16616-1E MB91460H Series 4. Registers 4.1. General-purpose register 32 bits Initial value R0 XXXX XXXXH R1 ... ... ... ... ... ... ... ... R12 R13 AC ... R14 FP XXXX XXXXH R15 SP 0000 0000H Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation operations and as pointers for memory access. Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular applications. R13 : Virtual accumulator R14 : Frame pointer R15 : Stack pointer Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value). 4.2. PS (Program Status) This register holds the program status, and is divided into three parts, ILM, SCR, and CCR. All undefined bits (-) in the diagram are reserved bits. The read values are always “0”. Write access to these bits is invalid. Bit position → bit 31 bit 20 bit 16 ILM DS07-16616-1E bit 10 bit 8 bit 7 SCR bit 0 CCR 31 MB91460H Series 4.3. CCR (Condition Code Register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SV S I N Z V C Initial value - 000XXXXB SV : Supervisor flag S : Stack flag I : Interrupt enable flag N : Negative enable flag Z : Zero flag V : Overflow flag C : Carry flag 4.4. SCR (System Condition Register) bit 10 bit 9 D1 bit 8 D0 Initial value T XX0B Flag for step division (D1, D0) This flag stores interim data during execution of step division. Step trace trap flag (T) This flag indicates whether the step trace trap is enabled or disabled. The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution of user programs. 4.5. ILM (Interrupt Level Mask register) bit 20 bit 19 bit 18 bit 17 bit 16 Initial value ILM4 ILM3 ILM2 ILM1 ILM0 01111B This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking. The register is initialized to value “01111B” at reset. 4.6. PC (Program Counter) bit 31 bit 0 Initial value XXXXXXXXH The program counter indicates the address of the instruction that is being executed. The initial value at reset is undefined. 32 DS07-16616-1E MB91460H Series 4.7. TBR (Table Base Register) bit 31 bit 0 Initial value 000FFC00H The table base register stores the starting address of the vector table used in EIT processing. The initial value at reset is 000FFC00H. 4.8. RP (Return Pointer) bit 31 bit 0 Initial value XXXXXXXXH The return pointer stores the address for return from subroutines. During execution of a CALL instruction, the PC value is transferred to this RP register. During execution of a RET instruction, the contents of the RP register are transferred to PC. The initial value at reset is undefined. 4.9. USP (User Stack Pointer) bit 31 bit 0 Initial value XXXXXXXXH The user stack pointer, when the S flag is “1”, this register functions as the R15 register. • The USP register can also be explicitly specified. The initial value at reset is undefined. • This register cannot be used with RETI instructions. 4.10. Multiply & divide registers bit 31 bit 0 MDH MDL These registers are for multiplication and division, and are each 32 bits in length. The initial value at reset is undefined. DS07-16616-1E 33 MB91460H Series ■ EMBEDDED PROGRAM/DATA MEMORY (FLASH) 1. Flash features • • • • • MB91F464HB : 416 Kbytes (6 × 64 Kbytes + 4 × 8 Kbytes = 3.25 Mbits) Programmable wait states for read/write access Flash and Boot security with security vector at 0x0014:8000 - 0x0014:800F Boot security Basic specification: Same as MBM29LV400TC (except size and part of sector configuration) 2. Operation modes: (1) 32-bit CPU mode: • CPU reads and executes programs in word (32-bit) length units. • Actual Flash Memory access is performed in word (32-bit) length units. (2) 16-bit CPU mode: • CPU reads and writes in half-word (16-bit) length units. • Program execution from the Flash is not possible. • Actual Flash Memory access is performed in word (16-bit) length units. (3) Flash memory mode (external access to Flash memory enabled) Note: The operation mode of the flash memory can be selected using a Boot-ROM function. The function start address is 0xBF60. The parameter description is given in the Hardware Manual in chapter 54.6 "Flash Access Mode Switching". 34 DS07-16616-1E MB91460H Series 3. Flash access in CPU mode 3.1. Flash configuration 3.1.1. Flash memory map MB91F464HB Address 0014:FFFFh 0014:C000h SA6 (8KB) SA7 (8KB) 0014:BFFFh 0014:8000h SA4 (8KB) SA5 (8KB) 0014:7FFFh 0014:4000h SA2 (8KB) SA3 (8KB) 0014:3FFFh 0014:0000h SA0 (8KB) SA1 (8KB) 0013:FFFFh 0012:0000h SA22 (64KB) SA23 (64KB) 0011:FFFFh 0010:0000h SA20 (64KB) SA21 (64KB) 000F:FFFFh 000E:0000h SA18 (64KB) SA19 (64KB) ROMS5 000D:FFFFh 000C:0000h SA16 (64KB) SA17 (64KB) ROMS4 000B:FFFFh 000A:0000h SA14 (64KB) SA15 (64KB) ROMS3 0009:FFFFh 0008:0000h SA12 (64KB) SA13 (64KB) ROMS2 0007:FFFFh 0006:0000h SA10 (64KB) SA11 (64KB) ROMS1 0005:FFFFh 0004:0000h SA8 (64KB) SA9 (64KB) ROMS0 ROMS7 ROMS6 addr+0 16bit read/write addr+1 addr+2 dat[31:16] addr+3 dat[15:0] addr+4 addr+5 addr+6 dat[31:16] 32bit read dat[31:0] dat[31:0] Legend Memory not available in this area Memory available in this area DS07-16616-1E addr+7 dat[15:0] 35 MB91460H Series 3.2. Flash access timing settings in CPU mode The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or maximum clock modulation) for Flash read and write access. 3.2.1. Core clock (CLKB) ATD ALEH EQ WEXH WTC to 24 MHz 0 0 0 - 1 to 48 MHz 0 0 1 - 2 to 96 MHz 1 1 3 - 4 to 100 MHz 1 1 3 - 4 3.2.2. 36 Flash read timing settings (synchronous read) Remark Flash write timing settings (synchronous write) Core clock (CLKB) ATD ALEH EQ WEXH WTC to 16 MHz 0 - - 0 3 to 32 MHz 0 - - 0 4 to 48 MHz 0 - - 0 5 to 64 MHz 1 - - 0 6 to 96 MHz 1 - - 0 7 to 100 MHz 1 - - 0 7 Remark DS07-16616-1E MB91460H Series 3.3. Address mapping from CPU to parallel programming mode The following tables show the calculation from CPU addresses to flash macro addresses which are used in parallel programming. 3.3.1. Address mapping MB91F464HB CPU Address Condition (addr) Flash sectors FA (flash address) Calculation 14:8000h to 14:FFFFh addr[2]==0 SA4, SA6 (8 Kbyte) FA := addr - addr%00:4000h + (addr%00:4000h)/2 (addr/2)%4 + addr%4 - 0D:0000h 14:8000h to 14:FFFFh addr[2]==1 SA5, SA7 (8 Kbyte) FA := addr - addr%00:4000h + (addr%00:4000h)/2 + 00:2000h - (addr/2)%4 + addr%4 - 0D:0000h 0A:0000h to 0F:FFFFh addr[2]==0 SA14, SA16, SA18 (64 Kbyte) FA := addr - addr%02:0000 + (addr%02:0000h)/2 (addr/2)%4 + addr%4 0A:0000h to 0F:FFFFh addr[2]==1 SA15, SA17, SA19 (64 Kbyte) FA := addr - addr%02:0000h + (addr%02:0000h)/2 + 01:0000h - (addr/2)%4 + addr%4 Note: FA result is without 20:0000h offset for parallel Flash programming. Set offset by keeping FA[21] = 1 as described in section “Parallel Flash programming mode”. DS07-16616-1E 37 MB91460H Series 4. Parallel Flash programming mode 4.1. Flash configuration in parallel Flash programming mode Parallel Flash programming mode (MD[2:0] = 111): MB91F464HB FA[20:0] 001F:FFFFh 001F:0000h SA19 (64KB) 001E:FFFFh 001E:0000h SA18 (64KB) 001D:FFFFh 001D:0000h SA17 (64KB) 001C:FFFFh 001C:0000h SA16 (64KB) 001B:FFFFh 001B:0000h SA15 (64KB) 001A:FFFFh 001A:0000h SA14 (64KB) SA13 (64KB) SA12 (64KB) SA11 (64KB) SA10 (64KB) SA9 (64KB) SA8 (64KB) 0017:FFFFh 0017:E000h SA7 (8KB) 0017:DFFFh 0017:C000h SA6 (8KB) 0017:BFFFh 0017:A000h SA5 (8KB) 0017:9FFFh 0017:8000h SA4 (8KB) SA3 (8KB) SA2 (8KB) SA1 (8KB) SA0 (8KB) 16bit write mode FA[1:0]=00 FA[1:0]=10 DQ[15:0] DQ[15:0] Remark: Always keep FA[0] = 0 and FA[20] = 1 Legend Memory available in this area Memory not available in this area 38 DS07-16616-1E MB91460H Series 4.2. Pin connections in parallel programming mode Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory's interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of the signals to GP-Ports. Please see table below for signal mapping. In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set when writing/erasing using the parallel Flash programmer. In this mode, all operations of the 8.5 Mbits Flash memory's Auto Algorithms are available. Correspondence between MBM29LV400TC and Flash Memory Control Signals MBM29LV400TC MB91F464HB FR-CPU mode External pins external pins Comment Flash memory mode Normal function Pin number - INITX - INITX 84 RESET - FRSTX GP16_6 70 - - MD2 MD2 76 Set to ‘1’ - - MD1 MD1 75 Set to ‘1’ - - MD0 MD0 74 Set to ‘1’ RY/BY FMCS:RDY bit RY/BYX GP18_2 100 BYTE Internally fixed to ‘H’ BYTEX GP16_4 68 WE WEX GP16_7 71 OE OEX GP07_7 3 CEX GP07_6 2 ATDIN GP18_6 103 Set to ‘0’ EQIN GP18_5 102 Set to ‘0’ - TESTX GP16_5 69 Set to ‘1’ - RDYI GP18_4 101 Set to ‘0’ A-1 FA0 GP05_5 17 Set to ‘0’ A0 to A3 FA1 to FA4 GP19_0 to GP19_2, GP19_4 92 to 95 A4 to A7 FA5 to FA8 GP19_5 to GP19_6, GP18_0 to GP18_1 96 to 99 A8 to A11 FA9 to FA12 GP06_0 to GP06_3 4 to 7 A12 to A15 FA13 to FA16 GP06_4 to GP06_7 8 to 11 A16 to A18 FA17 to FA19 GP05_0 to GP05_2 12 to 14 A19 FA20 GP05_3 15 DQ0 to DQ7 GP00_0 to GP00_7 28 to 35 DQ8 to DQ15 GP01_0 to GP01_7 20 to 27 CE - Internal control signal + control via interface circuit Internal address bus DQ0 to DQ7 DQ8 to DQ15 DS07-16616-1E Internal data bus Set to ‘1’ 39 MB91460H Series 5. Poweron Sequence in parallel programming mode The flash memory can be accessed in programming mode after a certain wait time, which is needed for Security Vector fetch: • Minimum wait time after VDD5/VDD5R power on: • Minimum wait time after INITX rising: 2.76 ms 1.0 ms 6. Flash Security 6.1. Vector addresses Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1, BSV2) controlling the protection functions of the Flash Security Module: FSV1: 0x14:8000 FSV2: 0x14:8008 6.2. BSV1: 0x14:8004 BSV2: 0x14:800C Security Vector FSV1 The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes and the individual write protection of the 8 KBytes sectors. 6.2.1. FSV1 (bit31 to bit16) The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write protection modes. Explanation of the bits in the Flash Security Vector FSV1[31:16] FSV1[18] FSV1[17] FSV1[16] FSV1[31:19] Write Protection Write Protection Read Protection Level Flash Security Mode set all to ‘0’ set to ‘0’ set to ‘0’ set to ‘1’ Read Protection (all device modes, except INTVEC mode MD[2:0]=”000”) set all to ‘0’ set to ‘0’ set to ‘1’ set to ‘0’ Write Protection (all device modes, without exception) set all to ‘0’ set to ‘0’ set to ‘1’ set to ‘1’ Read Protection (all device modes, except INTVEC mode MD[2:0]=”000”) and Write Protection (all device modes) set all to ‘0’ set to ‘1’ set to ‘0’ set to ‘1’ Read Protection (all device modes, except INTVEC mode MD[2:0]=”000”) set all to ‘0’ set to ‘1’ set to ‘1’ set to ‘0’ Write Protection (all device modes, except INTVEC mode MD[2:0]=”000”) set to ‘1’ Read Protection (all device modes, except INTVEC mode MD[2:0]=”000”) and Write Protection (all device modes except INTVEC mode MD[2:0]=”000”) set all to ‘0’ 40 set to ‘1’ set to ‘1’ DS07-16616-1E MB91460H Series 6.2.2. FSV1 (bit15 to bit0) MB91F464HB The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write protection of the 8 KBytes sectors. It is only evaluated if write protection bit FSV1[17] is set. Explanation of the bits in the Flash Security Vector FSV1[15:0] Enable Write Disable Write FSV1 bit Sector Protection Protection Comment FSV1[3:0] ⎯ ⎯ ⎯ not available FSV1[4] SA4 set to “0” — Write protection is mandatory! FSV1[5] SA5 set to “0” set to “1” FSV1[6] SA6 set to “0” set to “1” FSV1[7] SA7 set to “0” set to “1” FSV1[15:8] ⎯ ⎯ ⎯ not available Note: It is mandatory to always set the sector where the Flash Security Vectors FSV1 and FSV2 are located to write protected (here sector SA4). Otherwise it is possible to overwrite the Security Vector to a setting where it is possible to either read out the Flash content or manipulate data by writing. See section “Flash access in CPU mode” for an overview about the sector organisation of the Flash Memory. DS07-16616-1E 41 MB91460H Series 6.3. Security Vector FSV2 MB91F464HB The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write protection of the 64 KByte sectors. It is only evaluated if write protection bit FSV1[17] is set. Explanation of the bits in the Flash Security Vector FSV2[31:0] Enable Write Disable Write Protection Protection FSV2 bit Sector FSV2[5:0] ⎯ ⎯ ⎯ FSV2[6] SA14 set to “0” set to “1” FSV2[7] SA15 set to “0” set to “1” FSV2[8] SA16 set to “0” set to “1” FSV2[9] SA17 set to “0” set to “1” FSV2[10] SA18 set to “0” set to “1” FSV2[11] SA19 set to “0” set to “1” FSV2[31:12] ⎯ ⎯ ⎯ Comment not available not available Note : See section “Flash access in CPU mode” for an overview about the sector organisation of the Flash Memory. 42 DS07-16616-1E MB91460H Series ■ MEMORY SPACE The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access. • Direct addressing area The following address space area is used for I/O. This area is called direct addressing area, and the address of an operand can be specified directly in an instruction. The size of directly addressable area depends on the length of the data being accessed as shown below. Byte data access : 000H to 0FFH Half word access : 000H to 1FFH Word data access : 000H to 3FFH DS07-16616-1E 43 MB91460H Series ■ MEMORY MAPS 1. MB91F464HB MB91F464HB 00000000H 00000400H 00001000H I/O (direct addressing area) I/O DMA 00002000H 00004000H Flash-Cache (8 Kbytes) 00006000H 00007000H Flash memory control 00008000H 0000B000H 0000C000H Boot ROM (4 Kbytes) CAN 0000D000H 0002C000H 00030000H D-RAM (0 wait, 16 Kbytes) ID-RAM (16 Kbytes) 00034000H 00040000H External bus area 00080000H 000A0000H Flash memory (384 Kbytes) 00100000H 00148000H External bus area Flash memory (32 Kbytes) 00150000H 00180000H External bus area 00500000H External data bus FFFFFFFFH Note: 44 Access prohibited areas DS07-16616-1E MB91460H Series ■ I/O MAP 1. MB91F464HB Address 000000H Register +0 +1 +2 +3 PDR0 [R/W] XXXXXXXX PDR1 [R/W] XXXXXXXX PDR2 [R/W] XXXXXXXX PDR3 [R/W] XXXXXXXX Block T-unit port data register Read/write attribute Register initial value after reset Register name (column 1 register at address 4n, column 2 register at address 4n + 1...) Leftmost register address (for word access, the register in column 1 becomes the MSB side of the data.) Note : Initial values of register bits are represented as follows: “ 1 ” : Initial value “ 1 ” “ 0 ” : Initial value “ 0 ” “ X ” : Initial value “ undefined ” “ - ” : No physical register at this location Access is barred with an undefined data access attribute. DS07-16616-1E 45 MB91460H Series Address Register Block +0 +1 +2 +3 000000H PDR00 [R/W] XXXXXXXX PDR01 [R/W] XXXXXXXX Reserved Reserved 000004H Reserved PDR05 [R/W] - - XXXXXX PDR06 [R/W] XXXXXXXX PDR07 [R/W] XXXXXXXX 000008H PDR08 [R/W] X--X---X PDR09 [R/W] - - - - - - XX PDR10 [R/W] -------X Reserved 00000CH Reserved Reserved PDR14 [R/W] XXXXXXXX PDR15 [R/W] XXXXXXXX 000010H PDR16 [R/W] XXXXXXXX PDR17 [R/W] XXXXXXXX PDR18 [R/W] - XXX - XXX PDR19 [R/W] - XXX - XXX 000014H PDR20 [R/W] - XXX - XXX PDR21 [R/W] - - - - - - XX PDR22 [R/W] XXXXXXXX PDR23 [R/W] XXXXXXXX 000018H PDR24 [R/W] XXXXXXXX Reserved PDR26 [R/W] XXXXXXXX PDR27 [R/W] XXXXXXXX 00001CH PDR28 [R/W] XXXXXXXX PDR29 [R/W] XXXXXXXX Reserved Reserved 000020H to 00002CH R-bus Port Data Register Reserved 000030H EIRR0 [R/W] XXXXXXXX ENIR0 [R/W] 00000000 ELVR0 [R/W] 00000000 00000000 External interrupt (INT 0 to INT 7) 000034H EIRR1 [R/W] XXXXXXXX ENIR1 [R/W] 00000000 ELVR1 [R/W] 00000000 00000000 External interrupt (INT 8 to INT 15) 000038H DICR [R/W] -------0 HRCL [R/W] 0 - - 11111 RBSYNC Delay interrupt Reserved 00003CH 000040H 000044H SCR00 [R/W,W] 00000000 SMR00 [R/W,W] 00000000 ESCR00 [R/W] 00000X00 ECCR00 [R/W,R,W] -00000XX 000048H 00004CH 000050H 000054H 46 Reserved SSR00 [R/W,R] 00001000 RDR00/TDR00 [R/W] 00000000 Reserved Reserved SCR02 [R/W,W] 00000000 SMR02 [R/W,W] 00000000 ESCR02 [R/W] 00000X00 ECCR02 [R/W,R,W] -00000XX LIN-USART 0 Reserved SSR02 [R/W,R] 00001000 RDR02/TDR02 [R/W] 00000000 LIN-USART 2 Reserved DS07-16616-1E MB91460H Series Address Register Block +0 +1 +2 +3 SCR03 [R/W,W] 00000000 SMR03 [R/W,W] 00000000 SSR03 [R/W,R] 00001000 RDR03/TDR03 [R/W] 00000000 00005CH ESCR03 [R/W] 00000X00 ECCR03 [R/W,R,W] -00000XX 000060H SCR04 [R/W,W] 00000000 SMR04 [R/W,W] 00000000 SSR04 [R/W,R] 00001000 RDR04/TDR04 [R/W] 00000000 000064H ESCR04 [R/W] 00000X00 ECCR04 [R/W,R,W] -00000XX FSR04 [R] - - - 00000 FCR04 [R/W] 0001 - 000 000068H SCR05 [R/W,W] 00000000 SMR05 [R/W,W] 00000000 SSR05 [R/W,R] 00001000 RDR05/TDR05 [R/W] 00000000 00006CH ESCR05 [R/W] 00000X00 ECCR05 [R/W,R,W] -00000XX FSR05 [R] - - - 00000 FCR05 [R/W] 0001 - 000 000070H SCR06 [R/W,W] 00000000 SMR06 [R/W,W] 00000000 SSR06 [R/W,R] 00001000 RDR06/TDR06 [R/W] 00000000 000074H ESCR06 [R/W] 00000X00 ECCR06 [R/W,R,W] -00000XX FSR06 [R] - - - 00000 FCR06 [R/W] 0001 - 000 000078H SCR07 [R/W,W] 00000000 SMR07 [R/W,W] 00000000 SSR07 [R/W,R] 00001000 RDR07/TDR07 [R/W] 00000000 00007CH ESCR07 [R/W] 00000X00 ECCR07 [R/W,R,W] -00000XX FSR07 [R] - - - 00000 FCR07 [R/W] 0001 - 000 000080H BGR100 [R/W] 00000000 BGR000 [R/W] 00000000 Reserved Reserved 000084H BGR102 [R/W] 00000000 BGR002 [R/W] 00000000 BGR103 [R/W] 00000000 BGR003 [R/W] 00000000 000088H BGR104 [R/W] 00000000 BGR004 [R/W] 00000000 BGR105 [R/W] 00000000 BGR005 [R/W] 00000000 00008CH BGR106 [R/W] 00000000 BGR006 [R/W] 00000000 BGR107 [R/W] 00000000 BGR007 [R/W] 00000000 000058H 000090H to 0000CCH DS07-16616-1E LIN-USART 3 Reserved Reserved LIN-USART 4 with FIFO LIN-USART 5 with FIFO LIN-USART 6 with FIFO LIN-USART 7 with FIFO Baud rate Generator LIN-USART 0 to 7 Reserved 47 MB91460H Series Address Register Block +0 +1 +2 +3 0000D0H IBCR0 [R/W] 00000000 IBSR0 [R] 00000000 ITBAH0 [R/W] - - - - - - 00 ITBAL0 [R/W] 00000000 0000D4H ITMKH0 [R/W] 00 - - - - 11 ITMKL0 [R/W] 11111111 ISMK0 [R/W] 01111111 ISBA0 [R/W] - 0000000 0000D8H Reserved IDAR0 [R/W] 00000000 ICCR0 [R/W] - 0011111 Reserved 0000DCH IBCR1 [R/W] 00000000 IBSR1 [R] 00000000 ITBAH1 [R/W] - - - - - - 00 ITBAL1 [R/W] 00000000 0000E0H ITMKH1 [R/W] 00 - - - - 11 ITMKL1 [R/W] 11111111 ISMK1 [R/W] 01111111 ISBA1 [R/W] - 0000000 0000E4H Reserved IDAR1 [R/W] 00000000 ICCR1 [R/W] - 0011111 Reserved 0000E8H to 0000FCH Reserved I2C 0 I2C 1 Reserved 000100H GCN10 [R/W] 00110010 00010000 Reserved GCN20 [R/W] - - - - 0000 PPG Control 0 to 3 000104H GCN11 [R/W] 00110010 00010000 Reserved GCN21 [R/W] - - - - 0000 PPG Control 4 to 7 000108H GCN12 [R/W] 00110010 00010000 Reserved GCN22 [R/W] - - - - 0000 PPG Control 8 to 11 000110H PTMR00 [R] 11111111 11111111 000114H PDUT00 [W] XXXXXXXX XXXXXXXX 000118H PTMR01 [R] 11111111 11111111 00011CH PDUT01 [W] XXXXXXXX XXXXXXXX 000120H PTMR02 [R] 11111111 11111111 000124H PDUT02 [W] XXXXXXXX XXXXXXXX 000128H PTMR03 [R] 11111111 11111111 00012CH PDUT03 [W] XXXXXXXX XXXXXXXX 000130H PTMR04 [R] 11111111 11111111 000134H PDUT04 [W] XXXXXXXX XXXXXXXX 48 PCSR00 [W] XXXXXXXX XXXXXXXX PCNH00 [R/W] 0000000 - PCNL00 [R/W] 000000 - 0 PCSR01 [W] XXXXXXXX XXXXXXXX PCNH01 [R/W] 0000000 - PCNL01 [R/W] 000000 - 0 PCSR02 [W] XXXXXXXX XXXXXXXX PCNH02 [R/W] 0000000 - PCNL02 [R/W] 000000 - 0 PCSR03 [W] XXXXXXXX XXXXXXXX PCNH03 [R/W] 0000000 - PCNL03 [R/W] 000000 - 0 PCSR04 [W] XXXXXXXX XXXXXXXX PCNH04 [R/W] 0000000 - PCNL04 [R/W] 000000 - 0 PPG 0 PPG 1 PPG 2 PPG 3 PPG 4 DS07-16616-1E MB91460H Series Address Register +0 +1 000138H PTMR05 [R] 11111111 11111111 00013CH PDUT05 [W] XXXXXXXX XXXXXXXX 000140H PTMR06 [R] 11111111 11111111 000144H PDUT06 [W] XXXXXXXX XXXXXXXX 000148H PTMR07 [R] 11111111 11111111 00014CH PDUT07 [W] XXXXXXXX XXXXXXXX 000150H PTMR08 [R] 11111111 11111111 000154H PDUT08 [W] XXXXXXXX XXXXXXXX 000158H PTMR09 [R] 11111111 11111111 00015CH PDUT09 [W] XXXXXXXX XXXXXXXX 000160H PTMR10 [R] 11111111 11111111 000164H PDUT10 [W] XXXXXXXX XXXXXXXX 000168H PTMR11 [R] 11111111 11111111 00016CH PDUT11 [W] XXXXXXXX XXXXXXXX 000170H to 00017CH 000180H Block +2 +3 PCSR05 [W] XXXXXXXX XXXXXXXX PCNH05 [R/W] 0000000 - PCNL05 [R/W] 000000 - 0 PCSR06 [W] XXXXXXXX XXXXXXXX PCNH06 [R/W] 0000000 - PCNL06 [R/W] 000000 - 0 PCSR07 [W] XXXXXXXX XXXXXXXX PCNH07 [R/W] 0000000 - PCNL07 [R/W] 000000 - 0 PCSR08 [W] XXXXXXXX XXXXXXXX PCNH08 [R/W] 0000000 - PCNL08 [R/W] 000000 - 0 PCSR09 [W] XXXXXXXX XXXXXXXX PCNH09 [R/W] 0000000 - PCNL09 [R/W] 000000 - 0 PCSR10 [W] XXXXXXXX XXXXXXXX PCNH10 [R/W] 0000000 - PCNL10 [R/W] 000000 - 0 PCSR11 [W] XXXXXXXX XXXXXXXX PCNH11 [R/W] 0000000 - PCNL11 [R/W] 000000 - 0 Reserved Reserved ICS01 [R/W] 00000000 PPG 6 PPG 7 PPG 8 PPG 9 PPG 10 PPG 11 Reserved Reserved ICS23 [R/W] 00000000 000184H IPCP0 [R] XXXXXXXX XXXXXXXX IPCP1 [R] XXXXXXXX XXXXXXXX 000188H IPCP2 [R] XXXXXXXX XXXXXXXX IPCP3 [R] XXXXXXXX XXXXXXXX DS07-16616-1E PPG 5 Input Capture 0 to 3 49 MB91460H Series Address Register +0 +1 Block +2 +3 00018CH OCS01 [R/W] - - - 0 - - 00 0000 - - 00 OCS23 [R/W] - - - 0 - - 00 0000 - - 00 000190H OCCP0 [R/W] XXXXXXXX XXXXXXXX OCCP1 [R/W] XXXXXXXX XXXXXXXX 000194H OCCP2 [R/W] XXXXXXXX XXXXXXXX OCCP3 [R/W] XXXXXXXX XXXXXXXX 000198H SGCRH [R/W] 0000 - - 00 SGCRL [R/W] - - 0 - - 000 00019CH SGAR [R/W] 00000000 Reserved 0001A0H ADERH [R/W] 00000000 00000000 SGFR [R/W, R] XXXXXXXX XXXXXXXX SGTR [R/W] XXXXXXXX SGDR [R/W] XXXXXXXX ADCS1 [R/W] 00000000 ADCS0 [R/W] 00000000 ADCR1 [R] 000000XX ADCR0 [R] XXXXXXXX 0001A8H ADCT1 [R/W] 00010000 ADCT0 [R/W] 00101100 ADSCH [R/W] - - - 00000 ADECH [R/W] - - - 00000 0001ACH Reserved ACSR0 [R/W] -11XXX00 Reserved Reserved TMRLR0 [W] XXXXXXXX XXXXXXXX 0001B4H Reserved 0001B8H TMRLR1 [W] XXXXXXXX XXXXXXXX 0001BCH Reserved 0001C0H TMRLR2 [W] XXXXXXXX XXXXXXXX 0001C4H Reserved 0001C8H TMRLR3 [W] XXXXXXXX XXXXXXXX 0001CCH Reserved 0001D0H TMRLR4 [W] XXXXXXXX XXXXXXXX 0001D4H 50 Reserved Sound Generator ADERL [R/W] 00000000 00000000 0001A4 0001B0H Output Compare 0 to 3 TMR0 [R] XXXXXXXX XXXXXXXX TMCSRH0 [R/W] - - - 00000 TMCSRL0 [R/W] 0 - 000000 TMR1 [R] XXXXXXXX XXXXXXXX TMCSRH1 [R/W] - - - 00000 TMCSRL1 [R/W] 0 - 000000 TMR2 [R] XXXXXXXX XXXXXXXX TMCSRH2 [R/W] - - - 00000 TMCSRL2 [R/W] 0 - 000000 TMR3 [R] XXXXXXXX XXXXXXXX TMCSRH3 [R/W] - - - 00000 TMCSRL3 [R/W] 0 - 000000 TMR4 [R] XXXXXXXX XXXXXXXX TMCSRH4 [R/W] - - - 00000 TMCSRL4 [R/W] 0 - 000000 A/D Converter Alarm Comparator 0 to 1 Reload Timer 0 (PPG 0, PPG 1) Reload Timer 1 (PPG 2, PPG 3) Reload Timer 2 (PPG 4, PPG 5) Reload Timer 3 (PPG 6, PPG 7) Reload Timer 4 (PPG 8, PPG 9) DS07-16616-1E MB91460H Series Address Register +0 0001D8H +1 TMRLR5 [W] XXXXXXXX XXXXXXXX 0001DCH Reserved 0001E0H TMRLR6 [W] XXXXXXXX XXXXXXXX 0001E4H Reserved 0001E8H TMRLR7 [W] XXXXXXXX XXXXXXXX Block +2 +3 TMR5 [R] XXXXXXXX XXXXXXXX TMCSRH5 [R/W] - - - 00000 TMCSRL5 [R/W] 0 - 000000 TMR6 [R] XXXXXXXX XXXXXXXX TMCSRH6 [R/W] - - - 00000 TMCSRL6 [R/W] 0 - 000000 TMR7 [R] XXXXXXXX XXXXXXXX Reload Timer 6 (PPG 12, PPG 13) Reload Timer 7 (PPG 14, PPG 15) (A/D Converter) 0001ECH Reserved TMCSRH7 [R/W] - - - 00000 0001F0H TCDT0 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS0 [R/W] 00000000 Free Running Timer 0 (ICU 0, ICU 1) 0001F4H TCDT1 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS1 [R/W] 00000000 Free Running Timer 1 (ICU 2, ICU 3) 0001F8H TCDT2 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS2 [R/W] 00000000 Free Running Timer 2 (OCU 0, OCU 1) 0001FCH TCDT3 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS3 [R/W] 00000000 Free Running Timer 3 (OCU 2, OCU 3) 000200H DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000204H DMACB0 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000208H DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 00020CH DMACB1 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000210H DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000214H DMACB2 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000218H DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 00021CH DMACB3 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DS07-16616-1E TMCSRL7 [R/W] 0 - 000000 Reload Timer 5 (PPG 10, PPG 11) DMAC 51 MB91460H Series Address Register +0 +1 Block +2 +3 000220H DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX 000224H DMACB4 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000228H to 00023CH Reserved 000240H DMAC DMACR [R/W] 00 - - 0000 Reserved 000244H to 0002CCH 0002D0H Reserved Reserved ICS045 [R/W] 00000000 Reserved Reserved ICS67 [R/W] 00000000 0002D4H IPCP4 [R] XXXXXXXX XXXXXXXX IPCP5 [R] XXXXXXXX XXXXXXXX 0002D8H IPCP6 [R] XXXXXXXX XXXXXXXX IPCP7 [R] XXXXXXXX XXXXXXXX 0002DCH OCS45 [R/W] - - - 0 - - 00 0000 - - 00 OCS67 [R/W] - - - 0 - - 00 0000 - - 00 0002E0H OCCP4 [R/W] XXXXXXXX XXXXXXXX OCCP5 [R/W] XXXXXXXX XXXXXXXX 0002E4H OCCP6 [R/W] XXXXXXXX XXXXXXXX OCCP7 [R/W] XXXXXXXX XXXXXXXX 0002E8H to 0002ECH Reserved Input Capture 4 to 7 Output Compare 4 to 7 Reserved 0002F0H TCDT4 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS4 [R/W] 00000000 Free Running Timer 4 (ICU 4, ICU 5) 0002F4H TCDT5 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS5 [R/W] 00000000 Free Running Timer 5 (ICU 6, ICU 7) 0002F8H TCDT6 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS6 [R/W] 00000000 Free Running Timer 6 (OCU 4, OCU 5) 0002FCH TCDT7 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS7 [R/W] 00000000 Free Running Timer 7 (OCU 6, OCU 7) 52 DS07-16616-1E MB91460H Series Address Register Block +0 +1 +2 +3 000300H UDRC1 [W] 00000000 UDRC0 [W] 00000000 UDCR1 [R] 00000000 UDCR0 [R] 00000000 000304H UDCCH0 [R/W] 00000000 UDCCL0 [R/W] 00001000 Reserved UDCS0 [R/W] 00000000 000308H UDCCH1 [R/W] 00000000 UDCCL1 [R/W] 00001000 Reserved UDCS1 [R/W] 00000000 00030CH to 00031CH 000320H Reserved GCN13 [R/W] 00110010 00010000 000324H to 00032CH PTMR12 [R] 11111111 11111111 000334H PDUT12 [W] XXXXXXXX XXXXXXXX 000338H PTMR13 [R] 11111111 11111111 00033CH PDUT13 [W] XXXXXXXX XXXXXXXX 000340H PTMR14 [R] 11111111 11111111 000344H PDUT14 [W] XXXXXXXX XXXXXXXX 000348H PTMR15 [R] 11111111 11111111 00034CH PDUT15 [W] XXXXXXXX XXXXXXXX 000350H to 00038CH 000390H 000394H to 0003ECH DS07-16616-1E Reserved GCN23 [R/W] - - - - 0000 Reserved Reserved 000330H PCNH12 [R/W] 0000000 - PCNL12 [R/W] 000000 - 0 PCSR13 [W] XXXXXXXX XXXXXXXX PCNH13 [R/W] 0000000 - PCNL13 [R/W] 000000 - 0 PCSR14 [W] XXXXXXXX XXXXXXXX PCNH14 [R/W] 0000000 - PCNL14 [R/W] 000000 - 0 PCSR15 [W] XXXXXXXX XXXXXXXX PCNH15 [R/W] 0000000 - PCNL15 [R/W] 000000 - 0 Reserved PPG 12 PPG 13 PPG 14 PPG 15 Reserved Reserved Reserved PPG Control 12 to 15 Reserved PCSR12 [W] XXXXXXXX XXXXXXXX ROMS [R] 11111111 01000011 Up/Down Counter 0 to 1 ROM Select Register Reserved 53 MB91460H Series Address Register +0 +1 Block +2 +3 0003F0H BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4H BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8H BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FCH BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000400H to 00043CH Reserved 000440H ICR00 [R/W] ---11111 ICR01 [R/W] ---11111 ICR02 [R/W] ---11111 ICR03 [R/W] ---11111 000444H ICR04 [R/W] ---11111 ICR05 [R/W] ---11111 ICR06 [R/W] ---11111 ICR07 [R/W] ---11111 000448H ICR08 [R/W] ---11111 ICR09 [R/W] ---11111 ICR10 [R/W] ---11111 ICR11 [R/W] ---11111 00044CH ICR12 [R/W] ---11111 ICR13 [R/W] ---11111 ICR14 [R/W] ---11111 ICR15 [R/W] ---11111 000450H ICR16 [R/W] ---11111 ICR17 [R/W] ---11111 ICR18 [R/W] ---11111 ICR19 [R/W] ---11111 000454H ICR20 [R/W] ---11111 ICR21 [R/W] ---11111 ICR22 [R/W] ---11111 ICR23 [R/W] ---11111 000458H ICR24 [R/W] ---11111 ICR25 [R/W] ---11111 ICR26 [R/W] ---11111 ICR27 [R/W] ---11111 00045CH ICR28 [R/W] ---11111 ICR29 [R/W] ---11111 ICR30 [R/W] ---11111 ICR31 [R/W] ---11111 000460H ICR32 [R/W] ---11111 ICR33 [R/W] ---11111 ICR34[R/W] ---11111 ICR35 [R/W] ---11111 000464H ICR36 [R/W] ---11111 ICR37 [R/W] ---11111 ICR38 [R/W] ---11111 ICR39 [R/W] ---11111 000468H ICR40 [R/W] ---11111 ICR41 [R/W] ---11111 ICR42 [R/W] ---11111 ICR43 [R/W] ---11111 00046CH ICR44 [R/W] ---11111 ICR45 [R/W] ---11111 ICR46 [R/W] ---11111 ICR47 [R/W] ---11111 000470H ICR48 [R/W] ---11111 ICR49 [R/W] ---11111 ICR50 [R/W] ---11111 ICR51 [R/W] ---11111 000474H ICR52 [R/W] ---11111 ICR53 [R/W] ---11111 ICR54 [R/W] ---11111 ICR55 [R/W] ---11111 000478H ICR56 [R/W] ---11111 ICR57 [R/W] ---11111 ICR58 [R/W] ---11111 ICR59 [R/W] ---11111 54 Bit Search Module Interrupt Controller DS07-16616-1E MB91460H Series Address Register Block +0 +1 +2 +3 00047CH ICR60 [R/W] ---11111 ICR61 [R/W] ---11111 ICR62 [R/W] ---11111 ICR63 [R/W] ---11111 000480H RSRR [R/W] 10000000 STCR [R/W] 00110011 TBCR [R/W] 00XXXX00 CTBR [W] XXXXXXXX 000484H CLKR [R/W] - - - - 0000 WPR [W] XXXXXXXX DIVR0 [R/W] 00000011 DIVR1 [R/W] 00000000 Reserved 000488H PLLDIVN [R/W] - - 000000 Interrupt Controller Clock Control Reserved 00048CH PLLDIVM [R/W] - - - - 0000 PLLDIVG [R/W] - - - - 0000 PLLMULG [R/W] 00000000 000490H PLLCTRL [R/W] - - - - 0000 000494H OSCC1 [R/W] - - - - - 010 000498H PORTEN [R/W] - - - - - - 00 0004A0H Reserved 0004A4H Reserved 0004A8H WTHR [R/W] - - - 00000 WTMR [R/W] - - 000000 WTSR [R/W] - - 000000 Reserved 0004ACH CSVTR [R/W] - - - 00010 CSVCR [R/W] - 011100 CSCFG [R/W] 0X000000 CMCFG [R/W] 00000000 PLL Interface Reserved OSCS1 [R/W] 00001111 OSCC2 [R/W] - - - - - 010 OSCS2 [R/W] 00001111 Port Input Enable Control Reserved WTCER [R/W] - - - - - - 00 Main/Sub Oscillator Control (Reserved) WTCR [R/W] 00000000 000 - 00 - 0 WTBR [R/W] - - - XXXXX XXXXXXXX XXXXXXXX 0004B0H CUCR [R/W] - - - - - - - - - - - 0 - - 00 CUTD [R/W] 10000000 00000000 0004B4H CUTR1 [R] - - - - - - - - 00000000 CUTR2 [R] 00000000 00000000 0004B8H CMPR [R/W] - - 000010 11111101 0004BCH CMT1 [R/W] 00000000 1 - - - 0000 CMCR [R/W] - 001 - - 00 Reserved CMT2 [R/W] - - 000000 - - 000000 Real Time Clock (Watch Timer) ClockSupervisor /Selector/ Monitor Calibration of Sub Clock Clock Modulator 0004C0H CANPRE [R/W] 0 - - - 0000 CANCKD [R/W] - - 000000 0004C4H LVSEL [R/W] 00000111 LVDET [R/W] 00000 - 00 HWWDE [R/W] - - - - - - 00 HWWD [R/W,W] 00011000 Low Voltage Detection/ Hardware Watchdog 0004C8H OSCRH [R/W] 000 - - 001 OSCRL [R/W] - - - - - 000 WPCRH [R/W] 000 - - 001 WPCRL [R/W] - - - - - - 00 Main-/Sub-Oscillation Stabilisation Timer DS07-16616-1E Reserved CAN Clock Control 55 MB91460H Series Address Register +0 0004CCH OSCCR [R/W] - - - - - - 00 Block +1 +2 +3 Reserved REGSEL [R/W] - - 000110 REGCTR [R/W] - - - 0 - - 00 0004D0H to 00063CH Reserved Reserved 000640H ASR0 [R/W] 00000000 00000000 ACR0 [R/W] 1111**00 00000000*2 000644H ASR1 [R/W] XXXXXXXX XXXXXXXX ACR1 [R/W] XXXXXXXX XXXXXXXX 000648H ASR2 [R/W] XXXXXXXX XXXXXXXX ACR2 [R/W] XXXXXXXX XXXXXXXX 00064CH ASR3 [R/W] XXXXXXXX XXXXXXXX ACR3 [R/W] XXXXXXXX XXXXXXXX 000650H ASR4 [R/W] XXXXXXXX XXXXXXXX ACR4 [R/W] XXXXXXXX XXXXXXXX 000654H ASR5 [R/W] XXXXXXXX XXXXXXXX ACR5 [R/W] XXXXXXXX XXXXXXXX 000658H ASR6 [R/W] XXXXXXXX XXXXXXXX ACR6 [R/W] XXXXXXXX XXXXXXXX 00065CH ASR7 [R/W] XXXXXXXX XXXXXXXX ACR7 [R/W] XXXXXXXX XXXXXXXX 000660H AWR0 [R/W] 01111111 11111*11 AWR1 [R/W] XXXXXXXX XXXXXXXX 000664H AWR2 [R/W] XXXXXXXX XXXXXXXX AWR3 [R/W] XXXXXXXX XXXXXXXX 000668H AWR4 [R/W] XXXXXXXX XXXXXXXX AWR5 [R/W] XXXXXXXX XXXXXXXX 00066CH AWR6 [R/W] XXXXXXXX XXXXXXXX AWR7 [R/W] XXXXXXXX XXXXXXXX 000670H MCRA [R/W] XXXXXXXX 000674H 000678H MCRB [R/W] XXXXXXXX External Bus Unit Reserved Reserved IOWR0 [R/W] XXXXXXXX IOWR1 [R/W] XXXXXXXX IOWR2 [R/W] XXXXXXXX IOWR3 [R/W] XXXXXXXX Reserved 00067CH 000680H CSER [R/W] 00000001 CHER [R/W] 11111111 000684H RCRH [R/W] 00XXXXXX RCRL [R/W] XXXX0XXX 56 Main- Oscillation Standby Control / Main/Sub Regulator Control Reserved TCR [R/W] 0000**** *3 Reserved DS07-16616-1E MB91460H Series Address Register +0 +1 000688H to 0007F8H Block +2 +3 Reserved 0007FCH Reserved MODR [W] XXXXXXXX 000800H to 000CFCH External Bus Unit Reserved Mode Register Reserved Reserved 000D00H PDRD00 [R] XXXXXXXX PDRD01 [R] XXXXXXXX 000D04H Reserved PDRD05 [R] - - XXXXXX PDRD06 [R] XXXXXXXX PDRD07 [R] XXXXXXXX 000D08H PDRD08 [R] X - - X - - -X PDRD09 [R] - - - - - - XX PDRD10 [R] -------X Reserved PDRD14 [R] XXXXXXXX PDRD15 [R] XXXXXXXX Reserved 000D0CH Reserved 000D10H PDRD16 [R] XXXXXXXX PDRD17 [R] XXXXXXXX PDRD18 [R] - XXX - XXX PDRD19 [R] - XXX - XXX 000D14H PDRD20 [R] - XXX - XXX PDRD21 [R] -------X PDRD22 [R] XXXXXXXX PDRD23 [R] XXXXXXXX 000D18H PDRD24 [R] XXXXXXXX Reserved PDRD26 [R] XXXXXXXX PDRD27 [R] XXXXXXXX 000D1CH PDRD28 [R] XXXXXXXX PDRD29 [R] XXXXXXXX 000D20H to 000D3CH R-bus Port Data Direct Read Register Reserved Reserved 000D40H DDR00 [R/W] 00000000 DDR01 [R/W] 00000000 000D44H Reserved DDR05 [R/W] - - 000000 DDR06 [R/W] 00000000 DDR07 [R/W] 00000000 000D48H DDR08 [R/W] 0 - - 0 - - -0 DDR09 [R/W] - - - - - - 00 DDR10 [R/W] - - - - - - -0 Reserved DDR14 [R/W] 00000000 DDR15 [R/W] 00000000 Reserved 000D4CH Reserved 000D50H DDR16 [R/W] 00000000 DDR17 [R/W] 00000000 DDR18 [R/W] - 000 - 000 DDR19 [R/W] - 000 - 000 000D54H DDR20 [R/W] - 000 - 000 DDR21 [R/W] - - - - - - 00 DDR22 [R/W] 00000000 DDR23 [R/W] 00000000 000D58H DDR24 [R/W] 00000000 Reserved DDR26 [R/W] 00000000 DDR27 [R/W] 00000000 000D5CH DDR28 [R/W] 00000000 DDR29 [R/W] 00000000 DS07-16616-1E R-bus Port Direction Register Reserved 57 MB91460H Series Address Register +0 +1 000D60H to 000D7CH Block +2 +3 Reserved Reserved 000D80H PFR00 [R/W] 11111111 PFR01 [R/W] 11111111 000D84H Reserved PFR05 [R/W] - - 111111 PFR06 [R/W] 11111111 PFR07 [R/W] 11111111 000D88H PFR08 [R/W] 1 - - 1 - - 11 PFR09 [R/W] - - - - - - 11 PFR10 [R/W] - - - - - - -1 Reserved PFR14 [R/W] 00000000 PFR15 [R/W] 00000000 000D8CH Reserved Reserved 000D90H PFR16 [R/W] 00000000 PFR17 [R/W] 00000000 PFR18 [R/W] - 000 - 000 PFR19 [R/W] - 000 - 000 000D94H PFR20 [R/W] - 000 - 000 PFR21 [R/W] - - - - - - 00 PFR22 [R/W] 0000-0-0 PFR23 [R/W] -0000000 000D98H PFR24 [R/W] 00000000 Reserved PFR26 [R/W] 00000000 PFR27 [R/W] 00000000 000D9CH PFR28 [R/W] 00000000 PFR29 [R/W] 00000000 000DA0H to 000DC4H Reserved Reserved 000DC8H Reserved EPFR10 [R/W] -------0 Reserved 000DCCH Reserved EPFR14 [R/W] 00000000 EPFR15 [R/W] 00000000 EPFR18 [R/W] - 000 - 000 EPFR19 [R/W] - 0- - - 0- - 000DD0H EPFR16 [R/W] 0 - 00 - - - - Reserved 000DD4H EPFR20 [R/W] - 000 - 000 EPFR21 [R/W] ---- ---- 000DD8H 000DDCH to 000DFCH 58 R-bus Port Function Register Reserved R-bus Port Extra Function Register Reserved EPFR26 [R/W] 00000000 Reserved EPFR27 [R/W] 00000000 Reserved DS07-16616-1E MB91460H Series Address Register Block +0 +1 +2 000E00H PODR00 [R/W] 00000000 PODR01 [R/W] 00000000 000E04H Reserved PODR05 [R/W] - - 000000 PODR06 [R/W] 00000000 PODR07 [R/W] 00000000 000E08H PODR08 [R/W] 0--0---0 PODR09 [R/W] - - - - - - 00 PODR10 [R/W] -------0 Reserved PODR14 [R/W] 00000000 PODR15 [R/W] 00000000 Reserved 000E0CH +3 Reserved 000E10H PODR16 [R/W] 00000000 PODR17 [R/W] 00000000 PODR18 [R/W] - 000 - 000 PODR19 [R/W] - 000 - 000 000E14H PODR20 [R/W] - 000 - 000 PODR21 [R/W] - - - - - - 00 PODR22 [R/W] 00000000 PODR23 [R/W] 00000000 000E18H PODR24 [R/W] 00000000 Reserved PODR26 [R/W] 00000000 PODR27 [R/W] 00000000 000E1CH PODR28 [R/W] 00000000 PODR29 [R/W] 00000000 000E20H to 000E3CH Reserved Reserved Reserved 000E40H PILR00 [R/W] 00000000 PILR01 [R/W] 00000000 000E44H Reserved PILR05 [R/W] - - 000000 PILR06 [R/W] 00000000 PILR07 [R/W] 00000000 000E48H PILR08 [R/W] 0--0---0 PILR09 [R/W] - - - - - - 00 PILR10 [R/W] -------0 Reserved PILR14 [R/W] 00000000 PILR15 [R/W] 00000000 Reserved 000E4CH Reserved 000E50H PILR16 [R/W] 00000000 PILR17 [R/W] 00000000 PILR18 [R/W] - - - - - 000 PILR19 [R/W] - 000 - 000 000E54H PILR20 [R/W] - 000 - 000 PILR21 [R/W] - - - - - - 00 PILR22 [R/W] 00000000 PILR23 [R/W] 00000000 000E58H PILR24 [R/W] 00000000 Reserved PILR26 [R/W] 00000000 PILR27 [R/W] 00000000 000E5CH PILR28 [R/W] 00000000 PILR29 [R/W] 00000000 000E60H to 000E7CH DS07-16616-1E R-bus Port Output Drive Select Register Reserved R-bus Port Input Level Select Register Reserved Reserved 59 MB91460H Series Address Register Block +0 +1 000E80H EPILR00 [R/W] 00000000 EPILR01 [R/W] 00000000 000E84H Reserved EPILR05 [R/W] - - 000000 EPILR06 [R/W] 00000000 EPILR07 [R/W] 00000000 000E88H EPILR08 [R/W] 0 - - 0- - - 0 EPILR09 [R/W] - - - - - - 00 EPILR10 [R/W] -------0 Reserved EPILR14 [R/W] 00000000 EPILR15 [R/W] 00000000 000E8CH +2 Reserved +3 Reserved 000E90H EPILR16 [R/W] 00000000 EPILR17 [R/W] 00000000 EPILR18 [R/W] - - - - - 000 EPILR19 [R/W] - 000 - 000 000E94H EPILR20 [R/W] - 000 - 000 EPILR21 [R/W] - - - - - - 00 EPILR22 [R/W] 00000000 EPILR23 [R/W] 00000000 000E98H EPILR24 [R/W] 00000000 Reserved EPILR26 [R/W] 00000000 EPILR27 [R/W] 00000000 000E9CH EPILR28 [R/W] 00000000 EPILR29 [R/W] 00000000 000EA0H to 000EBCH Reserved Reserved Reserved 000EC0H PPER00 [R/W] 00000000 PPER01 [R/W] 00000000 000EC4H Reserved PPER05 [R/W] - - 000000 PPER06 [R/W] 00000000 PPER07 [R/W] 00000000 000EC8H PPER08 [R/W] 0--0---0 PPER09 [R/W] - - - - - - 00 PPER10 [R/W] -------0 Reserved PPER14 [R/W] 00000000 PPER15 [R/W] 00000000 000ECCH Reserved Reserved 000ED0H PPER16 [R/W] 00000000 PPER17 [R/W] 00000000 PPER18 [R/W] - 000 - 000 PPER19 [R/W] - 000 - 000 000ED4H PPER20 [R/W] - 000 - 000 PPER21 [R/W] - - - - - - 00 PPER22 [R/W] 00000000 PPER23 [R/W] 00000000 000ED8H PPER24 [R/W] 00000000 Reserved PPER26 [R/W] 00000000 PPER27 [R/W] 00000000 000EDCH PPER28 [R/W] 00000000 PPER29 [R/W] 00000000 000EE0H to 000EFCH 60 R-bus Port Extra Input Level Select Register Reserved R-bus Port Pull-Up/Down Enable Register Reserved Reserved DS07-16616-1E MB91460H Series Address Register Block +0 +1 +2 000F00H PPCR00 [R/W] 11111111 PPCR01 [R/W] 11111111 000F04H Reserved PPCR05 [R/W] - - 111111 PPCR06 [R/W] 11111111 PPCR07 [R/W] 11111111 000F08H PPCR08 [R/W] 1--1---1 PPCR09 [R/W] - - - - - - 11 PPCR10 [R/W] -------1 Reserved PPCR14 [R/W] 00000000 PPCR15 [R/W] 11111111 Reserved 000F0CH +3 Reserved 000F10H PPCR16 [R/W] 00000000 PPCR17 [R/W] 00000000 PPCR18 [R/W] - 111- 111 PPCR19 [R/W] - 111- 111 000F14H PPCR20 [R/W] - 111- 111 PPCR21 [R/W] - - - - - - 11 PPCR22 [R/W] 11111111 PPCR23 [R/W] 11111111 000F18H PPCR24 [R/W] 11111111 Reserved PPCR26 [R/W] 11111111 PPCR27 [R/W] 11111111 000F1CH PPCR28 [R/W] 11111111 PPCR29 [R/W] 11111111 Reserved 000F20H to 000F3CH Reserved 001000H DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001004H DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001008H DMASA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00100CH DMADA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001010H DMASA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001014H DMADA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001018H DMASA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00101CH DMADA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001020H DMASA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001024H DMADA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001028H to 003FFCH Reserved DS07-16616-1E R-bus Port Pull-Up/Down Control Register Reserved DMAC Reserved 61 MB91460H Series Address Register +0 002000H to 006FFCH 007000H 007004H +1 Block +2 +3 Flash-cache size is 8 Kbytes : 004000H to 005FFCH FMCS [R/W] 01101000 FMCR [R/W] - - - - 0000 FMWT [R/W] 11111111 11111111 FCHCR [R/W] - - - - - - 00 10000011 Reserved FMPS [R/W] - - - - - 000 Flash-cache / I-RAM area Flash Memory/ I-Cache Control Register 007008H FMAC [R] 00000000 00000000 00000000 00000000 00700CH FCHA0 [R/W] - - - - - - - - - - 000000 00000000 00000000 007010H FCHA1 [R/W] - - - - - - - - - - 000000 00000000 00000000 007014H to 007FFCH Reserved Reserved 008000H to 00BFFCH Boot-ROM size is 4 Kbytes : 00B000H to 00BFFCH (instruction access is 1 wait cycle, data access is 1 wait cycle) Boot ROM area 00C000H CTRLR0 [R/W] 00000000 00000001 STATR0 [R/W] 00000000 00000000 00C004H ERRCNT0 [R] 00000000 00000000 BTR0 [R/W] 00100011 00000001 00C008H INTR0 [R] 00000000 00000000 TESTR0 [R/W] 00000000 X0000000 00C00CH BRPE0 [R/W] 00000000 00000000 CBSYNC0 62 I-Cache Non-cacheable area setting Register CAN 0 Control Register DS07-16616-1E MB91460H Series Address Register +0 +1 Block +2 +3 00C010H IF1CREQ0 [R/W] 00000000 00000001 IF1CMSK0 [R/W] 00000000 00000000 00C014H IF1MSK20 [R/W] 11111111 11111111 IF1MSK10 [R/W] 11111111 11111111 00C018H IF1ARB20 [R/W] 00000000 00000000 IF1ARB10 [R/W] 00000000 00000000 00C01CH IF1MCTR0 [R/W] 00000000 00000000 Reserved 00C020H IF1DTA10 [R/W] 00000000 00000000 IF1DTA20 [R/W] 00000000 00000000 00C024H IF1DTB10 [R/W] 00000000 00000000 IF1DTB20 [R/W] 00000000 00000000 00C028H to 00C02CH Reserved 00C030H IF1DTA20 [R/W] 00000000 00000000 IF1DTA10 [R/W] 00000000 00000000 00C034H IF1DTB20 [R/W] 00000000 00000000 IF1DTB10 [R/W] 00000000 00000000 00C038H to 00C03CH Reserved 00C040H IF2CREQ0 [R/W] 00000000 00000001 IF2CMSK0 [R/W] 00000000 00000000 00C044H IF2MSK20 [R/W] 11111111 11111111 IF2MSK10 [R/W] 11111111 11111111 00C048H IF2ARB20 [R/W] 00000000 00000000 IF2ARB10 [R/W] 00000000 00000000 DS07-16616-1E CAN 0 IF 1 Register CAN 0 IF 2 Register 63 MB91460H Series Address Register +0 +1 Block +2 +3 00C04CH IF2MCTR0 [R/W] 00000000 00000000 Reserved 00C050H IF2DTA10 [R/W] 00000000 00000000 IF2DTA20 [R/W] 00000000 00000000 00C054H IF2DTB10 [R/W] 00000000 00000000 IF2DTB20 [R/W] 00000000 00000000 00C058H to 00C05CH Reserved 00C060H IF2DTA20 [R/W] 00000000 00000000 IF2DTA10 [R/W] 00000000 00000000 00C064H IF2DTB20 [R/W] 00000000 00000000 IF2DTB10 [R/W] 00000000 00000000 00C068H to 00C07CH Reserved 00C080H TREQR20 [R] 00000000 00000000 TREQR10 [R] 00000000 00000000 00C084H to 00C08CH Reserved Reserved 00C090H NEWDT20 [R] 00000000 00000000 NEWDT10 [R] 00000000 00000000 00C094H to 00C09CH Reserved Reserved 00C0A0H INTPND20 [R] 00000000 00000000 INTPND10 [R] 00000000 00000000 00C0A4H to 00C0ACH Reserved Reserved 00C0B0H MSGVAL20 [R] 00000000 00000000 MSGVAL10 [R] 00000000 00000000 00C0B4H to 00C0FCH Reserved Reserved 00C100H to 00EFFCH 64 Reserved CAN 0 Status Flags Reserved DS07-16616-1E MB91460H Series Address Register +0 +1 Block +2 00F000H BCTRL [R/W] - - - - - - - - - - - - - - - - 11111100 00000000 00F004H BSTAT [R/W] - - - - - - - - - - - - - 000 00000000 10 - - 000000 00F008H BIAC [R] - - - - - - - - - - - - - - - - 00000000 00000000 00F00CH BOAC [R] - - - - - - - - - - - - - - - - 00000000 00000000 00F010H BIRQ [R/W] - - - - - - - - - - - - - - - - 00000000 00000000 00F014H to 00F01CH Reserved 00F020H BCR0 [R/W] - - - - - - - - 00000000 00000000 00000000 00F024H BCR1 [R/W] - - - - - - - - 00000000 00000000 00000000 00F028H BCR2 [R/W] - - - - - - - - 00000000 00000000 00000000 00F02CH BCR3 [R/W] - - - - - - - - 00000000 00000000 00000000 00F030H to 00F07CH Reserved DS07-16616-1E +3 EDSU / MPU Reserved 65 MB91460H Series Address Register +0 +1 Block +2 +3 00F080H BAD0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F084H BAD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F088H BAD2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F08CH BAD3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F090H BAD4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F094H BAD5 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F098H BAD6 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F09CH BAD7 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0A0H BAD8 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0A4H BAD9 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0A8H BAD10 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0ACH BAD11 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0B0H BAD12 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0B4H BAD13 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0B8H BAD14 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0BCH BAD15 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0C0H to 01FFFCH Reserved EDSU / MPU 020000H to 02FFFCH D-RAM size is 16 Kbytes : 02C000H - 02FFFCH (data access is 0 wait cycles) D-RAM area 030000H to 03FFFCH ID-RAM size is 16 Kbytes : 030000H - 033FFCH (instruction access is 0 wait cycles, data access is 1 wait cycle) ID-RAM area EDSU / MPU *1 : depends on the number of available CAN channels 66 DS07-16616-1E MB91460H Series *2 : ACR0 [11 : 10] depends on Mode vector fetch information on bus width *3 : TCR [3 : 0] INIT value = 0000, keeps value after RST DS07-16616-1E 67 MB91460H Series 2. Flash memory and external bus area 2.1. MB91F464HB 32bit read 16bit read/write Address dat[31:0] dat[31:16] dat[31:0] dat[15:0] dat[31:16] dat[15:0] Register +0 +1 +2 +3 +4 +5 +6 +7 Block 040000H to 05FFF8H Reserved Reserved ROMS0 060000H to 07FFF8H Reserved Reserved ROMS1 080000H to 09FFF8H Reserved Reserved ROMS2 0A0000H to 0BFFF8H SA14 (64KB) SA15 (64KB) ROMS3 0C0000H to 0DFFF8H SA16 (64KB) SA17 (64KB) ROMS4 0E0000H to 0FFFF0H SA18 (64KB) SA19 (64KB) 0FFFF8H FMV [R] 06 00 00 00H FRV [R] 00 00 BF F8H 100000H to 11FFF8H External Bus Area 120000H to 13FFF8H 140000H to 143FF8H ROMS6 External Bus Area 144000H to 17FF8H 148000H to 14BFF8H SA4 (8KB) SA5 (8KB) 14C000H to 14FFF8H SA6 (8KB) SA7 (8KB) 150000H to17FFF8H ROMS5 ROMS7 Reserved (Continued) 68 DS07-16616-1E MB91460H Series (Continued) 32bit read 16bit read/write Address dat[31:0] dat[31:16] dat[31:0] dat[15:0] dat[31:16] dat[15:0] Register +0 +1 +2 +3 +4 +5 +6 +7 Block 180000H to 1BFFF8H ROMS8 1C0000H to 1FFFF8H ROMS9 200000H to 27FFF8H ROMS10 280000H to 2FFFF8H ROMS11 300000H to 37FFF8H External Bus Area ROMS12 380000H to 3FFFF8H ROMS13 400000H to 47FFF8H ROMS14 480000H to 4FFFF8H ROMS15 Note: Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown above will be read. DS07-16616-1E 69 MB91460H Series ■ INTERRUPT VECTOR TABLE Interrupt number Interrupt Interrupt level *1 Interrupt vector *2 DMA Resource number Decimal Hexadecimal Setting Register Register address Offset Default vector address Reset 0 00 — — 3FCH 000FFFFCH — Mode vector 1 01 — — 3F8H 000FFFF8H — System reserved 2 02 — — 3F4H 000FFFF4H — System reserved 3 03 — — 3F0H 000FFFF0H — System reserved 4 04 — — 3ECH 000FFFECH — CPU supervisor mode (INT #5 instruction) *5 5 05 — — 3E8H 000FFFE8H — Memory Protection exception *5 6 06 — — 3E4H 000FFFE4H — System reserved 7 07 — — 3E0H 000FFFE0H — System reserved 8 08 — — 3DCH 000FFFDCH — System reserved 9 09 — — 3D8H 000FFFD8H — System reserved 10 0A — — 3D4H 000FFFD4H — System reserved 11 0B — — 3D0H 000FFFD0H — System reserved 12 0C — — 3CCH 000FFFCCH — System reserved 13 0D — — 3C8H 000FFFC8H — Undefined instruction exception 14 0E — — 3C4H 000FFFC4H — NMI request 15 0F 3C0H 000FFFC0H — External Interrupt 0 16 10 3BCH 000FFFBCH 0, 16 External Interrupt 1 17 11 3B8H 000FFFB8H 1, 17 External Interrupt 2 18 12 3B4H 000FFFB4H 2, 18 External Interrupt 3 19 13 3B0H 000FFFB0H 3, 19 External Interrupt 4 20 14 3ACH 000FFFACH 20 External Interrupt 5 21 15 3A8H 000FFFA8H 21 External Interrupt 6 22 16 3A4H 000FFFA4H 22 External Interrupt 7 23 17 3A0H 000FFFA0H 23 External Interrupt 8 24 18 39CH 000FFF9CH — External Interrupt 9 25 19 398H 000FFF98H — External Interrupt 10 26 1A 394H 000FFF94H — External Interrupt 11 27 1B 390H 000FFF90H — External Interrupt 12 28 1C 38CH 000FFF8CH — External Interrupt 13 29 1D 388H 000FFF88H — External Interrupt 14 30 1E 384H 000FFF84H — External Interrupt 15 31 1F 380H 000FFF80H — 70 FH fixed ICR00 440H ICR01 441H ICR02 442H ICR03 443H ICR04 444H ICR05 445H ICR06 446H ICR07 447H DS07-16616-1E MB91460H Series Interrupt number Interrupt Decimal Hexadecimal Reload Timer 0 32 20 Reload Timer 1 33 21 Reload Timer 2 34 22 Reload Timer 3 35 23 Reload Timer 4 36 24 Reload Timer 5 37 25 Reload Timer 6 38 26 Reload Timer 7 39 27 Free Run Timer 0 40 28 Free Run Timer 1 41 29 Free Run Timer 2 42 2A Free Run Timer 3 43 2B Free Run Timer 4 44 2C Free Run Timer 5 45 2D Free Run Timer 6 46 2E Free Run Timer 7 47 2F CAN 0 48 30 Reserved 49 31 Reserved 50 32 Reserved 51 33 Reserved 52 34 Reserved 53 35 LIN-USART 0 RX 54 36 LIN-USART 0 TX 55 37 Reserved 56 38 Reserved 57 39 LIN-USART 2 RX 58 3A LIN-USART 2 TX 59 3B LIN-USART 3 RX 60 3C LIN-USART 3 TX 61 3D System Reserved 62 3E 63 3F 64 40 65 41 Delayed Interrupt System Reserved *4 System Reserved *4 DS07-16616-1E Interrupt level *1 Setting Register Register address ICR08 448H ICR09 449H ICR10 44AH ICR11 44BH ICR12 44CH ICR13 44DH ICR14 44EH ICR15 44FH ICR16 450H ICR17 451H ICR18 452H ICR19 453H ICR20 454H ICR21 455H ICR22 456H ICR23 *3 457H ICR24 458H Interrupt vector *2 DMA Resource number Offset Default vector address 37CH 000FFF7CH 4, 32 378H 000FFF78H 5, 33 374H 000FFF74H 34 370H 000FFF70H 35 36CH 000FFF6CH 36 368H 000FFF68H 37 364H 000FFF64H 38 360H 000FFF60H 39 35CH 000FFF5CH 40 358H 000FFF58H 41 354H 000FFF54H 42 350H 000FFF50H 43 34CH 000FFF4CH 44 348H 000FFF48H 45 344H 000FFF44H 46 340H 000FFF40H 47 33CH 000FFF3CH — 338H 000FFF38H — 334H 000FFF34H — 330H 000FFF30H — 32CH 000FFF2CH — 328H 000FFF28H — 324H 000FFF24H 6, 48 320H 000FFF20H 7, 49 31CH 000FFF1CH 8, 50 318H 000FFF18H 9, 51 314H 000FFF14H 52 310H 000FFF10H 53 30CH 000FFF0CH 54 308H 000FFF08H 55 304H 000FFF04H — 300H 000FFF00H — 2FCH 000FFEFCH — 2F8H 000FFEF8H — 71 MB91460H Series Interrupt number Interrupt Decimal Hexadecimal LIN-USART (FIFO) 4 RX 66 42 LIN-USART (FIFO) 4 TX 67 43 LIN-USART (FIFO) 5 RX 68 44 LIN-USART (FIFO) 5 TX 69 45 LIN-USART (FIFO) 6 RX 70 46 LIN-USART (FIFO) 6 TX 71 47 LIN-USART (FIFO) 7 RX 72 48 LIN-USART (FIFO) 7 TX 73 49 IC0 74 4A I2C 1 75 4B Reserved 76 4C Reserved 77 4D Reserved 78 4E Reserved 79 4F Reserved 80 50 Reserved 81 51 Reserved 82 52 Reserved 83 53 Reserved 84 54 Reserved 85 55 Reserved 86 56 Reserved 87 57 Reserved 88 58 Reserved 89 59 Reserved 90 5A Reserved 91 5B Input Capture 0 92 5C Input Capture 1 93 5D Input Capture 2 94 5E Input Capture 3 95 5F Input Capture 4 96 60 Input Capture 5 97 61 Input Capture 6 98 62 Input Capture 7 99 63 2 72 Interrupt level *1 Setting Register Register address ICR25 459H ICR26 45AH ICR27 45BH ICR28 45CH ICR29 45DH ICR30 45EH ICR31 45FH ICR32 460H ICR33 461H ICR34 462H ICR35 463H ICR36 464H ICR37 465H ICR38 466H ICR39 467H ICR40 468H ICR41 469H Interrupt vector *2 DMA Resource number Offset Default vector address 2F4H 000FFEF4H 10, 56 2F0H 000FFEF0H 11, 57 2ECH 000FFEECH 12, 58 2E8H 000FFEE8H 13, 59 2E4H 000FFEE4H 60 2E0H 000FFEE0H 61 2DCH 000FFEDCH 62 2D8H 000FFED8H 63 2D4H 000FFED4H — 2D0H 000FFED0H — 2CCH 000FFECCH 64 2C8H 000FFEC8H 65 2C4H 000FFEC4H 66 2C0H 000FFEC0H 67 2BCH 000FFEBCH 68 2B8H 000FFEB8H 69 2B4H 000FFEB4H 70 2B0H 000FFEB0H 71 2ACH 000FFEACH 72 2A8H 000FFEA8H 73 2A4H 000FFEA4H 74 2A0H 000FFEA0H 75 29CH 000FFE9CH 76 298H 000FFE98H 77 294H 000FFE94H 78 290H 000FFE90H 79 28CH 000FFE8CH 80 288H 000FFE88H 81 284H 000FFE84H 82 280H 000FFE80H 83 27CH 000FFE7CH 84 278H 000FFE78H 85 274H 000FFE74H 86 270H 000FFE70H 87 DS07-16616-1E MB91460H Series Interrupt number Interrupt Decimal Hexadecimal Output Compare 0 100 64 Output Compare 1 101 65 Output Compare 2 102 66 Output Compare 3 103 67 Output Compare 4 104 68 Output Compare 5 105 69 Output Compare 6 106 6A Output Compare 7 107 6B Sound Generator 108 6C Reserved 109 6D System Reserved 110 6E System Reserved 111 6F PPG 0 112 70 PPG 1 113 71 PPG 2 114 72 PPG 3 115 73 PPG 4 116 74 PPG 5 117 75 PPG 6 118 76 PPG 7 119 77 PPG 8 120 78 PPG 9 121 79 PPG 10 122 7A PPG 11 123 7B PPG 12 124 7C PPG 13 125 7D PPG 14 126 7E PPG 15 127 7F Up/Down Counter 0 128 80 Up/Down Counter 1 129 81 Reserved 130 82 Reserved 131 83 Real Time Clock 132 84 Calibration Unit 133 85 DS07-16616-1E Interrupt level *1 Setting Register Register address ICR42 46AH ICR43 46BH ICR44 46CH ICR45 46DH ICR46 46EH ICR47 *3 46FH ICR48 470H ICR49 471H ICR50 472H ICR51 473H ICR52 474H ICR53 475H ICR54 476H ICR55 477H ICR56 478H ICR57 479H ICR58 47AH Interrupt vector *2 DMA Resource number Offset Default vector address 26CH 000FFE6CH 88 268H 000FFE68H 89 264H 000FFE64H 90 260H 000FFE60H 91 25CH 000FFE5CH 92 258H 000FFE58H 93 254H 000FFE54H 94 250H 000FFE50H 95 24CH 000FFE4CH — 248H 000FFE48H — 244H 000FFE44H — 240H 000FFE40H — 23CH 000FFE3CH 15, 96 238H 000FFE38H 97 234H 000FFE34H 98 230H 000FFE30H 99 22CH 000FFE2CH 100 228H 000FFE28H 101 224H 000FFE24H 102 220H 000FFE20H 103 21CH 000FFE1CH 104 218H 000FFE18H 105 214H 000FFE14H 106 210H 000FFE10H 107 20CH 000FFE0CH 108 208H 000FFE08H 109 204H 000FFE04H 110 200H 000FFE00H 111 1FCH 000FFDFCH — 1F8H 000FFDF8H — 1F4H 000FFDF4H — 1F0H 000FFDF0H — 1ECH 000FFDECH — 1E8H 000FFDE8H — 73 MB91460H Series Interrupt number Interrupt Decimal Hexadecimal A/D Converter 0 134 86 System reserved 135 87 Alarm Comparator 0 136 88 Reserved 137 89 Low Voltage Detection 138 8A Reserved 139 8B Time base Overflow 140 8C PLL Clock Gear 141 8D DMA Controller 142 8E Main/Sub OSC stability wait 143 8F Security vector 144 Used by the INT instruction. 145 to 255 Interrupt level *1 Setting Register Register address ICR59 47BH ICR60 47CH ICR61 47DH ICR62 47EH ICR63 47FH 90 — 91 to FF — Interrupt vector *2 DMA Resource number Offset Default vector address 1E4H 000FFDE4H 14, 112 1E0H 000FFDE0H — 1DCH 000FFDDCH — 1D8H 000FFDD8H — 1D4H 000FFDD4H — 1D0H 000FFDD0H — 1CCH 000FFDCCH — 1C8H 000FFDC8H — 1C4H 000FFDC4H — 1C0H 000FFDC0H — — 1BCH 000FFDBCH — — 1B8H to 000H 000FFDB8H to 000FFC00H — *1 : The Interrupt Control Registers (ICRs) are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is provided for each interrupt request. *2 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (TBR) . The TBR specifies the top of the EIT vector table. The addresses listed in the table are for the default TBR value (000FFC00H) . The TBR is initialized to this value by a reset. The TBR is set to 000FFC00H after the internal boot ROM is executed. *3 : ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0]) *4 : Used by REALOS *5 : Memory Protection Unit (MPU) support 74 DS07-16616-1E MB91460H Series ■ RECOMMENDED SETTINGS 1. PLL and Clockgear settings Please note that for MB91F464HB the core base clock frequencies are valid in the 1.8V operation mode of the Main regulator and Flash . Recommended PLL divider and clockgear settings PLL Input (CLK) [MHz] Frequency Parameter Clockgear Parameter PLL Output (X) [MHz] Core Base Clock [MHz] DIVM DIVN DIVG MULG 4 2 25 16 24 200 100 4 2 24 16 24 192 96 4 2 23 16 24 184 92 4 2 22 16 24 176 88 4 2 21 16 20 168 84 4 2 20 16 20 160 80 4 2 19 16 20 152 76 4 2 18 16 20 144 72 4 2 17 16 16 136 68 4 2 16 16 16 128 64 4 2 15 16 16 120 60 4 2 14 16 16 112 56 4 2 13 16 12 104 52 4 2 12 16 12 96 48 4 2 11 16 12 88 44 4 4 10 16 24 160 40 4 4 9 16 24 144 36 4 4 8 16 24 128 32 4 4 7 16 24 112 28 4 6 6 16 24 144 24 4 8 5 16 28 160 20 4 10 4 16 32 160 16 4 12 3 16 32 144 12 DS07-16616-1E Remarks MULG 75 MB91460H Series 2. Clock Modulator settings The following table shows all possible settings for the Clock Modulator in a base clock frequency range from 32MHz up to 88MHz. The Flash access time settings need to be adjusted according to Fmax while the PLL and clockgear settings should be set according to base clock frequency. Clock Modulator settings, frequency range and supported supply voltage 76 Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 1 3 026F 88 79.5 98.5 1 3 026F 84 76.1 93.8 1 3 026F 80 72.6 89.1 1 5 02AE 80 68.7 95.8 2 3 046E 80 68.7 95.8 1 3 026F 76 69.1 84.5 1 5 02AE 76 65.3 90.8 1 7 02ED 76 62 98.1 2 3 046E 76 65.3 90.8 3 3 066D 76 62 98.1 1 3 026F 72 65.5 79.9 1 5 02AE 72 62 85.8 1 7 02ED 72 58.8 92.7 2 3 046E 72 62 85.8 3 3 066D 72 58.8 92.7 1 3 026F 68 62 75.3 1 5 02AE 68 58.7 80.9 1 7 02ED 68 55.7 87.3 1 9 032C 68 53 95 2 3 046E 68 58.7 80.9 2 5 04AC 68 53 95 3 3 066D 68 55.7 87.3 4 3 086C 68 53 95 1 3 026F 64 58.5 70.7 1 5 02AE 64 55.3 75.9 1 7 02ED 64 52.5 82 1 9 032C 64 49.9 89.1 1 11 036B 64 47.6 97.6 2 3 046E 64 55.3 75.9 2 5 04AC 64 49.9 89.1 DS07-16616-1E MB91460H Series Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 3 3 066D 64 52.5 82 4 3 086C 64 49.9 89.1 5 3 0A6B 64 47.6 97.6 1 3 026F 60 54.9 66.1 1 5 02AE 60 51.9 71 1 7 02ED 60 49.3 76.7 1 9 032C 60 46.9 83.3 1 11 036B 60 44.7 91.3 2 3 046E 60 51.9 71 2 5 04AC 60 46.9 83.3 3 3 066D 60 49.3 76.7 4 3 086C 60 46.9 83.3 5 3 0A6B 60 44.7 91.3 1 3 026F 56 51.4 61.6 1 5 02AE 56 48.6 66.1 1 7 02ED 56 46.1 71.4 1 9 032C 56 43.8 77.6 1 11 036B 56 41.8 84.9 1 13 03AA 56 39.9 93.8 2 3 046E 56 48.6 66.1 2 5 04AC 56 43.8 77.6 2 7 04EA 56 39.9 93.8 3 3 066D 56 46.1 71.4 3 5 06AA 56 39.9 93.8 4 3 086C 56 43.8 77.6 5 3 0A6B 56 41.8 84.9 6 3 0C6A 56 39.9 93.8 1 3 026F 52 47.8 57 1 5 02AE 52 45.2 61.2 1 7 02ED 52 42.9 66.1 1 9 032C 52 40.8 71.8 1 11 036B 52 38.8 78.6 1 13 03AA 52 37.1 86.8 1 15 03E9 52 35.5 96.9 2 3 046E 52 45.2 61.2 2 5 04AC 52 40.8 71.8 DS07-16616-1E 77 MB91460H Series 78 Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 2 7 04EA 52 37.1 86.8 3 3 066D 52 42.9 66.1 3 5 06AA 52 37.1 86.8 4 3 086C 52 40.8 71.8 5 3 0A6B 52 38.8 78.6 6 3 0C6A 52 37.1 86.8 7 3 0E69 52 35.5 96.9 1 3 026F 48 44.2 52.5 1 5 02AE 48 41.8 56.4 1 7 02ED 48 39.6 60.9 1 9 032C 48 37.7 66.1 1 11 036B 48 35.9 72.3 1 13 03AA 48 34.3 79.9 1 15 03E9 48 32.8 89.1 2 3 046E 48 41.8 56.4 2 5 04AC 48 37.7 66.1 2 7 04EA 48 34.3 79.9 3 3 066D 48 39.6 60.9 3 5 06AA 48 34.3 79.9 4 3 086C 48 37.7 66.1 5 3 0A6B 48 35.9 72.3 6 3 0C6A 48 34.3 79.9 7 3 0E69 48 32.8 89.1 1 3 026F 44 40.6 48.1 1 5 02AE 44 38.4 51.6 1 7 02ED 44 36.4 55.7 1 9 032C 44 34.6 60.4 1 11 036B 44 33 66.1 1 13 03AA 44 31.5 73 1 15 03E9 44 30.1 81.4 2 3 046E 44 38.4 51.6 2 5 04AC 44 34.6 60.4 2 7 04EA 44 31.5 73 2 9 0528 44 28.9 92.1 3 3 066D 44 36.4 55.7 3 5 06AA 44 31.5 73 DS07-16616-1E MB91460H Series Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 4 3 086C 44 34.6 60.4 4 5 08A8 44 28.9 92.1 5 3 0A6B 44 33 66.1 6 3 0C6A 44 31.5 73 7 3 0E69 44 30.1 81.4 8 3 1068 44 28.9 92.1 1 3 026F 40 37 43.6 1 5 02AE 40 34.9 46.8 1 7 02ED 40 33.1 50.5 1 9 032C 40 31.5 54.8 1 11 036B 40 30 59.9 1 13 03AA 40 28.7 66.1 1 15 03E9 40 27.4 73.7 2 3 046E 40 34.9 46.8 2 5 04AC 40 31.5 54.8 2 7 04EA 40 28.7 66.1 2 9 0528 40 26.3 83.3 3 3 066D 40 33.1 50.5 3 5 06AA 40 28.7 66.1 3 7 06E7 40 25.3 95.8 4 3 086C 40 31.5 54.8 4 5 08A8 40 26.3 83.3 5 3 0A6B 40 30 59.9 6 3 0C6A 40 28.7 66.1 7 3 0E69 40 27.4 73.7 8 3 1068 40 26.3 83.3 9 3 1267 40 25.3 95.8 1 3 026F 36 33.3 39.2 1 5 02AE 36 31.5 42 1 7 02ED 36 29.9 45.3 1 9 032C 36 28.4 49.2 1 11 036B 36 27.1 53.8 1 13 03AA 36 25.8 59.3 1 15 03E9 36 24.7 66.1 2 3 046E 36 31.5 42 2 5 04AC 36 28.4 49.2 DS07-16616-1E 79 MB91460H Series 80 Modulation Degree (k) Random No (N) CMPR [hex] Baseclk [MHz] Fmin [MHz] Fmax [MHz] 2 7 04EA 36 25.8 59.3 2 9 0528 36 23.7 74.7 3 3 066D 36 29.9 45.3 3 5 06AA 36 25.8 59.3 3 7 06E7 36 22.8 85.8 4 3 086C 36 28.4 49.2 4 5 08A8 36 23.7 74.7 5 3 0A6B 36 27.1 53.8 6 3 0C6A 36 25.8 59.3 7 3 0E69 36 24.7 66.1 8 3 1068 36 23.7 74.7 9 3 1267 36 22.8 85.8 1 3 026F 32 29.7 34.7 1 5 02AE 32 28 37.3 1 7 02ED 32 26.6 40.2 1 9 032C 32 25.3 43.6 1 11 036B 32 24.1 47.7 1 13 03AA 32 23 52.5 1 15 03E9 32 22 58.6 2 3 046E 32 28 37.3 2 5 04AC 32 25.3 43.6 2 7 04EA 32 23 52.5 2 9 0528 32 21.1 66.1 2 11 0566 32 19.5 89.1 3 3 066D 32 26.6 40.2 3 5 06AA 32 23 52.5 3 7 06E7 32 20.3 75.9 4 3 086C 32 25.3 43.6 4 5 08A8 32 21.1 66.1 5 3 0A6B 32 24.1 47.7 5 5 0AA6 32 19.5 89.1 6 3 0C6A 32 23 52.5 7 3 0E69 32 22 58.6 8 3 1068 32 21.1 66.1 9 3 1267 32 20.3 75.9 10 3 1466 32 19.5 89.1 DS07-16616-1E MB91460H Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute maximum ratings Parameter Symbol Rating Min Max Unit Remarks ⎯ ⎯ 50 V/ms 1 VDD5R - 0.3 + 6.0 V 1 VDD5 - 0.3 + 6.0 V VDD5-0.3 VDD35-0.3 VDD5+0.3 VDD35+0.3 V At least one pin of the Ports 26 to 29 (ANn) is used as digital input or output. VSS5-0.3 VDD35-0.3 VDD5+0.3 VDD35+0.3 V All pins of the Ports 26 to 29 (ANn) follow the condition of VIA Power supply slew rate Power supply voltage 1* Power supply voltage 2* Relationship of the supply voltages AVCC5 Analog power supply voltage*1 AVCC5 - 0.3 + 6.0 V *2 Analog reference power supply voltage*1 AVRH - 0.3 + 6.0 V *2 Input voltage 1*1 VI1 Vss5 - 0.3 VDD5 + 0.3 V Analog pin input voltage*1 VIA AVss5 - 0.3 AVcc5 + 0.3 V Output voltage 1*1 VO1 Vss5 - 0.3 VDD5 + 0.3 V ICLAMP - 4.0 + 4.0 mA *3 Σ |ICLAMP| ⎯ 20 mA *3 IOL ⎯ 10 mA “L” level average output current*5 IOLAV ⎯ 8 mA “L” level total maximum output current ΣIOL ⎯ 100 mA ΣIOLAV ⎯ 50 mA IOH ⎯ - 10 mA “H” level average output current*5 IOHAV ⎯ -4 mA “H” level total maximum output current ΣIOH ⎯ - 100 mA ΣIOHAV ⎯ - 25 mA Power consumption PD ⎯ 600 mW Operating temperature TA - 40 + 105 °C Tstg - 55 + 150 °C Maximum clamp current Total maximum clamp current “L” level maximum output current*4 “L” level total average output current*6 “H” level maximum output current*4 “H” level total average output current*6 Storage temperature at TA = 105°C *1 : The parameter is based on VSS5 = AVSS5 = 0.0 V. DS07-16616-1E 81 MB91460H Series *2 : AVCC5 and AVRH5 must not exceed VDD5 + 0.3 V. *3 : • Use within recommended operating conditions. •Use with DC voltage (current). •+B signals are input signals that exceed the VDD5 voltage. +B signals should always be applied by connecting a limiting resistor between the +B signal and the microcontroller. •The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed the rated value at any time , either instantaneously or for an extended period, when the +B signal is input. •Note that when the microcontroller drive current is low, such as in the low power consumption modes, the +B input potential can increase the potential at the power supply pin via a protective diode, possibly affecting other devices. • Note that if the +B signal is input when the microcontroller is off (not fixed at 0 V), power is supplied through the +B input pin; therefore, the microcontroller may partially operate. • Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not function in the power supply voltage. • Do not leave +B input pins open. • Example of recommended circuit : • Input/output equivalent circuit Protective diode VCC Limiting resistor P-ch +B input (0 V to 16 V) N-ch R *4 : Maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5 : Average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 100 ms period. *6 : Total average output current is defined as the value of the average current flowing through all of the corresponding pins for a 100 ms period. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 82 DS07-16616-1E MB91460H Series 2. Recommended operating conditions (VSS5 = AVSS5 = 0.0 V) Parameter Power supply voltage Smoothing capacitor at VCC18C pin Symbol Max VDD5 3.0 ⎯ 5.5 V VDD5R 3.0 ⎯ 5.5 V Internal regulator AVCC5 3.0 ⎯ 5.5 V A/D converter CS ⎯ 4.7 ⎯ μF Use a X7R ceramic capacitor or a capacitor that has similar frequency characteristics. ⎯ ⎯ 50 V/ms − 40 ⎯ + 105 °C TA 10 ms Lock-up time PLL (4 MHz ->16 ...100MHz) RC Oscillator Remarks Typ Main Oscillation stabilisation time ESD Protection (Human body model) Unit Min Power supply slew rate Operating temperature Value 0.6 Vsurge 2 fRC100kHz fRC2MHz 50 1 ms kV 100 2 200 4 Rdischarge = 1.5kΩ Cdischarge = 100pF kHz VDDCORE > 1.65V MHz WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. VCC18C VSS5 AVSS5 CS DS07-16616-1E 83 MB91460H Series 3. DC characteristics (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 105 °C) Parameter Symbol Pin name Condition ⎯ Port inputs if CMOS Hysteresis 0.8/0.2 input is selected Remarks Typ Max 0.8 × VDD ⎯ VDD + 0.3 V CMOS hysteresis input Port inputs if CMOS 0.7 × VDD Hysteresis 0.7/0.3 0.74 × VDD input is selected ⎯ VDD + 0.3 V 4.5 V < VDD < 5.5 V ⎯ ⎯ VDD + 0.3 V 3 V < VDD < 4.5 V ⎯ AUTOMOTIVE Hysteresis input is selected 0.8 × VDD ⎯ VDD + 0.3 V ⎯ Port inputs if TTL input is selected 2.0 ⎯ VDD + 0.3 V VIHR INITX ⎯ 0.8 × VDD ⎯ VDD + 0.3 V INITX input pin (CMOS Hysteresis) VIHM MD_3 to MD_0 ⎯ VDD - 0.3 ⎯ VDD + 0.3 V Mode input pins VIHX0S X0, X0A ⎯ 2.5 ⎯ VDD + 0.3 V External clock in “Oscillation mode” VIHX0F X0 ⎯ 0.8 × VDD ⎯ VDD + 0.3 V External clock in “Fast Clock Input mode” ⎯ Port inputs if CMOS Hysteresis 0.8/0.2 input is selected VSS - 0.3 ⎯ 0.2 × VDD V ⎯ Port inputs if CMOS Hysteresis 0.7/0.3 input is selected VSS - 0.3 ⎯ 0.3 × VDD V VSS - 0.3 ⎯ 0.5 × VDD V 4.5 V < VDD < 5.5 V ⎯ Port inputs if AUTOMOTIVE Hysteresis input is selected VSS - 0.3 ⎯ 0.46 × VDD V 3 V < VDD < 4.5 V ⎯ Port inputs if TTL input is selected VSS - 0.3 ⎯ 0.8 V VIL Input “L” voltage 84 Unit Min VIH Input “H” voltage Value VILR INITX ⎯ VSS - 0.3 ⎯ 0.2 × VDD V INITX input pin (CMOS Hysteresis) VILM MD_3 to MD_0 ⎯ VSS - 0.3 ⎯ VSS + 0.3 V Mode input pins VILXDS X0, X0A ⎯ VSS - 0.3 ⎯ 0.5 V External clock in “Oscillation mode” DS07-16616-1E MB91460H Series Parameter Symbol Input “L” voltage Output “H” voltage Output “L“ voltage Pin name Condition X0 ⎯ Value Unit Remarks 0.2 × VDD V External clock in “Fast Clock Input mode” ⎯ ⎯ V Driving strength set to 2 mA VDD - 0.5 ⎯ ⎯ V Driving strength set to 5 mA I2C 3.0V ≤ VDD ≤ 5.5V, outputs IOH = - 3mA VDD - 0.5 ⎯ ⎯ V VOL2 4.5V ≤ VDD ≤ 5.5V, Normal IOL = + 2mA outputs 3.0V ≤ VDD < 4.5V, IOL = + 1.6mA ⎯ ⎯ 0.4 V Driving strength set to 2 mA VOL5 4.5V ≤ VDD ≤ 5.5V, Normal IOL = + 5mA outputs 3.0V ≤ VDD < 4.5V, IOL = + 3mA ⎯ ⎯ 0.4 V Driving strength set to 5 mA VOL3 I2C 3.0V ≤ VDD ≤ 5.5V, outputs IOL = + 3mA ⎯ ⎯ 0.4 V -1 ⎯ +1 IIL 3.0V ≤ VDD ≤ 5.5V VSS5 < VI < VDD Pnn_m TA=25 °C *1 3.0V ≤ VDD ≤ 5.5V VSS5 < VI < VDD TA=105 °C Min Typ Max VSS - 0.3 ⎯ VOH2 4.5V ≤ VDD ≤ 5.5V, Normal IOH = - 2mA outputs 3.0V ≤ VDD < 4.5V, IOH = - 1.6mA VDD - 0.5 VOH5 4.5V ≤ VDD ≤ 5.5V, Normal IOH = − 5mA outputs 3.0V ≤ VDD < 4.5V, IOH = - 3mA VOH3 VILXDF Input leakage current Analog input leakage current IAIN ANn*2 Pull-up resistance RUP Pnn_m *3 INITX Pull-down resistance RDOWN Pnn_m *4 DS07-16616-1E μA -3 ⎯ +3 3.0V ≤ VDD ≤ 5.5V TA=25 °C -1 ⎯ +1 μA 3.0V ≤ VDD ≤ 5.5V TA=105 °C -3 ⎯ +3 μA 3.0V ≤ VDD ≤ 3.6V 40 100 160 4.5V ≤ VDD ≤ 5.5V 25 50 100 3.0V ≤ VDD ≤ 3.6V 40 100 180 4.5V ≤ VDD ≤ 5.5V 25 50 100 kΩ kΩ 85 MB91460H Series Parameter Symbol Input capacitance Power supply current MB91 F464HB 4. 86 Condition Value Unit Remarks Min Typ Max CIN All except VDD5, VDD5R, f = 1 MHz VSS5, AVCC5, AVSS5, AVRH5 - 5 15 pF ICC CLKB: 100 MHz CLKP: 50 MHz VDD5R CLKT: 50 MHz CLKCAN: 50 MHz - 100 130 mA TA = + 25 °C - 30 150 μA TA = + 105 °C - 300 2000 μA TA = + 25 °C - 100 500 μA TA = + 105 °C - 500 2400 μA TA = + 25 °C - 50 250 μA TA = + 105 °C - 400 2200 μA RTC : 100 kHz mode *5 ICCH VDD5R Code fetch from Flash At stop mode *5 RTC : 4 MHz mode *5 ILVE VDD5 ⎯ ⎯ 70 150 μA External low voltage detection ILVI VDD5R ⎯ ⎯ 50 100 μA Internal low voltage detection - - 250 500 μA Main clock (4 MHz) - - 20 40 μA Sub clock (32 kHz) IOSC 1. 2. 3. Pin name VDD5 Pnn_m includes all GPIO pins. Analog (AN) channels and PullUp/PullDown are disabled. ANn includes all pins where AN channels are enabled. Pnn_m includes all GPIO pins. The pull up resistors must be enabled by PPER/PPCR setting and the pins must be in input direction. Pnn_m includes all GPIO pins. The pull down resistors must be enabled by PPER/PPCR setting and the pins must be in input direction. DS07-16616-1E MB91460H Series 4. A/D converter characteristics (VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C) Parameter Symbol Pin name Value Min Typ Max Unit Remarks Resolution ⎯ ⎯ ⎯ ⎯ 10 bit Total error ⎯ ⎯ −3 ⎯ +3 LSB Nonlinearity error ⎯ ⎯ − 2.5 ⎯ + 2.5 LSB Differential nonlinearity error ⎯ ⎯ − 1.9 ⎯ + 1.9 LSB Zero reading voltage VOT ANn AVRL− 1.5 LSB AVRL + 0.5 LSB AVRL + 2.5 LSB V Full scale reading voltage VFST ANn AVRH− 3.5 LSB AVRH− 1.5 LSB AVRH + 0.5 LSB V 0.6 ⎯ 16,500 μs 4.5 V ≤ AVCC5 ≤ 5.5 V 2.0 ⎯ ⎯ μs 3.0 V ≤ AVCC5 ≤ 4.5 V 0.4 ⎯ ⎯ μs 4.5 V ≤ AVCC5 ≤ 5.5 V, REXT < 2 kΩ 1.0 ⎯ ⎯ μs 3.0 V ≤ AVCC5 ≤ 4.5 V, REXT < 1 kΩ 1.0 ⎯ ⎯ μs 4.5 V ≤ AVCC5 ≤ 5.5 V 3.0 ⎯ ⎯ μs 3.0 V ≤ AVCC5 ≤ 4.5 V ⎯ ⎯ 11 pF ⎯ ⎯ 2.6 kΩ 4.5 V ≤ AVCC5 ≤ 5.5 V ⎯ ⎯ 12.1 kΩ 3.0 V ≤ AVCC5 ≤ 4.5 V −1 ⎯ +1 μA TA = + 25 °C −3 ⎯ +3 μA TA = + 105 °C Compare time Sampling time Conversion time Input capacitance Input resistance Tcomp Tsamp Tconv CIN RIN ⎯ ⎯ ⎯ ANn ANn Analog input leakage current IAIN ANn Analog input voltage range VAIN ANn AVRL ⎯ AVRH V Offset between input channels ⎯ ANn ⎯ ⎯ 4 LSB (Continued) Note : The accuracy gets worse as AVRH - AVRL becomes smaller DS07-16616-1E 87 MB91460H Series (Continued) Parameter Symbol Pin name Reference voltage current per ADC macro *3 Min Typ Max Unit Remarks AVRH AVRH5 0.75 × AVCC5 ⎯ AVCC5 V AVRL AVSS5 AVSS5 ⎯ AVCC5 × 0.25 V IA AVCC5 ⎯ 2.5 5 mA A/D Converter active IAH AVCC5 ⎯ ⎯ 5 μA A/D Converter not operated *1 IR AVRH5 ⎯ 0.7 1 mA A/D Converter active IRH AVRH5 ⎯ ⎯ 5 μA A/D Converter not operated *2 Reference voltage range Power supply current per ADC macro *3 Value *1 : Supply current at AVCC5, if A/D converter and ALARM comparator are not operating, (VDD5 = AVCC5 = AVRH = 5.0 V) *2 : Input current at AVRH5, if A/D converter is not operating, (VDD5 = AVCC5 = AVRH = 5.0 V) *3 : The current consumption per ADC macro is given here. On devices having more then one A/D converter, the current values have to be multiplied by the number of macros. Sampling Time Calculation Tsamp = ( 2.6 kOhm + REXT) × 11pF × 7; for 4.5V ≤ AVCC5 ≤ 5.5V Tsamp = (12.1 kOhm + REXT) × 11pF × 7; for 3.0V ≤ AVCC5 < 4.5V Conversion Time Calculation Tconv = Tsamp + Tcomp 88 DS07-16616-1E MB91460H Series Definition of A/D converter terms • Resolution Analog variation that is recognizable by the A/D converter. • Nonlinearity error Deviation between actual conversion characteristics and a straight line connecting the zero transition point (00 0000 0000B ↔ 00 0000 0001B) and the full scale transition point (11 1111 1110B ↔ 11 1111 1111B). • Differential nonlinearity error Deviation of the input voltage from the ideal value that is required to change the output code by 1 LSB. • Total error This error indicates the difference between actual and theoretical values, including the zero transition error, full scale transition error, and nonlinearity error. Total error 3FFH 1.5 LSB’ 3FEH Actual conversion characteristics Digital output 3FDH {1 LSB’ (N - 1) + 0.5 LSB’} 004H VNT 003H (measurement value) Actual conversion characteristics 002H Ideal characteristics 001H 0.5 LSB' AVSS5 AVRH Analog input 1LSB' (ideal value) = AVRH − AVSS5 [V] 1024 Total error of digital output N = VNT − {1 LSB' × (N − 1) + 0.5 LSB'} 1 LSB' N : A/D converter digital output value VOT' (ideal value) = AVSS5 + 0.5 LSB' [V] VFST' (ideal value) = AVRH − 1.5 LSB' [V] VNT : Voltage at which the digital output changes from (N + 1) H to NH (Continued) DS07-16616-1E 89 MB91460H Series (Continued) Nonlinearity error 3FFH Differential nonlinearity error Actual conversion characteristics Actual conversion characteristics (N+1)H 3FEH {1 LSB (N - 1) + VOT} VFST 004H VNT (measurement value) 003H 002H Ideal characteristics (measurement value) Digital output Digital output 3FDH NH (N-1)H VFST Actual conversion characteristics VNT (measurement value) Ideal characteristics (N-2)H 001H Actual conversion characteristics VTO (measurement value) AVSS5 AVSS5 AVRH Analog input Nonlinearity error of digital output N = VFST − VOT 1022 AVRH Analog input VNT − {1LSB × (N − 1) + VOT} [LSB] 1LSB Differential nonlinearity error of digital output N = 1LSB = (measurement value) V (N + 1) T − VNT 1LSB − 1 [LSB] [V] N : A/D converter digital output value VOT : Voltage at which the digital output changes from 000H to 001H. VFST : Voltage at which the digital output changes from 3FEH to 3FFH. 90 DS07-16616-1E MB91460H Series 5. Alarm comparator characteristics Parameter Symbol Pin name Min ⎯ IA5ALMF Power supply current Value Typ 25 Max 40 Unit Remarks μA Alarm comparator enabled in fast mode (per channel) *1 AVCC5 ⎯ IA5ALMS 7 10 μA Alarm comparator enabled in normal mode (per channel) *1 IA5ALMH ⎯ ⎯ 5 μA Alarm comparator disabled -1 ⎯ +1 μA TA=25 °C -3 ⎯ +3 μA TA=105 °C ALARM pin input current IALIN ALARM pin input voltage range VALIN 0 ⎯ AVCC5 V Alarm upper limit voltage VIAH AVCC5 × 0.78 - 3% AVCC5 × 0.78 AVCC5 × 0.78 + 3% V Alarm lower limit voltage VIAL AVCC5 × 0.36 - 5% AVCC5 × 0.36 AVCC5 × 0.36 + 5% V VIAHYS 50 ⎯ 250 mV RIN 5 ⎯ ⎯ MΩ tCOMPF ⎯ 0.1 0.2 μs Alarm hysteresis voltage Alarm input resistance ALARM_n Comparion time tCOMPS ⎯ 1 2 μs Alarm comparator enabled in fast mode *1 Alarm comparator enabled in normal mode *1 Note: *1 : The fast Alarm Comparator mode is enabled by setting ACSR.MD=1 Setting ACSR.MD=0 sets the normal mode. DS07-16616-1E 91 MB91460H Series 6. FLASH memory program/erase characteristics 6.1. MB91F464HB (TA = 25oC, Vcc = 5.0V) Parameter Value Unit Remarks 3.6 s Erasure programming time not included n*0.9 n*3.6 s n is the number of Flash sector of the device 23 370 μs System overhead time not included Min Typ Max Sector erase time - 0.9 Chip erase time - Word (16-bit or 32-bit width) programming time - Programme/Erase cycle 10 000 cycle Flash data retention time 20 year *1 *1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85oC) 92 DS07-16616-1E MB91460H Series 7. AC characteristics 7.1. Clock timing (VDD5 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 105 °C) Parameter Clock frequency Symbol Pin name fC Value Unit Condition 16 MHz Opposite phase external supply or crystal 100 kHz Min Typ Max X0 X1 3.5 4 X0A X1A 32 32.768 • Clock timing condition tC X0, X1, X0A, X1A 0.8 VCC 0.2 VCC PWH 7.2. PWL Reset input ratings (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 105 °C) Parameter INITX input time (at power-on) INITX input time (other than the above) Symbol tINTL Pin name Condition Value Unit Min Max 8 ⎯ ms 20 ⎯ μs ⎯ INITX tINTL INITX DS07-16616-1E 0.2 VCC 93 MB91460H Series 7.3. LIN-USART Timings at VDD5 = 3.0 to 5.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = -40 °C to +105 °C - Cl = 50 pF (load capacity value of pins when testing) - VOL = 0.2 x VDD5 - VOH = 0.8 x VDD5 - EPILR = 0, PILR = 1 (Automotive Level = worst case) (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 105 °C) Parameter Symbol Pin name Serial clock cycle time tSCYCI SCKn SCK ↓ → SOT delay time tSLOVI SCKn SOTn SOT → SCK ↓ delay time tOVSHI SCKn SOTn Valid SIN → SCK ↑ setup time tIVSHI SCKn SINn SCK ↑ → valid SIN hold time tSHIXI Serial clock “H” pulse width Condition VDD5 = 3.0 V to 4.5 V VDD5 = 4.5 V to 5.5 V Unit Min Max Min Max 4 tCLKP ⎯ 4 tCLKP ⎯ ns - 30 30 - 20 20 ns m× tCLKP - 30* ⎯ m× tCLKP - 20* ⎯ ns tCLKP + 55 ⎯ tCLKP + 45 ⎯ ns SCKn SINn 0 ⎯ 0 ⎯ ns tSHSLE SCKn tCLKP + 10 ⎯ tCLKP + 10 ⎯ ns Serial clock “L” pulse width tSLSHE SCKn tCLKP + 10 ⎯ tCLKP + 10 ⎯ ns SCK ↓ → SOT delay time tSLOVE SCKn SOTn ⎯ 2 tCLKP + 55 ⎯ 2 tCLKP + 45 ns Valid SIN → SCK ↑ setup time tIVSHE SCKn SINn 10 ⎯ 10 ⎯ ns SCK ↑ → valid SIN hold time tSHIXE SCKn SINn tCLKP + 10 ⎯ tCLKP + 10 ⎯ ns SCK rising time tFE SCKn ⎯ 20 ⎯ 20 ns SCK falling time tRE SCKn ⎯ 20 ⎯ 20 ns Internal clock operation (master mode) External clock operation (slave mode) * : Parameter m depends on tSCYCI and can be calculated as : • if tSCYCI = 2*k*tCLKP, then m = k, where k is an integer > 2 • if tSCYCI = (2*k + 1)*tCLKP, then m = k + 1, where k is an integer > 1 Notes : • The above values are AC characteristics for CLK synchronous mode. • tCLKP is the cycle time of the peripheral clock. 94 DS07-16616-1E MB91460H Series • Internal clock mode (master mode) tSCYCI SCKn for ESCR:SCES = 0 VOH VOL VOL VOH SCKn for ESCR:SCES = 1 VOH VOL tSLOVI tOVSHI VOH VOL SOTn tIVSHI tSHIXI VIH VIL SINn VIH VIL • External clock mode (slave mode) tSLSHE SCKn for ESCR:SCES = 0 VOH SCKn for ESCR:SCES = 1 VOL tSHSLE VOH VOL VOL VOH VOH VOL VOH VOL tRE tFE tSLOVE SOTn VOH VOL tIVSHE SINn DS07-16616-1E VIH VIL tSHIXE VIH VIL 95 MB91460H Series 7.4. I2C AC Timings at VDD5 = 3.0 to 5.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 3 mA - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = - 40 °C to + 105 °C - Cl = 50 pF - VOL = 0.3 × VDD5 - VOH = 0.7 × VDD5 - EPILR = 0, PILR = 0 (CMOS Hysteresis 0.3 × VDD5/0.7 × VDD5) Fast mode: (VDD5 = 3.5 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 105 °C) Parameter Symbol Pin name fSCL Value Unit Min Max SCLn 0 400 kHz tHD;STA SCLn, SDAn 0.6 ⎯ μs LOW period of the SCL clock tLOW SCLn 1.3 ⎯ μs HIGH period of the SCL clock tHIGH SCLn 0.6 ⎯ μs Setup time for a repeated START condition tSU;STA SCLn, SDAn 0.6 ⎯ μs Data hold time for I2C-bus devices tHD;DAT SCLn, SDAn 0 0.9 μs Data setup time tSU;DAT SCLn SDAn 100 ⎯ ns Rise time of both SDA and SCL signals tr SCLn, SDAn 20 + 0.1Cb 300 ns Fall time of both SDA and SCL signals tf SCLn, SDAn 20 + 0.1Cb 300 ns Setup time for STOP condition tSU;STO SCLn, SDAn 0.6 ⎯ μs Bus free time between a STOP and START condition tBUF SCLn, SDAn 1.3 ⎯ μs Capacitive load for each bus line Cb SCLn, SDAn ⎯ 400 pF Pulse width of spike suppressed by input filter tSP SCLn, SDAn 0 (1..1.5) × tCLKP ns SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated Remark *1 *1 The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles of peripheral clock, depending on the phase relationship between I2C signals (SDA, SCL) and peripheral clock. Note: tCLKP is the cycle time of the peripheral clock. 96 DS07-16616-1E DS07-16616-1E SCL SDA tHD;STA tf S tr tHD;DAT tLOW tHIGH tSU;DAT tSU;STA Sr tHD;STA tSP tr P tSU;ST0 tBUF S tf MB91460H Series 97 MB91460H Series 7.5. Free-run timer clock (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 105 °C) Parameter Input pulse width Symbol Pin name Condition tTIWH tTIWL CKn ⎯ Value Min Max 4tCLKP ⎯ Unit ns Note : tCLKP is the cycle time of the peripheral clock. CKn VIH VIH tTIWH 7.6. VIL VIL tTIWL Trigger input timing (VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = -40 °C to + 105 °C) Parameter Input capture input trigger A/D converter trigger Symbol Pin name Condition tINP ICUn tATGX ATGX Value Unit Min Max ⎯ 5tCLKP ⎯ ns ⎯ 5tCLKP ⎯ ns Note : tCLKP is the cycle time of the peripheral clock. tATGX, tINP ICUn, ATGX 98 DS07-16616-1E MB91460H Series 7.7. External Bus AC Timings at VDD35 = 3.0 to 5.5 V • Conditions during AC measurements All AC tests were measured under the following conditions: - IOdrive = 5 mA - VDD35 = 4.5 V to 5.5 V, Iload = 3 mA - VSS5 = 0 V - Ta = - 40 °C to + 105 °C - Cl = 50 pF - VOL = 0.5 × VDD35 - VOH = 0.5 × VDD35 - EPILR = 0, PILR = 1 (Automotive Level = worst case) 7.7.1. Basic Timing (VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 105 °C) Parameter SYSCLK SYSCLK ↓ to CSXn delay time Symbol tCLCH tCHCL Pin name SYSCLK tCLCSL tCLCSH SYSCLK ↑ to CSXn delay time (Addr → CS delay) tCHCSL SYSCLK ↓ to Address valid delay time tCLAV SYSCLK CSXn SYSCLK A21 to A0 Value Unit Min Max 1/2 × tCLKT - 1 1/2 × tCLKT + 9 ns 1/2 × tCLKT - 9 1/2 × tCLKT + 1 ns ⎯ 8 ns ⎯ 12 ns -6 +1 ns ⎯ 13 ns Note : tCLKT is the cycle time of the external bus clock. DS07-16616-1E 99 MB91460H Series tCLCH tCHCL tCYC SYSCLK tCLCSL tCLCSH CSXn tCHCSL delayed CSXn tCLASH tCLASL ASX tCLAV ADDRESS tCLBAH tCLBAL BAAX 100 DS07-16616-1E MB91460H Series 7.7.2. Synchronous/Asynchronous read access (VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 105 °C) Parameter SYSCLK ↑ to RDX delay time Symbol Pin name TCHRL SYSCLK RDX TCHRH Value Unit Min Max -7 1 ns -4 2 ns Data valid to RDX ↑ setup time TDSRH RDX D31 to D16 33 ⎯ ns RDX ↑ to Data valid hold time TRHDX RDX D31 to D16 0 ⎯ ns SYSCLK WRXn ⎯ 8 ns 0 ⎯ ns SYSCLK CSXn ⎯ 8 ns ⎯ 12 ns TCLWRL SYSCLK ↓ to WRXn (as byte enable) delay time TCLWRH TCLCSL SYSCLK ↓ to CSXn delay time TCLCSH SYSCLK tCLCSL tCLCSH CSXn tCLWRL tCLWRH WRXn (as byte enable) tCHRH tCHRL RDX tDSRH tRHDX DATA IN DS07-16616-1E 101 MB91460H Series 7.7.3. Synchronous write access (VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 105 °C) Parameter SYSCLK ↓ to WRXn delay time Symbol Pin name TCLWRL SYSCLK WRXn TCLWRH Value Unit Min Max ⎯ 8 ns 0 ⎯ ns Data valid to WRXn ↓ setup time TDSWRL WRXn D31 to D16 -7 ⎯ ns WRXn ↑ to Data valid hold time TWRHDH WRXn D31 to D16 tCLKT - 20 ⎯ ns ⎯ 8 ns ⎯ 12 ns SYSCLK ↓ to CSXn delay time TCLCSL TCLCSH SYSCLK CSXn SYSCLK tCLCSH tCLCSL CSXn tCLWRH tCLWRL WRXn tDSWRL tWRHDH DATA OUT 102 DS07-16616-1E MB91460H Series 7.7.4. Asynchronous write access (VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 105 °C) Parameter Symbol Pin name WRXn ↓ to WRXn ↑ pulse width TWRLWRH Data valid to WRXn ↓ setup time WRXn ↑ to Data valid hold time WRXn to CSXn delay time Value Unit Min Max WRXn tCLKT ⎯ ns TDSWRL WRXn D31 to D16 1/2 × tCLKT - 10 ⎯ ns TWRHDH WRXn D31 to D16 1/2 × tCLKT - 19 ⎯ ns ⎯ 1/2 × tCLKT ns 1/2 × tCLKT ⎯ ns TCLWRL WRXn CSXn TWRHCH CSXn TWRHCH TCLWRL TWRLWRH WRXn TDSWRL TWRHDH DATA OUT DS07-16616-1E 103 MB91460H Series 7.7.5. RDY waitcycle insertion (VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = -40 °C to + 105 °C) Parameter Symbol Pin name RDY setup time TRDYS RDY hold time TRDYH Value Unit Min Max SYSCLK RDY 34 ⎯ ns SYSCLK RDY 0 ⎯ ns SYSCLK tRDYS tRDYH RDY 104 DS07-16616-1E MB91460H Series ■ ORDERING INFORMATION Part number MB91F464HBPMC-GSE2 DS07-16616-1E Package 144-pin plastic LQFP (FPT-144P-M08) Remarks Lead-free package 105 MB91460H Series ■ PACKAGE DIMENSION 144-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 20.0 × 20.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 1.20g Code (Reference) P-LFQFP144-20×20-0.50 (FPT-144P-M08) 144-pin plastic LQFP (FPT-144P-M08) Note 1) *:Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 22.00±0.20(.866±.008)SQ * 20.00±0.10(.787±.004)SQ 108 0.145±0.055 (.006±.002) 73 109 72 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 .059 –.004 0˚~8˚ INDEX 144 37 "A" LEAD No. 1 36 0.50(.020) 0.22±0.05 (.009±.002) 0.08(.003) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) (Mounting height) 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) M ©2003-2008 FUJITSU MICROELECTRONICS LIMITED F144019S-c-4-7 C 2003 FUJITSU LIMITED F144019S-c-4-6 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ 106 DS07-16616-1E MB91460H Series ■ REVISION HISTORY Version Date 2.0 2009-01-07 DS07-16616-1E Remark Initial version 107 MB91460H Series ■ MAIN CHANGES IN THIS EDITION Page 87 Section 4. A/D converter characteristics Change Results Corrected "Zero reading voltage" and "Full scale reading voltage". The vertical lines marked in the left side of the page show the changes. 108 DS07-16616-1E MB91460H Series MEMO DS07-16616-1E 109 MB91460H Series MEMO 110 DS07-16616-1E MB91460H Series MEMO DS07-16616-1E 111 MB91460H Series FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. 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