FUJITSU MB89PV490CF

FUJITSU SEMICONDUCTOR
DATA SHEET
Revision 1.5
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89490 Series
MB89497/498/F499/PV490
■ DESCRIPTION
The MB89490 series has been developed as a general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit single-chip microcontrollers.
AR
Y
In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as
21-bit timebase timer, watch prescaler, PWM timer, 8/16-bit timer/counter, remote receiver control, LCD
controller/driver, external interrupt 0 (edge), external interrupt 1 (level), 10-bit A/D converter, UART/SIO, SIO,
I2C and watchdog timer reset.
IN
The MB89490 series is designed suitable for compact disc/cassette tape/radio receiver controller as well as in
a wide range of applications for consumer product.
IM
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
■ PACKAGE
PR
EL
• Package used
QFP package for MB89F499, MB89497,MB89498
MQFP package for MB89PV490
• High speed operating capability at low voltage
• Minimum execution time: 0.32 µs/12.5MHz
100-pin Plastic QFP
(Continued)
100-pin Ceramic MQFP
(FPT-100P-M06)
(FTP-100P-M06)
(MQP-100C-P01)
1
MB89490 Series
(Continued)
• F2MC-8L family CPU core
Instruction set optimized for controllers
Multiplication and division instructions
16-bit arithmetic operations
Test and branch instructions
Bit manipulation instructions, etc.
• Clock
Embedded PLL clock multiplication circuit for sub-clock
Operating clock (PLL for sub-clock) can be selected four times of the sub-clock oscillation
• Six timers
PWM timer x 2
8/16-bit timer/counter x 2
21-bit timebase timer
Watch prescaler
• External interrupt
Edge detection (selectable edge) : 8 channels
Low level interrupt (wake-up function) : 8 channels
• 10-bit A/D converter (8 channels)
10-bit successive approximation type
• UART/SIO
Synchronous/asynchronous data transfer capability
• SIO
Synchronous data transfer capability
• LCD controller/driver
Max. 32 segments output x 4 commons
• I2C interface circuit
• Remote receiver circuit
• Low-power consumption mode
Stop mode (oscillation stops so as to minimize the current consumption.)
Sleep mode (CPU stops so as to reduce the current consumption to approx. 1/3 of normal.)
Watch mode (everything except the watch prescaler stops so as to reduce the power comsumption to an
extremely low level.)
Sub-clock mode
• Watchdog timer reset
• I/O ports: max. 66channels
■ PRODUCT LINEUP
Part number
Parameter
Classification
ROM size
RAM size
MB89497
MB89498
Mass production products
(mask ROM product)
MB89PV490
FLASH
Piggy-back
32K x 8-bit
48K x 8-bit
60K x 8-bit (internal FLASH) 60K x 8-bit (external ROM)*1
(internal ROM) (internal ROM)
1K x 8-bit
2K x 8-bit
*1 : Use MBM27C512 as the external ROM.
2
MB89F499
2K x 8-bit
2K × 8-bit
MB89490 Series
Part number
Parameter
MB89497
MB89498
MB89F499
MB89PV490
CPU functions
Number of instructions
Instruction bit length
Instruction length
Data bit length
Minimum execution time
Minimum interrupt processing time
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, 16 bits
: 0.32 µs/12.5 MHz
: 2.88 µs/12.5 MHz
Ports
I/O ports (CMOS)
Input ports (CMOS)
N-channel open drain I/O ports
Total
: 56 pins
: 2 pins
: 8 pins
: 66 pins
21-bit timebase
timer
Interrupt period (0.66 ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 MHz
Watchdog timer
Reset period (167.8 ms to 335.5 ms) at 12.5 MHz.
PWM timer 0,1
8-bit reload timer operation (supports square wave output, operating clock period: 1, 8, 16, 64
tinst,)
8-bit resolution PWM operation
8/16-bit timer/
counter 00, 01
Can be operated either as a 2-channel 8-bit timer/counter (timer 00 and timer 01, each with its
own independent operating clock cycle), or as one 16-bit timer/counter
In timer 00 or 16-bit timer/counter operation, event counter operation (external clock-triggered)
and square wave output capability
8/16-bit timer/
counter 10, 11
Can be operated either as a 2-channel 8-bit timer/counter (timer 10 and timer 11, each with its
own independent operating clock cycle), or as one 16-bit timer/counter
In timer 10 or 16-bit timer/counter operation, event counter operation (external clock-triggered)
and square wave output capability
External interrupt 0
(edge)
8 independent channels (selectable edge, interrupt vector, request flag)
External interrupt 1
(level)
8 channels (low level interrupt)
A/D converter
10-bit resolution × 8 channels
A/D conversion function (conversion time: 38 tinst )
Supports repeated activation by internal clock
Common output
LCD controller/driver Segment output
Bias power supply pins
LCD display RAM size
UART/SIO
: 4 (max.)
: 32 (max.)
:3
: 32 × 4 bits
Synchronous/asynchronous data transfer capability
(Max. baud rate: 97.656 Kbps at 12.5 MHz)
(7 and 8 bits with parity bit; 8 and 9 bits without parity bit)
SIO
8-bit serial I/O with LSB first/MSB first selectability
One clock selectable from four operation clock (one external shift clock, three internal shift
clock: 0.64µs, 2.56µs, 10.24µs at 12.5MHz)
I2C*1
1 channel
Use a 2-wire protocol to communicate with other device
Remote receiver
Selectable maximum noise width removal
Reversible input polarity
Standby mode
Sleep mode, stop mode, watch mode, sub-clock mode
Process
CMOS
Operating voltage
2.2V ~ 3.6V
2.7V ~ 3.6V
2.7V ~ 3.6V
*1 : I2C is complied to Philips I2C specification.
3
MB89490 Series
■ PACKAGE AND CORRESPONDING PRODUCTS
Part number
MB89497/498
MB89F499
MB89PV490
FPT-100P-M06
O
O
X
MQP-100C-P01
X
X
O
Package
O : Availabe
X : Not available
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following point:
• The stack area is set at the upper limit of the RAM.
2. Current Consumption
• For the MB89PV490 the current consumed by the EPROM mounted in the piggy-back socket is needed to be
included.
• When operating at low speed, the current consumed by the FLASH product is greater than that for the mask
ROM product. However, the current consumption is roughly the same in sleep and stop mode.
• For more information, see “■
Electrical Characteristics.”
3. Oscillation Stabilization Time after Power-on Reset
• For MB89PV490 and MB89F499, the power-on stabilization time cannot be selected.
• For MB89497 and MB89498, the power-on stabilization time can be selected.
• For more information, please refer to “■
4
Mask Option”.
MB89490 Series
■ PIN ASSIGNMENT
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Vss
X0
X1
MOD0
RST
P84
P83
P82/SCK1
P81/SO1
P80/SI1
P77/SEG31
P76/SEG30
P75/SEG29
P74/SEG28
P73/SEG27
P72/SEG26
P71/SEG25
P70/SEG24
P67/SEG23
P66/SEG22
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P65/SEG21
P64/SEG20
P63/SEG19
P62/SEG18
P61/SEG17
P60/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
P54/COM3
P53/COM2
COM1
COM0
V1
V2
V3
Vcc
* High current pins
(FPT-100P-M06)
AVss
P30/AN0/INT10
P31/AN1/INT11
P32/AN2/INT12
P33/AN3/INT13
P34/AN4/INT14
P35/AN5/INT15
P36/AN6/INT16
P37/AN7/INT17
*P40
*P41
*P42
*P43
*P44
*P45
*P46/SCL
*P47/SDA
X1A
X0A
Vss
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Vcc
*P00
*P01
*P02
*P03
*P04
*P05
*P06
*P07
P10/INT00
P11/INT01
P12/INT02
P13/INT03
P14/INT04
P15/INT05
P16/INT06
P17/INT07
P20/TO0
P21/RMC
P22/EC0
P23
P24/TO1
P25/EC1
P26/PWM0
P27/PWM1
P50/SI0
P51/SO0
P52/SCK0
AVR
AVcc
5
MB89490 Series
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Vss
X0
X1
MOD0
RST
P84
P83
P82/SCK1
P81/SO1
P80/SI1
P77/SEG31
P76/SEG30
P75/SEG29
P74/SEG28
P73/SEG27
P72/SEG26
P71/SEG25
P70/SEG24
P67/SEG23
P66/SEG22
(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
120
119
118
117
116
115
114
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
121
122
123
124
125
126
127
128
129
130
131
132
101
102
103
104
113
112
111
110
109
108
107
106
105
P65/SEG21
P64/SEG20
P63/SEG19
P62/SEG18
P61/SEG17
P60/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
P54/COM3
P53/COM2
COM1
COM0
V1
V2
V3
Vcc
* High current pins
(MQP-100C-P01)
AVss
P30/AN0/INT10
P31/AN1/INT11
P32/AN2/INT12
P33/AN3/INT13
P34/AN4/INT14
P35/AN5/INT15
P36/AN6/INT16
P37/AN7/INT17
*P40
*P41
*P42
*P43
*P44
*P45
*P46/SCL
*P47/SDA
X1A
X0A
Vss
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Vcc
*P00
*P01
*P02
*P03
*P04
*P05
*P06
*P07
P10/INT00
P11/INT01
P12/INT02
P13/INT03
P14/INT04
P15/INT05
P16/INT06
P17/INT07
P20/TO0
P21/RMC
P22/EC0
P23
P24/TO1
P25/EC1
P26/PWM0
P27/PWM1
P50/SI0
P51/SO0
P52/SCK0
AVR
AVcc
Pin assignment on package top (MB89PV490 only)
Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name
101
N.C.
109
A2
117
N.C.
125
OE
102
A15
110
A1
118
O4
126
N.C.
103
A12
111
A0
119
O5
127
A11
104
A7
112
N.C.
120
O6
128
A9
105
A6
113
O1
121
O7
129
A8
106
A5
114
O2
122
O8
130
A13
107
A4
115
O3
123
CE
131
A14
108
A3
116
VSS
124
A10
132
VCC
N.C.: As connected internally, do not use.
6
MB89490 Series
■ PIN DESCRIPTION
Pin number
MQFP*1/QFP*2
99
Pin name
I/O circuit
type
Function
A
Connection pins for a crystal or other oscillator.
An external clock can be connected to X0. In this case, leave X1 open.
A
Connection pins for a crystal or other oscillator.
An external clock can be connected to X0A. In this case, leave X1A
open.
X0
98
X1
49
X0A
48
X1A
97
MOD0
B
Input pin for setting the memory access mode.
Connect directly to VSS.
95, 94
P84,P83
J
General-purpose CMOS Input port.
96
RST
C
Reset I/O pin. The pin is an N-ch open-drain type with pull-up resistor
and a hysteresis input. The pin outputs an “L” level when an internal
reset request is present. Inputting an “L” level initializes internal
circuits.
2~9
P00 ~ P07
D
General-purpose CMOS I/O port.
10~17
P10/INT00
~
P17/INT07
E
General-purpose CMOS I/O port.
The pin is shared with external interrupt 0 input.
18
P20/TO0
F
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer/counter 00, 01 output.
19
P21/RMC
E
General-purpose CMOS I/O port.
The pin is shared with remote receiver input.
20
P22/EC0
E
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer/counter 00, 01 input.
21
P23
F
General-purpose CMOS I/O port.
22
P24/TO1
F
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer/counter 10, 11 output.
23
P25/EC1
E
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer/counter 10,11 input.
24
P26/PWM0
F
General-purpose CMOS I/O port.
The pin is shared with PWM0 output.
25
P27/PWM1
F
General-purpose CMOS I/O port.
The pin is shared with PWM1 output.
32 ~ 39
P30/AN0/INT10
~
P37/AN7/INT17
G
General-purpose CMOS I/O port.
The pin is shared with external interrupt 1 input and A/D converter
input.
40 ~ 45
P40~P45
H
General-purpose N-ch open-drain I/O port.
46
P46/SCL
H
General-purpose N-ch open-drain I/O port.
The pin is shared with I2C clock I/O.
47
P47/SDA
H
General-purpose N-ch open-drain I/O port.
The pin is shared with I2C data I/O.
26
P50/SI0
E
General-purpose CMOS I/O port.
The pin is shared with SIO data input.
27
P51/SO0
F
General-purpose CMOS I/O port.
The pin is shared with SIO data output.
28
P52/SCK0
E
General-purpose CMOS I/O port.
The pin is shared with SIO clock I/O.
7
MB89490 Series
(Continued)
Pin number
Pin name
I/O circuit
type
57
P53/COM2
F/I
General-purpose CMOS I/O port.
The pin is shared with the LCD common output.
58
P54/COM3
F/I
General-purpose CMOS I/O port.
The pin is shared with the LCD common output.
75 ~ 82
P60/SEG16
~
P67/SEG23
F/I
General-purpose CMOS I/O port.
The pin is shared with LCD segment output.
83 ~ 90
P70/SEG24
~
P77/SEG31
F/I
General-purpose CMOS I/O port.
The pin is shared with LCD segment output.
91
P80/SI1
E
General-purpose CMOS I/O port.
The pin is shared with UART/SIO data input.
92
P81/SO1
F
General-purpose CMOS I/O port.
The pin is shared with UART/SIO data output.
93
P82/SCK1
E
General-purpose CMOS I/O port.
The pin is shared with UART/SIO clock I/O.
59 ~ 74
SEG0 ~
SEG15
I
LCD segment output-only pin.
55 ~ 56
COM0 ~
COM1
I
LCD common output-only pin.
54, 53, 52
V1 to V3
—
LCD driving power supply pin.
1,51
VCC
—
Power supply pin.
50,100
VSS
—
Power supply pin (GND).
30
AVCC
—
A/D converter power supply pin.
29
AVR
—
A/D converter reference voltage input pin.
31
AVSS
—
A/D converter power supply pin.
Use at the same voltage level as VSS.
MQFP*1/QFP*2
*1: MQP-100C-P01
*2: FPT-100P-M06
8
Function
MB89490 Series
• External EPROM Socket (MB89PV490 only)
Pin
number
Pin
name
I/O
102
131
130
103
127
124
128
129
104
105
106
107
108
109
110
111
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins.
122
121
120
119
118
115
114
113
O8
O7
O6
O5
O4
O3
O2
O1
I
Data input pins.
101
112
117
126
N.C.
—
Internally connected pins. Always leave open.
116
VSS
O
Power supply pin (GND).
123
CE
O
Chip enable pin for the EPROM. Outputs “H” in standby mode.
125
OE
O
Output enable pin for the EPROM. Always outputs “L”.
132
VCC
O
Power supply pin for the EPROM.
Function
MQFP*1
*1: MQP-100C-P01
9
MB89490 Series
■ I/O CIRCUIT TYPE
Circuit
Class
Circuit
Remarks
X1 (X1A)
N-ch P-ch
P-ch
X0 (X0A)
A
N-ch
• Main/Sub-clock circuit
N-ch
Stop mode control signal
B
• Hysteresis input (CMOS input in
MB89F499)
• The pull-down resistor (not
available in MB89F499)
Approx. 50kΩ
R
R
P-ch
• The pull-up resistor (P-channel)
Approx. 50 kΩ
• Hysteresis input
C
N-ch
pull-up
resistor register
R
P-ch
P-ch
D
N-ch
•
•
•
•
CMOS output
IOH=-4mA, IOL=12mA
CMOS input
Selectable pull-up resistor
Approx. 50 kΩ
•
•
•
•
•
CMOS output
IOH=-2mA, IOL=4mA
CMOS port input
Hysteresis resource input
Selectable pull-up resistor
Approx. 50 kΩ
port
pull-up
resistor register
R
P-ch
E
P-ch
N-ch
port
resource
(Continued)
10
MB89490 Series
(Continued)
pull-up
resistor register
R
P-ch
•
•
•
•
P-ch
F
N-ch
CMOS output
IOH=-2mA, IOL=4mA
CMOS input
Selectable pull-up resistor
Approx. 50 kΩ
port
pull-up
resistor register
R
P-ch
G
•
•
•
•
P-ch
N-ch
port
resource
CMOS output
IOH=-2mA, IOL=4mA
CMOS port input
Automotive (VIH=0.85Vcc, VIL=0.5Vcc)
resource input
• Analog input
• Selectable pull-up resistor
Approx. 50 kΩ
analog
H
N-ch
port / resource
•
•
•
•
•
N-ch open-drain output
IOL=15mA
CMOS port input
CMOS resource input
5V tolerance
P-ch
N-ch
I
• LCD segment output
P-ch
N-ch
J
• CMOS input
11
MB89490 Series
■
HANDLING DEVICES
1. Preventing Latch-up
Latch-up may occur on CMOS ICs if voltage higher than V CC or lower than VSS is applied to input and output
pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in “■ Electrical Characteristics” is applied between V CC and VSS.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR), and analog input from exceeding the digital
power supply (V CC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D is not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is
therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations
(P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the
transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power
is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up
from stop mode.
7. Treatment of Unused dedicated LCD pins
When dedicated LCD pins are not in use, keep them open.
12
MB89490 Series
■ PROGRAMMING AND ERASING FLASH MEMORY ON THE MB89F499
1. Flash Memory
The flash memory is located between 1000H and FFFFH in the CPU memory map and incorporates a flash
memory interface circuit that allows read access and program access from the CPU to be performed in the same
way as mask ROM. Programming and erasing flash memory is also performed via the flash memory interface
circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the
control of the CPU, providing an efficient method of updating program and data.
2. Flash Memory Features
• 60 K byte × 8-bit configuration (16 K + 8 K + 8 K + 28 K sectors)
• Automatic programming algorithm (Embedded algorithm* : Equivalent to MBM29LV200)
• Includes an erase pause and restart function
• Data polling and toggle bit for detection of program/erase completion
• Detection of program/erase completion via CPU interrupt
• Compatible with JEDEC-standard commands
• Sector Protection (sectors can be combined in any combination)
• No. of program/erase cycles : 10,000 (Min)
*: Embedded Algorithm is a trademark of Advanced Micro Devices.
3. Procedure for Programming and Erasing Flash Memory
Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or
erase flash memory, the program must first be copied from flash memory to RAM so that programming can be
performed without program access from flash memory.
4. Flash Memory Register
• Control status register (FMCS)
Address
007AH
Bit 7
Bit 6
Bit 5
Bit 4
INTE
RDYINT
WE
RDY
R/W
R/W
R/W
R
Bit 3
Bit 2
Reserved Reserved
R/W
R/W
Bit 1
Bit 0
Initial value
—
Reserved
000X00-0 B
—
R/W
5. Sector Configuration
The table below shows the sector configuration of flash memory and lists the addresses of each sector for both
during CPU access a flash memory programming.
• Sector configuration of flash memory
Flash Memory
CPU Address
Programmer Address*
16 K bytes
FFFFH to C000H
1FFFFH to 1C000H
8 K bytes
BFFFH to A000H
1BFFFH to 1A000H
8 K bytes
9FFFH to 8000H
19FFFH to 18000H
28 K bytes
7FFFH to 1000H
17FFFH to 11000H
13
MB89490 Series
* : Programmer address
The programmer address is the address to be used instead of the CPU address when programming data
from a parallel flash memory programmer. Use the programmer address on programming or erasing using
a general purpose parallel programmer.
6. ROM Programmer Adaptor and Recommended ROM Programmers
Part number
MB89F499PF
Package
FPT-100P-M06
* Enquiries
Sunhayato Co. Ltd. : FAX +81-3-5396-9106
Ando Denki Co. Ltd. : TEL +81-44-549-7300
14
Adaptor Part No.
Recommended Programmer
Manufacturer and Model
Sun Hayato Co. Ltd.
Ando Denki Co. Ltd.
TBD
AF9708 (ver 1.60 or later)
AF9709 (ver 1.60 or later)
MB89490 Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C512-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
Adapter socket part number
LCC-32 (Rectangle)
ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3986-0403
3. Memory Space
Memory space in each mode is shown in the diagram below.
Address
Normal operating mode
Corresponding addresses on the EPROM programmer
0000H
I/O
0080H
RAM
0880H
1000H
Not available
1000H
PROM
60KB
FFFFH
EPROM
60KB
FFFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C512.
(2) Load program data into the EPROM programmer at 1000H to FFFFH.
(3) Program to 1000H to FFFFH with the EPROM programmer.
15
MB89490 Series
■ Block Diagram
Main clock
oscillator
X0
X1
21-bit timebase
timer
AVcc
AVss
AVR
Clock controller
10-bit
A/D converter
Reset circuit
(Watchdog timer)
RST
CMOS I/O port
External interrupt 1
(level)
Watch prescaler
8/16-bit
timer/counter 00,01
P22/EC0
P20/TO0
P25/EC1
P24/TO1
8/16-bit
timer/counter 10,11
8
Port 1
8
8
External interrupt 0
(edge)
P47/SDA
P46/SCL
6
N-ch open-drain I/O port
UART/SIO
P82/SCK1
P81/SO1
P80/SI1
P52/SCK0
P51/SO0
P50/SI0
SIO
CMOS I/O port
2
2
P54/COM3
to P53/COM2
CMOS I/O port
Port 0*1
CMOS I/O port
16 SEG0
t0 SEG15
LCD controller/driver
2
F2MC-8L
CPU
16
ROM (32K bytes / 48K bytes)
Other pins
Vcc x 2, Vss x 2, MOD0
*1: High current I/O port.
COM0
to COM1
3 V1
to V3
32 × 4-bit display
RAM (16 bytes)
CMOS I/O port
Port 6, 7
RAM (1K bytes / 2K bytes)
P45 to P40
P84
P83
CMOS I/O port
Port 8
Remote receiver
P21/RMC
Internal data bus
Port 2
8-bit PWM timer 1
Port 4*1
I2C
8-bit PWM timer 0
P27/PWM1
16
P37/AN7/INT17
to
P30/AN0/INT10
8
Port 5
P26/PWM0
P07 to P00
8
CMOS I/O port
P23
P17/INT07 to
P10/INT00
8
Port 3
Sub-clock
oscillator
(PLL x 1,2,4)
X0A
X1A
8
P67/SEG23
to P60/SEG16
8
P77/SEG31
to P70/SEG24
MB89490 Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89490 series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89490 series is structured as illustrated below.
Memory Space
MB89498
MB89497
0000 H
0000 H
0080 H
0100 H
0200H
Generalpurpose
registers
0200H
0880H
0480 H
0080H
RAM
RAM
0100H
0100 H
Generalpurpose
registers
I/O
I/O
0080 H
RAM
RAM
0100 H
MB89PV490
0000H
0000 H
I/O
I/O
0080 H
MB89F499
0200H
Generalpurpose
registers
0880H
0200H
0880H
Vacant
Vacant
1000H
Vacant
Generalpurpose
registers
1000 H
Vacant
FLASH
(60K)
External
ROM
(60K)
4000H
8000H
FFC0H
FFFFH
ROM
FFC0H
FFFFH
ROM
FFC0 H
FFFFH
FFC0H
FFFFH
Vector table (reset, interrupt, vector call instruction)
17
MB89490 Series
2. Registers
The F 2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following registers are provided:
Program counter (PC):
A 16-bit register for indicating instruction storage positions.
Accumulator (A):
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T):
A 16-bit register for performing arithmetic operations with the accumulator.
When the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX):
A 16-bit register for index modification.
Extra pointer (EP):
A 16-bit pointer for indicating a memory address.
Stack pointer (SP):
A 16-bit register for indicating a stack area.
Program status (PS):
A 16-bit register for storing a register pointer, a condition code.
Initial value
16 bits
PC
FFFDH
: Program counter
A
: Accumulator
Undefined
T
: Temporary accumulator
Undefined
IX
: Index register
Undefined
EP
: Extra pointer
Undefined
SP
: Stack pointer
Undefined
PS
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
PS
14
13
12
RP
10
9
8
Vacancy Vacancy Vacancy
RP
18
11
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
MB89490 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set to "1" when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Clear
to "0" otherwise. This flag is for decimal adjustment instructions.
I-flag:
Interrupt is allowed when this flag is set to "1". Interrupt is prohibited when the flag is set to "0". Clear to "0"
when reset.
IL1, 0:
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
Priority
High
1
Low = no interrupt
N-flag: Set to "1" if the MSB is set to "1" as the result of an arithmetic operation. Clear to "0" otherwise.
Z-flag:
Set to "1" when an arithmetic operation results in "0". Clear to "0" otherwise.
V-flag:
Set to "1" if a signed numeric value overflows because of an arithmetic calculation. Clear to "0" if the
overflow does not occur.
C-flag: Set to "1" when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Clear to
"0" otherwise. Set to the shift-out value in the case of a shift instruction.
19
MB89490 Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers. Up to a total of 32 banks can be used on the MB89490 series. The bank currently in use is
indicated by the register bank pointer (RP).
Register Bank Configuration
This address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
32 banks
Memory area
20
MB89490 Series
■ I/O MAP
Address
Register name
Register description
00H
PDR0
Port 0 data register
01H
DDR0
Port 0 data direction register
02H
PDR1
Port 1 data register
03H
DDR1
Port 1 data direction register
04H
PDR2
Port 2 data register
05H
Read/Write
Initial value
R/W
XXXXXXXX B
W*
00000000B
R/W
XXXXXXXX B
W*
00000000B
R/W
00000000B
(Reserved)
06H
DDR2
Port 2 data direction register
R/W
00000000B
07H
SYCC
System clock control register
R/W
X-1MM100B
08H
STBC
Standby control register
R/W
00010XXXB
09H
WDTC
Watchdog timer control register
W*
0---XXXXB
0AH
TBTC
Timebase timer control register
R/W
00---000B
0BH
WPCR
Watch prescaler control register
R/W
00--0000B
0C H
PDR3
Port 3 data register
R/W
XXXXXXXX B
0D H
DDR3
Port 3 data direction register
R/W
00000000B
0EH
RSFR
Reset flag register
R
XXXX---- B
0FH
PDR4
Port 4 data register
R/W
11111111B
10H
PDR5
Port 5 data register
R/W
---XXXXX B
11H
DDR5
Port 5 data direction register
R/W
---00000B
12H
PDR6
Port 6 data register
R/W
XXXXXXXX B
13H
DDR6
Port 6 data direction register
R/W
00000000B
14H
PDR7
Port 7 data register
R/W
XXXXXXXX B
15H
DDR7
Port 7 data direction register
R/W
00000000B
16H
PDR8
Port 8 data register
R/W
---XXXXX B
17H
DDR8
Port 8 data direction register
R/W
---00000B
18H
EIC0
External interrupt 0 control register 0
R/W
00000000B
19H
EIC1
External interrupt 0 control register 1
R/W
00000000B
1AH
EIC2
External interrupt 0 control register 2
R/W
00000000B
1BH
EIC3
External interrupt 0 control register 3
R/W
00000000B
1C H
EIE1
External interrupt 1 enable register
R/W
00000000B
1D H
EIF1
External interrupt 1 flag register
R/W
-------0 B
1EH
SMR
Serial mode register
R/W
00000000B
1FH
SDR
Serial data register
R/W
XXXXXXXX B
20H
T01CR
Timer 01 control register
R/W
000000X0B
21H
T00CR
Timer 00 control register
R/W
000000X0B
22H
T01DR
Timer 01 data register
R/W
XXXXXXXX B
23H
T00DR
Timer 00 data register
R/W
XXXXXXXX B
24H
T11CR
Timer 11 control register
R/W
000000X0B
25H
T10CR
Timer 10 control register
R/W
000000X0B
(Continued)
21
MB89490 Series
(Continued)
Address
Register name
Register description
Read/Write
Initial value
26H
T11DR
Timer 11 data register
R/W
XXXXXXXXB
27H
T10DR
Timer 10 data register
R/W
XXXXXXXXB
28H
ADER
A/D input enable register
R/W
11111111B
29H
ADC0
A/D control register 0
R/W
-00000X0B
2AH
ADC1
A/D control register 1
R/W
-0000001B
2BH
ADDH
A/D data register (Upper byte)
R
------XXB
2CH
ADDL
A/D data register (Lower byte)
R
XXXXXXXXB
2DH
CNTR0
PWM 0 timer control register
R/W
0-000000B
2EH
COMR0
PWM 0 timer compare register
W*
XXXXXXXXB
2FH
SMC0
UART/SIO serial mode control register
R/W
00000000B
30H
SMC1
UART/SIO serial mode control register
R/W
00000000B
31H
SSD
UART/SIO serial status/data register
R/W
00001---B
32H
SIDR/SODR
33H
SRC
34H
35H
UART/SIO serial data register
R/W
XXXXXXXXB
UART/SIO serial rate control register
R/W
XXXXXXXXB
CNTR1
PWM 1 timer control register
R/W
0-000000B
COMR1
PWM 1 timer compare register
W*
XXXXXXXXB
2
R
00000000B
2
36H
IBSR
37H
IBCR
I C bus control register
R/W
00000000B
38H
ICCR
I2C clock control register
R/W
000XXXXXB
39H
IADR
I2C address register
R/W
XXXXXXXXB
I C data register
R/W
XXXXXXXXB
Sub PLL control register
R/W
----0000B
3AH
IDAR
3BH
PLLCR
I C bus status register
2
3CH to 3FH
(Reserved)
40H
RMN
Remote control counter register
R
XXXXXXXXB
41H
RMC
Remote control control register
R/W
00000000B
42H
RMS
Remote control status register
R/W
0X000001B
43H
RMD
Remote control FIFO data register
R
X----XXXB
44H
RMCD0
Remote control compare register 0
R/W
11111111B
45H
RMCD1
Remote control compare register 1
R/W
11111111B
46H
RMCD2
Remote control compare register 2
R/W
11111111B
47H
RMCD3
Remote control compare register 3
R/W
11111111B
48H
RMCD4
Remote control compare register 4
R/W
11111111B
49H
RMCD5
Remote control compare register 5
R/W
11111111B
4AH
RMCI
Remote interrupt register
R/W
-110-000B
5EH
LOCR
LCD controller output control register
R/W
-0000000B
5FH
LCD
LCD controller control register
R/W
00010000B
60H to 6FH
VRAM
LCD data RAM
R/W
XXXXXXXXB
70H
PURC0
Port 0 pull up resistor control register
R/W
11111111B
71H
PURC1
Port 1 pull up resistor control register
R/W
11111111B
4BH to 5DH
(Reserved)
(Continued)
22
MB89490 Series
(Continued)
Address
Register name
Read/Write
Initial value
72H
PURC2
Port 2 pull up resistor control register
Register description
R/W
11111111B
73H
PURC3
Port 3 pull up resistor control register
R/W
11111111B
74H
PURC5
Port 5 pull up resistor control register
R/W
---11111B
75H
PURC6
Port 6 pull up resistor control register
R/W
11111111B
76H
PURC7
Port 7 pull up resistor control register
R/W
11111111B
77H
PURC8
Port 8 pull up resistor control register
R/W
-----111B
78H to 79H
(Reserved)
7AH
FMCS
R/W
000X00-0B
7BH
ILR1
Interrupt level setting register 1
Flash memory control status registger
W*
11111111B
7CH
ILR2
Interrupt level setting register 2
W*
11111111B
7DH
ILR3
Interrupt level setting register 3
W*
11111111B
7EH
ILR4
Interrupt level setting register 4
W*
11111111B
7FH
(Reserved)
* Bit manipulation instruction cannot be used.
● Read/write access symbols
R/W : Readable and writable
R : Read-only
W : Write-only
● Initial value symbols
0: The initial value of this bit is “0”.
1: The initial value of this bit is “1”.
X: The initial value of this bit is undefined.
- : Unused bit.
M: The initial value of this bit is determined by mask option.
23
MB89490 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
AV CC
VSS – 0.3
VSS + 4.0
V
AVR
VSS – 0.3
VSS + 4.0
V
V1 to V3
VSS – 0.3
VCC
V
VSS – 0.3
VCC + 0.3
V
other than P40~P47
VSS – 0.3
VSS + 6.0
V
P40~P47 in MB89PV490,
MB89497/498
VSS – 0.3
VSS + 5.5
V
P40~P47 in MB89F499
VSS – 0.3
VCC + 0.3
V
“L” level maximum output current IOL

15
mA
“L” level average output current
IOLAV

4
mA
“L” level total maximum output
current
åIOL

100
mA
“L” level total average output
current
åIOLAV

40
mA
“H” level maximum output current
IOH

–15
mA
“H” level average output current
IOHAV

–4
mA
“H” level total maximum output
current
åIOH

–50
mA
“H” level total average output
current
åIOHAV

–20
mA
Power consumption
PD

300
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
Power supply voltage
LCD power supply voltage
Input voltage
Output voltage
VI
VO
AVCC must be equal to VCC
Average value (operating current
× operating rate)
Average value (operating current
× operating rate)
Average value (operating current
× operating rate)
Average value (operating current
× operating rate)
Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
24
MB89490 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Symbol
Parameter
Value
Unit
Remarks
Min.
Max.
2.7*
3.6
V
Operation assurance
range
MB89PV490,
MB89F499
2.2*
3.6
V
Operation assurance
range
MB89497,
MB89498
1.5
3.6
V
Retains the RAM state in
stop mode
AVR
2.7
3.6
V
LCD power supply voltage
V1 to V3
Vss
Vcc
V
Operating temperature
TA
–40
+85
°C
VCC
AVCC
Power supply voltage
* : These values depend on the operating conditions and the analog assurance range. See Figure 1, 2 and
“5. A/D Converter Electrical Characteristics.”
Operating
voltage (V)
3.6
Analog accuracy
assurance range :
Vcc = AVcc = 2.7V~3.6V
3.0
2.7
2.2
2.0
Main clock
operating freq. (MHz)
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0 12.0 12.5
4.0
2.0
1.33
1.0
0.8
0.66
0.57
0.50
0.44
0.4
0.36 0.33 0.32
Min execution
time (inst. cycle) (µs)
Note : The shaded area is not assured for MB89F499
Figure 1
Operating Voltage vs. Main Clock Operating Frequency (MB89F499/497/498)
25
MB89490 Series
Operating
voltage (V)
3.6
3.5
Analog accuracy
assurance range :
Vcc = AVcc = 2.7V~3.6V
3.0
2.7
Main clock
operating Freq. (MHz)
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0 12.0 12.5
4.0
2.0
1.33
1.0
0.8
0.66
0.57
0.50
0.44
0.4
0.36 0.33 0.32
Figure 2
Min execution
time (inst. cycle) (µs)
Operating Voltage vs. Main Clock Operating Frequency (MB89PV490)
Figure 1 and 2 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH.
Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating
speed is switched using a gear.
26
MB89490 Series
3. DC Characteristics
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
VIH
“H” level
input voltage
Pin
P00 ~ P07,
P10 ~ P17,
P20 ~ P27,
P30 ~ P37,
P50 ~ P54,
P60 ~ P67,
P70 ~ P77,
P80 ~ P84,
SCL, SDA,
MOD1, MOD2
P40 ~ P47
Value
Unit
Remarks
Min.
Typ.
Max.
—
0.7 V CC
—
VCC + 0.3
V
—
0.7 V CC
—
VSS + 6.0
V
MB89PV490,
MB89497/498
—
0.7 V CC
—
VSS + 5.5
V
MB89F499
VIHS
RST, MOD0, EC0,
EC1, SCK0, SI0,
SCK1, SI1, RMC,
INT00 ~ INT07
—
0.8 V CC
—
VCC + 0.3
V
VIHA
INT10 ~ INT17
—
0.85 VCC
—
VCC + 0.3
V
VIL
P00 ~ P07,
P10 ~ P17,
P20 ~ P27,
P30 ~ P37,
P40 ~ P47,
P50 ~ P54,
P60 ~ P67,
P70 ~ P77,
P80 ~ P84,
SCL, SDA,
MOD1, MOD2
—
VSS − 0.3
—
0.3 VCC
V
VILS
RST, MOD0, EC0,
EC1, SCK0, SI0,
SCK1, SI1, RMC,
INT00 ~ INT07
—
VSS − 0.3
—
0.2 VCC
V
VILA
INT10 ~ INT17
—
VSS − 0.3
—
0.5 VCC
V
—
VSS + 6.0
V
P40 ~ P47
VSS − 0.3
—
VD
MB89PV490,
MB89497/498
—
VSS − 0.3
—
VSS + 5.5
V
MB89F499
“L” level
input voltage
Open-drain
output pin
application
voltage
Condition
“H” level
VOH
output voltage
P10
P20
P30
P50
P60
P70
P80
~ P17,
~ P27,
~ P37,
~ P54,
~ P67,
~ P77,
~ P82
IOH = -2.0 mA
2.2
—
—
V
P00 ~ P07
IOH = -4.0 mA
2.2
—
—
V
(Continued)
27
MB89490 Series
(Continued)
Parameter
Symbol
“L” level
VOL
output voltage
Input leakage
current
ILI
Pin
Condition
Value
Unit
Min.
Typ.
Max.
IOL = 4.0 mA
—
—
0.4
V
P00 ~ P07
IOL = 12.0 mA
—
—
0.4
V
P40 ~ P47
IOL = 15.0 mA
—
—
0.4
V
P00 ~
P10 ~
P20 ~
P30 ~
P40 ~
P50 ~
P60 ~
P70 ~
P80 ~
0.45 V < VI < VCC
−5
—
+5
µA
P10 ~
P20 ~
P30 ~
P50 ~
P60 ~
P70 ~
P80 ~
P17,
P27,
P37,
P54,
P67,
P77,
P82, RST
P07,
P17,
P27,
P37,
P47,
P54,
P67,
P77,
P84
Open-drain
output leakage ILOD
current
P40 ~ P47
0.0 V < VI < VCC
−5
—
+5
µA
Pull-down
resistance
RDOWN
MOD0
VI = VCC
25
50
100
kΩ
Pull-up
resistance
RPULL
P00 ~
P10 ~
P20 ~
P30 ~
P50 ~
P60 ~
P70 ~
P80 ~
RST
Common
output
impedance
RVCOM
Segment
output
impedance
RVSEG
LCD divided
RLCD
resistance
LCD
controller/
driver
leakage
current
ILCDL
P07,
P17,
P27,
P37,
P54,
P67,
P77,
P82,
Remarks
Without
pull-up
resistor
Except
MB89F499
When pull-up
resistor is
selected
(except RST)
VI = 0.0 V
25
50
100
kΩ
COM0 to COM3
V1 to V3 = +3.0 V
—
—
2.5
kΩ
SEG0 to SEG31
V1 to V3 = +3.0 V
—
—
15
kΩ
—
Between V CC and
VSS
300
500
750
kΩ
V1 to V3,
COM0 to COM3,
SEG0 to SEG31
—
-1
—
+1
µA
(Continued)
28
MB89490 Series
(Continued)
Parameter
Symbol
Pin
ICC1
ICC2
ICCS1
ICCS2
ICCL
VCC
Power supply
current
TBD
mA
MB89PV490,
MB89497/498
6.0
TBD
mA
MB89F499
—
0.4
TBD
mA
MB89PV490,
MB89497/498
—
1.5
TBD
mA
MB89F499
FCH = 10 MHz
tinst = 0.4 µs
Main clock sleep mode
—
1.2
TBD
mA
MB89PV490,
MB89497/498
—
2.0
TBD
mA
MB89F499
FCH = 10 MHz
tinst = 6.4 µs
Main clock sleep mode
—
0.4
TBD
mA
MB89PV490,
MB89497/498
—
1.0
TBD
mA
MB89F499
FCL = 32.768 kHz
Sub-clock mode
TA = +250C
—
22.0
TBD
µA
MB89PV490,
MB89497/498
—
35.0
TBD
µA
MB89F499
—
120.0
TBD
µA
MB89PV490,
MB89497/498
—
150.0
TBD
µA
MB89F499
—
7.0
TBD
µA
MB89PV490,
MB89497/498
—
15.0
TBD
µA
MB89F499
—
1.0
TBD
µA
MB89PV490,
MB89497/498
—
5.0
TBD
µA
MB89F499
—
0.8
TBD
µA
MB89PV490,
MB89497/498
—
1.0
TBD
µA
MB89F499
AVcc = 3.0 V, TA = +25 C
—
1.0
3.0
mA
A/D converting
TA = +250C
—
0.8
4.0
µA
A/D stop
—
10.0
—
pF
Max.
FCH = 10 MHz
tinst = 0.4 µs
Main clock run mode
—
3.5
—
FCH = 10 MHz
tinst = 6.4 µs
Main clock run mode
FCL = 32.768 kHz
Watch mode
Main clock stop mode
TA = +250C
ICCT
TA = +250C
Sub-clock stop mode
ICCH
0
IA
CIN
Remarks
Typ.
FCL = 32.768 kHz
Sub-clock sleep mode
TA = +250C
ICCLS
Input
capacitance
Unit
Min.
FCL = 32.768 kHz
Sub-clock mode
TA = +250C
sub PLL x 4
ICCLPLL
IAH
Value
Condition
AV cc
Other than
VCC , VSS, AVCC, f = 1 MHz
AV SS, AVR
29
MB89490 Series
4. AC Characteristics
(1) Reset Timing
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
Symbol
Parameter
RST “L” pulse width
tZLZH
—
48 tHCYL
—
ns
Note: tHCYL is the oscillation cycle (1/FCH) to input to the X0 pin.
The MCU operation is not guaranteed when the "L" pulse width is shorter than tZLZH.
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(AV SS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Power supply rising time
tR
Power supply cut-off time
tOFF
Condition
—
Value
Unit
Min.
Max.
—
50
ms
1
—
ms
Remarks
Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time.
Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to
be varied in the course of operation, a smooth voltage rise is recommended.
tR
tOFF
1.5 V
VCC
30
0.2 V
0.2 V
0.2 V
MB89490 Series
(3) Clock Timing
(AV SS = VSS = 0.0 V, TA = –40°C to +85°C)
Symbol
Parameter
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rising/falling time
Value
Pin
Min.
Typ.
Max.
Unit
FCH
X0, X1
1
—
12.5
MHz
FCL
X0A, X1A
—
32.768
75
kHz
tHCYL
X0, X1
80
—
1000
ns
tLCYL
X0A, X1A
13.3
30.5
—
µs
PWH
PWL
X0
20
—
—
ns
PWHL
PWLL
X0A
—
15.2
—
µs
tCR
tCF
X0, X0A
—
—
10
ns
Remarks
External clock
X0 and X1 Timing and Conditions
tHCYL
PWH
PWL
tCR
tCF
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
Main Clock Conditions
When a crystal
or
ceramic reasonator is used
X0
When an external clock is used
X1
X0
X1
Open
FCH
C1
C2
FCH
31
MB89490 Series
Sub-clock Timing and Conditions
tLCYL
0.8 VCC
X0A
0.2 VCC
PWHL
PWLL
tCR
tCF
Sub-clock Conditions
When a crystal
or
ceramic oscillator is used
X0A
X0A
X 1A
FCL
When an external clock is used
X1A
Rd
X0A
Open
X1A
Open
FCL
C0
When subclock is not used
C1
(4) Instruction Cycle
Parameter
Instruction cycle
(minimum execution time)
32
Symbol
Value
Unit
Remarks
4/F CH, 8/FCH, 16/FCH, 64/FCH
µs
(4/FCH)tinst = 0.32 µs when operating
at FCH = 12.5 MHz
2/FCL, 1/2FCL
µs
(2/FCL)tinst = 61.036 µs when
operating at FCL = 32.768 kHz
tinst
MB89490 Series
PLL operation guarantee range (subPLL x 4)
Relationship between internal operating clock frequency and power supply voltage
Operating
voltage (V)
subPLL operating guarantee range
3.6
3.0
2.7
2.5
2.0
Internal operating clock freq. (kHz)
131.072
300
15.625
Min execution
time (inst. cycle) (µs)
6.67
Not assured for MB89F499, MB89PV490.
Instruction cylcle, Tinst (min. exec. time)
(us)
Relationship between subclock oscillating frequency and instruction cycle when
subPLL is enabled
15.625
Multipliedby-4
6.67
32.768
75
Oscillation clock FCL (kHz)
33
MB89490 Series
(5) Serial I/O Timing
Parameter
Serial clock cycle time
(AVCC = VCC = 3.0 V, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Pin
Condition
Unit
Min.
Max.
Symbol
tSCYC
2 tinst*
—
µs
–200
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
1 tinst*
—
µs
1 tinst*
—
µs
0
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
SCK0, SCK1
SCK ↓ → SO time
tSLOV
SCK0, SCK1, SO0, SO1
Valid SI → SCK ↑
tIVSH
SI0, SI1, SCK0, SCK1
SCK ↑ → valid SI hold time
tSHIX
SCK0, SCK1, SI0, SI1
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
SCK ↓ → SO time
tSLOV
SCK0, SCK1, SO0, SO1
Valid SI → SCK ↑
tIVSH
SI0, SI1, SCK0, SCK1
SCK ↑ → valid SI hold time
tSHIX
SCK0, SCK1, SI0, SI1
Internal
shift clock
mode
SCK0, SCK1
External
shift clock
mode
* : For information on tinst, see “(4) Instruction Cycle.”
Internal Clock Operation
tSCYC
SCK0, SCK1
2.4 V
0.8 V
0.8 V
tSLOV
SO0, SO1
2.4 V
0.8 V
tIVSH
SI0, SI1
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
External Clock Operation
tSLSH
tSHSL
SCK0, SCK1
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
SO0, SO1
2.4 V
0.8 V
tIVSH
SI0, SI1
34
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
MB89490 Series
(6) I2C Timing
Symbol
Parameter
Pin
Start condition output tSTA
SCL
SDA
Stop condition output tSTO
SCL
SDA
Condition
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
Start condition detect tSTA
Stop condition detect tSTO
(Vcc = 3.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit Remarks
Min.
Max.
master
1/4tinst x
1/4tinst*1 x
ns
mode
M x N + 20
M x N - 20
1/4tinst x
1/4tinst x
master
ns
(M*2 x N*3 + 8) +
(M x N + 8) - 20
mode
20
1/4tinst x 6 + 40
—
ns
1/4tinst x 6 + 40
—
ns
Re-start condition
1/4tinst x
1/4tinst x
master
tSTASU
ns
output
(M x N + 8) - 20 (M x N + 8) + 20
mode
Re-start condition
—
ns
1/4tinst x 4 + 40
tSTASU
detect
1/4tinst x
SCL output LOW
1/4tinst x
master
SCL
tLOW
ns
width
M x N - 20
M x N + 20
mode
1/4tinst x
1/4tinst x
master
SCL output HIGH
SCL
ns
tHIGH
(M x N + 8) - 20 (M x N + 8) + 20
mode
width
SDA
1/4tinst x 4 - 20
1/4tinst x 4 + 20
ns
SDA output delay
tDO
SDA output setup
tDOSU
SDA
1/4tinst x 4 - 20
—
ns
*4
time after interrupt
SCL input LOW
SCL
1/4tinst x 6 + 40
—
ns
tLOW
pulse width
SCL input HIGH
SCL
1/4 tinst x 2 + 40
—
ns
tHIGH
pulse width
SDA input setup time tSU
SDA
40
—
ns
SDA hold time
tHO
SDA
0
—
ns
*1: For information in tinst, see "(4) Instruction Cycle".
*2: M is defined in the ICCR CS4 and CS3 (bit 4 to bit 3). For details, please refer to the H/W manual register
explanation.
*3: N is defined in the ICCR CS2 to CS0 (bit 2 to bit 0)
*4: When the interrupt period is grater than SCL "L" width, SDA and SCL output (Standard) value is based on
hypothesis when rising time is 0 ns.
Data transmit (master/slave)
tDO
tSU
tDO
SDA
tHO
tDOSU
ACK
tSTASU
tSTA
tLOW
tHO
SCL
1
9
Data receive (master/slave)
tSU
tHO
tDO
SDA
tDOSU
ACK
tHIGH
SCL
tDO
6
7
tLOW
tSTO
8
9
35
MB89490 Series
(7) Peripheral Input Timing
Parameter
(AVCC = V CC = 3.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin
Unit
Remarks
Min.
Max.
Symbol
Peripheral input “H” pulse width 1
tILIH1
Peripheral input “L” pulse width 1
tIHIL1
EC0, EC1, RMC, INT00 ~
INT07, INT10 ~ INT17
2 tinst*
—
µs
2 tinst*
—
µs
* : For information on tinst, see “(4) Instruction Cycle.”
t IHIL1
EC0, EC1, RMC,
INT00 ~ INT07
t ILIH1
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
t IHIL1
t ILIH1
INT10 to INT17
0.85 VCC
0.5 VCC
36
0.5 VCC
0.85 VCC
MB89490 Series
5. A/D Converter Electrical Characteristics
(1) A/D Converter Electrical Characteristics
(AVCC = VCC = 2.7 V ~ 3.6 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Resolution
Total error
—
Linearity error
Differential linearity error
—
Value
Unit
Min.
Typ.
Max.
—
10
—
bit
—
—
±3.0
LSB
—
—
±2.5
LSB
—
—
±1.9
LSB
Zero transition voltage
VOT
AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB
mV
Full-scale transition
voltage
VFST
AVCC – 3.5 LSB AVCC – 1.5 LSB AVCC - 0.5 LSB
mV
A/D mode conversion time
—
Analog port input current
IAIN
Analog input voltage
VAIN
Reference voltage
Reference voltage supply
current
AN0 to
AN7
—
IR
IRH
AVR
Remarks
—
—
38 tinst*
µs
—
—
10
µA
AVSS
—
AVR
V
AVSS + 2.7
—
AVCC
V
—
200
TBD
µA
A/D is
activated
—
—
5
µA
A/D is
stopped
* : For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics".
(2) A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
The deviation of the straight line connecting the zero transition point ("00 0000 0000" ↔ "00 0000 0001") with
the full-scale transition point ("11 1111 1111" ↔ "11 1111 1110") from actual conversion characteristics.
• Differential linearity error (unit: LSB)
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value.
• Total error (unit: LSB)
The difference between theoretical and actual conversion values.
37
MB89490 Series
Theoretical I/O characteristics
3FF
Total error
3FF
VFST
3FE
3FE
3FD
1.5 LSB
Digital output
Digital output
3FD
004
003
Actual conversion
value
{1 LSB × N + VOT}
004
VNT
003
VOT
002
Actual conversion
value
002
1 LSB
Theoretical value
001
001
0.5 LSB
AVCC
AVSS
1 LSB =
Analog input
VFST – VOT
1022
Total error = VNT – {1 LSB × N + 0.5 LSB}
1 LSB
(V)
Zero transition error
Full-scale transition error
004
Theoretical value
Actual conversion
value
3FF
Actual conversion
value
Digital output
003
Digital output
AVCC
AVSS
Analog input
002
3FE
VFST
(Actual
measurement)
3FD
Actual conversion
value
001
Actual conversion value
3FC
VOT (Actual measurement)
AVCC
AVSS
Analog input
Analog input
Differential linearity error
Linearity error
3FF
Theoretical value
Actual conversion
value
3FE
N+1
{1 LSB × N + VOT}
Actual conversion
value
VNT
VFST
(Actual
measurement)
004
Digital output
Digital output
3FD
V(N + 1)T
N
N–1
003
VNT
Actual conversion value
Actual conversion value
002
Theoretical value
001
N–2
VOT (Actual measurement)
AVCC
AVSS
Analog input
Linearity error =
38
VNT – {1 LSB × N + VOT}
1 LSB
AVCC
AVSS
Analog input
Differential linearity error =
V(N + 1)T – VNT
1 LSB
–1
MB89490 Series
(3) Notes on Using A/D Converter
• Input impedance of the analog input pins
The A/D converter used for the MB89490 series contains a sample and hold circuit as illustrated below to fetch
analog input voltage into the sample and hold capacitor for 16 instruction cycles after activation A/D conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low.
Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about
0.1 µF for the analog input pin.
Sample hold circuit
Analog Input Circuit Model
Analog input pin
Comparator
If the analog input
impedance is higher
than 10 kΩ, it is
recommended to
connect an external
capacitor of approx.
0.1 µF.
R
C
Close for 16 instruction cycles after
activating A/D conversion.
Analog channel selector
R: analog input equivalent resistance
C: analog input equivalent capacitance
MB89F499
2.4 kΩ
52 pF
MB89PV490/MB89497/MB89498
2.4 kΩ
53 pF
39
MB89490 Series
■ MASK OPTIONS
Part number
No.
1
40
MB89497
Specifying procedure
Selection of oscillation
stabilization time (OSC)
• The initial value of the
oscillation stabilization OSC
time for the main clock
1
can be set by
2
3
selecting the values of
the WTM1 and WTM0
bit on the right.
MB89498
Specify when
ordering mask
MB89F499
MB89PV490
Setting not possible
Selectable
: 210/FCH
: 214/FCH
: 218/FCH
Fixed to oscillation
stabilization time of 218/FCH
MB89490 Series
■ ORDERING INFORMATION
Part number
MB89497PF
MB89498PF
MB89F499PF
MB89PV490CF
Package
Remarks
100-pin Plastic QFP
(FPT-100P-M06)
100-pin Ceramic MQFP
(MQP-100C-P01)
41
MB89490 Series
■ PACKAGE DIMENSIONS
100-pin Plastic QFP
FPT-100P-M06
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
"A"
C
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8°
31
2001 FUJITSU LIMITED F100008S-c-4-4
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches)
(Continued)
42
MB89490 Series
(Continued)
100-pin ceramic MQFP
MQP-100C-P01
18.70(.736)TYP
INDEX AREA
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.35(.486)TYP
+0.40
1.20 –0.20
.047
0.65±0.15
(.0256±.0060)
+.016
–.008
0.65±0.15
(.0256±.0060)
1.27±0.13
(.050±.005)
22.30±0.33
(.878±.013)
24.70(.972)
TYP
0.30(.012)
TYP
1.27±0.13
(.050±.005)
18.12±0.20
12.02(.473)
(.713±.008)
TYP
10.16(.400)
14.22(.560)
TYP
TYP
0.30(.012)TYP
7.62(.300)TYP
0.30±0.08
(.012±.003)
18.85(.742)
TYP
0.30±0.08
(.012±.003)
+0.40
1.20 –0.20
+.016
.047 –.008
9.48(.373)TYP
11.68(.460)TYP
10.82(.426)
0.15±0.05 MAX
(.006±.002)
C
1994 FUJITSU LIMITED M100001SC-1-2
43
MB89490 Series
MEMO
44
MB89490 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Marketing Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3353
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fma.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fme.fujitsu.com/
All Rights Reserved.
The contents of this document are subject to change
without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device
applications, and are not intended to be incorporated in
devices for actual use. Also, FUJITSU is unable to assume
responsibility for infringement of any patent rights or other
rights of third parties arising from the use of this
information or circuit diagrams.
The products described in this document are designed,
developed and manufactured as contemplated for general
use, including without limitation, ordinary industrial use,
general office use, personal use, and household use, but
are not designed, developed and manufactured as
contemplated (1) for use accompanying fatal risks or
dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead
directly to death, personal injury, severe physical damage
or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass
transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and
artificial satellite).
Please note that Fujitsu will not be liable against you and/
or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-6281-0770
Fax: +65-6281-0220
http://www.fmal.fujitsu.com/
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss
from such failures by incorporating safety design
measures into your facility and equipment such as
redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Korea
If any products described in this document represent
goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law
of Japan, the prior authorization by Japanese government
will be required for export of those products from Japan.
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
F0208
ã FUJITSU LIMITED Printed in Japan
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