FUJITSU MB89530A

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12547-5E
8-bit Microcontroller
CMOS
F2MC-8L MB89530A Series
MB89535A/537A/537AC/538A/538AC/F538
MB89P538/PV530
■ DESCRIPTION
The MB89530A series is a one-chip microcontroller featuring the F2MC-8L core supporting low-voltage and highspeed operation. Built-in peripheral functions include timers, serial interface, A/D converter, and external interrupt.
This product is an ideal general-purpose one-chip microcontroller for a wide variety of applications from household
to industrial equipment, as well as use in portable devices.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• Wide range of package options
• QFP package (1.00 mm pitch)
• Two types of LQFP packages (0.65 mm pitch, 0.50 mm pitch)
• SH-DIP package (1.778 mm pitch)
• BCC package (0.50 mm pitch)
• Low voltage, high-speed operating capability
Minimum instruction execution time 0.32 µs (at base oscillator 12.5 MHz)
• F2MC-8L CPU Core
• Instruction set optimized for controller operation
• Multiplication/division instructions
• 16-bit calculation
• Branching instructions with bit testing
• Bit operation instructions, etc.
(Continued)
Copyright©2001-2007 FUJITSU LIMITED All rights reserved
MB89530A Series
(Continued)
• Five timer systems
• 8-bit PWM timer with 2 channels (usable as either interval timer of PWM timer)
• Pulse width count timer (supports continuous measurement or remote control receiving applications)
• 16-bit timer counter
• 21-bit time base timer
• Watch prescaler (17-bit)
• UART
Synchronous or asynchronous operation, switchable
• 2 serial interfaces (Serial I/O)
Selection of transfer direction (specify MSB first or LSB first) for communication with a variety of devices
• 10-bit A/D converter (8 channels)
• External clock input for startup support
• Time base timer output for startup support (except MB89F538)
• Pulse generators (PPG) with 2-program capability
• 6-bit PPG with selection of pulse width and pulse period
• 12-bit PPG (2 channels) with selection of pulse width and pulse period
• I2C* interface circuits
• External interrupt 1 (single-clock system : 4 channels, dual-clock system : 3 channels)
4 or 3 independent inputs, release enabled from standby mode (includes edge detection function)
• External interrupt 2 (except for MB89F538 : 8 channels, MB89F538 : 7 channels)
8 or 7 independent input, release enabled form standby mode (includes level edge detection function)
• Standby modes (low power consumption modes)
• Stop mode (oscillator stops, virtually no power consumed)
• Sleep mode (CPU stops, power consumption reduced to one-third)
• Sub clock mode
• Watch mode
• Watchdog timer reset
• I/O ports
• Maximum ports
Single-clock system : Except MB89F538 53 ports
: MB89F538
52 ports
Dual-clock system : Except MB89F538 51 ports
: MB89F538
50 ports
• 38 general-purpose I/O ports (CMOS) (MB89F538 : 37 general-purpose I/O ports)
• 2 general-purpose I/O ports (N-ch open drain)
• 8 general-purpose output ports (N-ch open drain)
• General-purpose input ports (CMOS) : single-clock system : 5 ports, dual-clock system : 3 ports
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as defined
by Philips.
2
MB89530A Series
■ PRODUCT LINEUP
Part number
MB89535A
Parameter
Type
MB89537A/ MB89538A/
537AC
538AC
Mass produced (MASK ROM)
MB89F538
MB89P538
MB89PV530
Flash product
One-time
programmable
product
Evaluation
product
ROM capacity
48 Kbytes ×
48 Kbytes ×
16 Kbytes × 32 Kbytes × 48 Kbytes ×
8-bit
8-bit
8-bit
8-bit
8-bit
(built-in Flash)
(built-in ROM) 48 Kbytes × 8-bit
(built-in
(built-in
(built-in
(write from
(write from
(external ROM) *2
ROM)
ROM)
ROM)
general purpose general purpose
EPROM writer) EPROM writer)
RAM capacity
512 bytes ×
8-bit
Operating
voltage
2.2 V to 5.5 V *1
(MB89535A/537A/538A/537AC/538AC)
CPU functions
Basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Minimum interrupt processing time
1 Kbyte ×
8-bit
2 Kbytes × 8-bit
3.5 V to 5.5 V
2.7 V to 5.5 V
2.7 V to 5.5 V
: 136
: 8 bits
: 1 bit to 3 bits
: 1, 8, 16 bits
: 0.32 µs / 12.5 MHz
: 2.88 µs / 12.5 MHz
Peripheral functions
Input ports
Ports
: single-clock system : 5 (4 also usable as external interrupts)
dual-clock system
: 3 (3 also usable as external interrupts)
Output-only ports (N-ch open drain)
: 8 (8 also usable as A/D converter input)
I/O ports (N-ch open drain) : 2 (2 also usable as SO2/SDA or SI2/SCL)
I/O ports (CMOS) (Except MB89F538)
: 38
I/O ports (CMOS) (MB89F538)
: 37 (21 have no other function)
Total (except MB89F538) : single-clock system : 53
dual-clock system : 51
Total (MB89F538)
: single-clock system : 52
dual-clock system : 50
Time base
timer
21 bits
Interrupt periods at main clock oscillation frequency of 12.5 MHz
(approx. 0.655 ms, 2.621 ms, 20.97 ms, 335.5 ms)
Watchdog
timer
Reset period of approx. 167.8 ms to 335.6 ms at main clock frequency of 12.5 MHz
Reset period of approx. 500 ms to 1000 ms at sub clock frequency of 32.768 kHz.
PWM timer
8-bit interval timer operation
(supports square wave output, operating clock period : 1, 8, 16, 64 tinst*3)
Pulse width measurement with 8-bit resolution (conversion period : 28 tinst*3 to 28 × 64 tinst*3)
2 channels (can also be used as interval timer, can also be used as ch.1 output and ch.2 count
clock)
Watch prescaler
Interval times at 17-bit sub clock base frequency of 32.768 kHz
(approx. 31.25 ms, 0.25 s, 0.50 s, 1.00 s, 2.00 s, 4.00 s)
(Continued)
3
MB89530A Series
(Continued)
Part number
MB89535A
Parameter
MB89537A/
537AC
MB89538A/
538AC
MB89F538
MB89P538
MB89PV530
Peripheral functions
8-bit one-shot timer operation
(supports underflow output, operating clock period : 1, 4, 32 tinst*3, external)
8-bit reload timer operation
Pulse width
(supports square wave output, operating clock period : 1, 4, 32 tinst*3, external)
count timer
8-bit pulse width measurement operation
(continuous measurement, “H” width measurement, “L” width measurement, ↑ to ↑, ↓ to ↓, “H”
width measurement and ↑ to↑)
16-bit timer operation (operating clock period : 1 tinst*3, external)
16-bit timer/
16-bit event counter operation (select rising, falling, or both edges)
counter
16-bit × 1 channel
8 bits length
Serial I/O
Selection of LSB first or MSB first
Transfer clock (2, 8, 32 tinst*3, external)
CLK synchronous/CLK asynchronous data transfer capability (8, 9-bit with parity bit, or 7,8-bit
UART/SIO
without parity bit) .
Built-in baud rate generator provides selection of 14 baud rate settings.
CLK synchronous/CLK asynchronous data transfer capability (4, 6, 7, 8-bit with parity bit, or 5,
7, 8, 9-bit without parity bit) .
UART
Built-in baud rate generator provides selection of 14 baud rate settings.
External clock output, 2-channel 8-bit PWM timer output also available for baud rate
settings.
Single-clock system : 4 channels independent, dual-clock system : 3 channels independent.
External
Selection of rising, falling, or both edge detection.
interrupt 1
Can be used for recovery from standby mode (edge detection also available in stop mode)
External
Except MB89F538 : 8 channels, MB89F538 : 7 channels
interrupt 2
Can be used for recovery from standby mode.
6-bit PPG,
Can generate square wave signals with programmable period.
12-bit PPG
6-bit × 1 channel or 12-bit × 2 channels.
1-channel , compatible with Intel System Administrator bus version 1.0 and
I2C bus
⎯
Philips I2C specifications.
interface
2-line communications (on MB89PV530/P538/F538/537AC/538AC)
10-bit resolution × 8 channels.
A/D conversion functions (conversion time : 60 tinst*3)
A/D converter Supports repeated calls from external clock (except MB89F538) .
Supports repeated calls from internal clock.
Standard voltage input provided (AVR)
Standby modes
(power saving
Sleep mode, stop mode, sub clock mode, watch mode.
modes)
Process
CMOS
*1 : Depends on operating frequency.
*2 : Using external ROM and MBM27C512.
*3 : tinst represents instruction execution time. This can be selected as 1/4, 1/8, 1/16, 1/64 of the main clock cycle
or 1/2 of the sub clock cycle.
Note : MB89535A/537A/538A have no built-in I2C functions.
To use I2C functions, choose the MB89PV530/MB89P538/F538/537AC/538AC.
4
MB89530A Series
■ MODEL DIFFERENCES AND SELECTION CONSIDERATIONS
Part number
MB89535A
Package
MB89537A/
537AC
MB89538A/
538AC
MB89F538
MB89P538
MB89PV530
DIP-64P-M01
FPT-64P-M03
FPT-64P-M06
FPT-64P-M09
LCC-64P-M19
LCC-64P-M16
*
MDP-64C-P02
MQP-64C-P01
: Model-package combination available
: Model-package combination not available
* : Only for ES
Conversion sockets for pin pitch conversion (manufactured by Sunhayato Corp.) can be used.
Contact : Sunhayato Corp. :
TEL
: +81-3-3984-7791
FAX
: +81-3-3971-0535
Advanced Interconnectics : http://www.advantest.co.jp/en-index.shtml
5
MB89530A Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Capacity
When this product is used in an evaluation product or other evaluation configuration, it is necessary to carefully
confirm the differences between the model being used and the product it is evaluating. Particular attention should
be given to the following (Refer to “ CPU CORE 1.Memory Space”) .
• The program ROM area starts from address 4000H on the MB89F538, MB89P538 and MB89PV530 models.
• Note upper limits on RAM, such as stack areas, etc.
2. Current Consumption
• On the MB89PV530, the additional current consumed by the EPROM is added at the connecting socket on
the back side.
• When operating at low speed, the current consumption in the one-time PROM or EPROM models is greater
than on the MASK ROM models. However, current consumption in sleep or stop modes is identical.
For details, refer to “ ELECTRICAL CHARACTERISTICS”.
3. Mask Options
The options available for use, and the method of specifying options, differ according to the model. Before use,
check the “ MASK OPTIONS” specification section.
4. Wild Register Functions
The following table shows areas in which wild register functions can be used.
Wild Register Usage Areas
Part number
6
Address space
MB89PV530
4000H to FFFFH
MB89P538
4000H to FFFFH
MB89F538
4000H to FFFFH
MB89537A/537AC
8000H to FFFFH
MB89538A/538AC
4000H to FFFFH
MB89535A
C000H to FFFFH
MB89530A Series
■ PIN ASSIGNMENTS
(TOP VIEW)
P36/WTO
P37/PTO1
P40/INT20/EC
P41/INT21/SCK2
P42/INT22/SO2/SDA
P43/INT23/SI2/SCL
P44/INT24/UCK2
P45/INT25/UO2
P46/INT26/UI2
P47/INT27/ADST/MOD2*1
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT10
P61/INT11
P62/INT12
P63/INT13/X0A*2
P64/X1A*2
RST
MOD0
MOD1
X0
X1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
*4
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O1
O2
O3
VSS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
92
91
90
89
88
87
86
85
84
83
82
81
80
79
VCC
A14
A13
A8
A9
A11
OE
A10
CE
O8
O7
O6
O5
O4
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
P35/PWC
P34/PTO2
P33/SI1 (UI1)
P32/SO1 (UO1)
P31/SCK1 (UCK1) /LMCO
P30/PPG03/MCO
C/N.C. *3
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20/PWCK
P21/PPG01
P22/PPG02
P23
P24
P25
P26
P27
(DIP-64P-M01)
(MDP-64C-P02)
*1 : Pin 10 is MOD2 pin for MB89F538 and P47/INT27/ADST pins except for MB89F538.
*2 : Pin 25 and pin 26 are P63/INT13, P64 pins for single-clock system and X0A, X1A pins for dual-clock
system.
*3 : The function of pin 57 depends on the model. For details, refer to “■PIN DESCRIPTIONS” and
“■HANDLING DEVICES”.
*4 : Package top pin assignments (MB89PV530 only)
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
65
A15
73
A1
81
O6
89
A8
66
A12
74
A0
82
O7
90
A13
67
A7
75
O1
83
O8
91
A14
68
A6
76
O2
84
CE
92
VCC
69
A5
77
O3
85
A10
70
A4
78
VSS
86
OE
71
A3
79
O4
87
A11
72
A2
80
O5
88
A9
N.C. : Internal connection only. Not for use.
(Continued)
7
MB89530A Series
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P45/INT25/UO2
P44/INT24/UCK2
P43/INT23/SI2/SCL
P42/INT22/SO2/SDA
P41/INT21/SCK2
P40/INT20/EC
P37/PTO1
P36/WTO
VCC
P35/PWC
P34/PTO2
P33/SI1 (UI1)
P32/SO1 (UO1)
P31/SCK1 (UCK1) /LMCO
P30/PPG03/MCO
C/N.C.*3
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P63/INT13/X0A*2
P64/X1A*2
RST
MOD0
MOD1
X0
X1
VSS
P27
P26
P25
P24
P23
P22/PPG02
P21/PPG01
P20/PWCK
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P46/INT26/UI2
P47/INT27/ADST/MOD2*1
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT10
P61/INT11
P62/INT12
(FPT-64P-M03)
(FPT-64P-M09)
*1 : Pin 2 is MOD2 pin for MB89F538 and P47/INT27/ADST pins except for MB89F538.
*2 : Pin 17 and pin 18 are P63/INT13, P64 pins for single-clock system and X0A, X1A pins for dual-clock
system.
*3 : The function of pin 49 depends on the model. For details, refer to “■PIN DESCRIPTIONS” and
“■HANDLING DEVICES”.
(Continued)
8
MB89530A Series
64
63
62
61
60
59
58
57
56
55
54
53
52
P44/INT24/UCK2
P43/INT23/SI2/SCL
P42/INT22/SO2/SDA
P41/INT21/SCK2
P40/INT20/EC
P37/PTO1
P36/WTO
VCC
P35/PWC
P34/PTO2
P33/SI1 (UI1)
P32/SO1/ (UO1)
P31/SCK1 (UCK1) /LMCO
(TOP VIEW)
84
83
82
81
80
79
78
*4
85
86
87
88
89
90
91
92
93
77
76
75
74
73
72
71
70
69
94
95
96
65
66
67
68
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P30/PPG03/MCO
C/N.C.*3
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20/PWCK
RST
MOD0
MOD1
X0
X1
VSS
P27
P26
P25
P24
P23
P22/PPG02
P21/PPG01
20
21
22
23
24
25
26
27
28
29
30
31
32
P45/INT25/UO2
P46/INT26/UI2
P47/INT27/ADST/MOD2*1
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT10
P61/INT11
P62/INT12
P63/INT13/X0A*2
P64/X1A*2
(FPT-64P-M06)
(MQP-64C-P01)
*1 : Pin 3 is MOD2 pin for MB89F538 and P47/INT27/ADST pins except for MB89F538.
*2 : Pin 18 and pin 19 are P63/INT13, P64 pins for single-clock system and X0A, X1A pins for dual-clock
system.
*3 : The function of pin 50 depends on the model. For details, refer to “■PIN DESCRIPTIONS” and
“■HANDLING DEVICES”.
*4 : Package top pin assignments (MB89PV530 only)
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
65
N.C.
73
A2
81
N.C.
89
OE
66
A15
74
A1
82
O4
90
N.C.
67
A12
75
A0
83
O5
91
A11
68
A7
76
N.C.
84
O6
92
A9
69
A6
77
O1
85
O7
93
A8
70
A5
78
O2
86
O8
94
A13
95
A14
71
A4
79
O3
87
CE
72
A3
80
VSS
88
A10
96
VCC
N.C. : Internal connection only. Not for use.
(Continued)
9
MB89530A Series
(Continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P63/INT13/X0A∗2
P64/X1A∗2
RST
MOD0
MOD1
X0
X1
VSS
P27
P26
P25
P24
P23
P22/PPG02
P21/PPG01
P20/PWCK
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P46/INT26/UI2
P47/INT27/ADST/MOD2∗1
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT10
P61/INT11
P62/INT12
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P45/INT25/UO2
P44/INT24/UCK2
P43/INT23/SI2/SCL
P42/INT22/SO2/SDA
P41/INT21/SCK2
P40/INT20/EC
P37/PTO1
P36/WTO
VCC
P35/PWC
P34/PTO2
P33/SI1 (UI1)
P32/SO1 (UO1)
P31/SCK1 (UCK1) /LMCO
P30/PPG03/MCO
C/NC∗3
(TOP VIEW)
(LCC-64P-M19)
(LCC-64P-M16) *4
*1 : Pin 2 is MOD2 pin for MB89F538 and P47/INT27/ADST pins except for MB89F538.
*2 : Pin 17 and 18 are P63/INT13, P64 pins for single-clock system and X0A, X1A pins for dual-clock system.
*3 : The function of pin 49 depends on the model. For details, refer to “■PIN DESCRIPTIONS” and
“■HANDLING DEVICES”.
*4 : Only for ES
10
MB89530A Series
■ PIN DESCRIPTIONS
Pin no.
SH-DIP*
MDIP*2
1
30
QFP*3
MQFP*4
LQFP*5
BCC*6
Pin name
23
22
X0
31
24
23
X1
28
21
20
MOD0
29
22
21
MOD1
I/O
circuit
type*7
Function
A
Connecting pins to crystal oscillator circuit or other
oscillator circuit. The X0 pin can connect to an external
clock. In that case, X1 is left open.
B
Input pins for memory access mode setting.
Connect directly to Vss.
27
20
19
RST
C
Reset I/O pin. This pin has pull-up resistance with
CMOS I/O or hysteresis input. At an internal reset
request, an ’L’ signal is output. An ’L’ level input
initializes the internal circuits.
56 to 49
49 to 42
48 to 41
P00 to P07
D
General purpose I/O ports.
48 to 41
41 to 34
40 to 33
P10 to P17
D
General purpose I/O ports.
40
33
32
P20/PWCK
E
General purpose I/O port.Resource I/O pin (hysteresis
input).Hysteresis input. This pin also functions as a
PWC input.
39
32
31
P21/
PPG01
D
General purpose I/O port.This pin also functions as the
PPG01 output.
38
31
30
P22/
PPG02
D
General purpose I/O port.This pin also functions as the
PPG02 output.
37
30
29
P23
D
General purpose I/O port.
36
29
28
P24
D
General purpose I/O port.
35
28
27
P25
D
General purpose I/O port.
34
27
26
P26
D
General purpose I/O port.
33
26
25
P27
D
General purpose I/O port.
58
51
50
P30/
PPG03/
MCO
D
General purpose I/O port.This pin also functions as the
PPG03 output.
59
52
51
P31/SCK1
(UCK1) /
LMCO
E
General purpose I/O port.Resource I/O pin (hysteresis
input).This pin also functions as the UART/SIO clock
input/output pin.
60
53
52
P32/SO1
(UO1)
D
General purpose I/O port.This pin also functions as the
UART/SIO data output pin.
61
54
53
P33/SI1
(UI1)
E
General purpose I/O port.Resource input/output pin
(hysteresis input).This pin also functions as the UART/
SIO serial data input pin.
62
55
54
P34/PTO2
D
General purpose I/O port.This pin also functions as the
PWM timer 2 output pin.
63
56
55
P35/PWC
E
General purpose I/O port.Resource I/O pin (hysteresis
input).This pin also functions as a PWC input.
(Continued)
11
MB89530A Series
Pin no.
1
3
5
Pin
name
I/O
circuit
type*7
Function
QFP*
MQFP*4
LQFP*
BCC*6
1
58
57
P36/
WTO
D
General purpose I/O port.Resource output.
This pin also functions as the PWC output pin.
2
59
58
P37/
PTO1
D
General purpose I/O port.Resource output.
This pin also functions as the PWM timer 1 output pin.
3
60
59
P40/
INT20/
EC
E
General purpose I/O port.Resource I/O pin (hysteresis
input).This pin also functions as an external interrupt
input or 16-bit timer/counter input.
4
61
60
P41/
INT21/
SCK2
E
General purpose I/O port.Resource I/O pin (hysteresis
input).This pin also functions as an external interrupt
input or SIO clock I/O pin.
61
P42/
INT22/
SO2/
SDA
G
N-ch open drain output.
Resource I/O pin (hysteresis only for INT22 input) .
This pin also functions as an external interrupt input,
SIO serial data output, or I2C data line.
62
P43/
INT23/
SI2/SCL
G
N-ch open drain output.
Resource I/O pin (hysteresis only for INT23 input) .
This pin also functions as an external interrupt, SIO
serial data input, or I2C clock I/O pin.
63
P44/
INT24/
UCK2
E
General purpose I/O port.
Resource I/O pin (hysteresis input) .
This pin also functions as an external interrupt input or
UART clock I/O pin.
64
P45/
INT25/
UO2
E
General purpose I/O port.
Resource I/O pin (hysteresis input) .
This pin also functions as an external interrupt input or
UART data output pin.
1
P46/
INT26/
UI2
E
General purpose I/O port.
Resource I/O pin (hysteresis input) .
This pin also functions as an external interrupt input or
UART data input pin.
SH-DIP*
MDIP*2
5
6
7
8
9
10
11 to 18
62
63
64
1
2
3
4 to 11
P47/
INT27/
ADST
E
MOD2
B
P50/AN0
to P57/
AN7
H
2
3 to 10
Except MB89F538
General purpose I/O port.
Resource I/O pin (hysteresis input) .
This pin also functions as an external interrupt input or
A/D converter clock input pin.
MB89F538
Input pins for memory access mode setting.
Connect directly to Vss.
N-ch open drain output port.
This pin also functions as an A/D converter analog input
pin.
(Continued)
12
MB89530A Series
(Continued)
Pin no.
SH-DIP*
MDIP*2
1
22 to 24
25
QFP*
MQFP*4
5
LQFP*
BCC*6
Pin name
I/O
circuit
type*7
Function
15 to 17
14 to 16
P60/INT10
to
P62/INT12
I
General purpose input port.
Resource input pin (hysteresis input) .
This pin also functions as an external interrupt input pin.
3
18
17
P63/INT13
I
Single-clock system
General purpose input port.
Resource input (hysteresis
input) .
This pin also functions as an
external interrupt.
X0A
A
Dual-clock system
Connected pin for sub clock.
P64
J
Single-clock system
General purpose input port.
X1A
A
Dual-clock system
Connected pin for sub clock.
26
19
18
64
57
56
VCC
⎯
Power supply pin.
32
25
24
VSS
⎯
Ground pin (GND) .
19
12
11
AVCC
⎯
A/D converter power supply pin.
20
13
12
AVR
⎯
A/D converter reference voltage input pin.
21
14
13
AVSS
⎯
A/D converter power supply pin.
Used at the same voltage level as the Vss supply.
57
50
49
C
⎯
MB89F538
Capacitor connection pin for
stabilization power supply.
Connect an external ceramic
capacitor of approximately
0.1 µF.
MB89P538
If “Available” is selected for
the step-down circuit
stabilization time, VCC is fixed.
If “Unavailable” is selected for
the step-down circuit
stabilization time, VSS is fixed.
MB89PV530
MB89537A/537AC
MB89538A/538AC
MB89535A
N.C. pin
*1 : DIP-64P-M01
*2 : MDP-64C-P02
*3 : FPT-64P-M06
*4 : MQP-64C-P01
*5 : FPT-64P-M03/M09
*6 : LCC-64P-M19/M16
*7 : For I/O circuit type, refer to “ ■I/O CIRCUIT TYPE” .
13
MB89530A Series
External EPROM Socket Pin Function Descriptions (MB89PV530 only)
Pin no.
I/O Circuit
Pin name
1
2
type*3
MQFP*
MDIP*
65
66
67
68
69
70
71
72
73
74
66
67
68
69
70
71
72
73
74
75
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins.
75
76
77
77
78
79
O1
O2
O3
I
Data input pins
78
80
VSS
O
Power supply pin (GND) .
79
80
81
82
83
82
83
84
85
86
O4
O5
O6
O7
O8
I
Data input pins.
84
87
CE
O
ROM chip enable pin.
Outputs an “H” level signal in standby mode.
85
88
A10
O
Address output pin.
86
89
OE
O
ROM output enable pin.
Outputs “L” at all times.
87
88
89
91
92
93
A11
A9
A8
O
90
94
A13
O
91
95
A14
O
92
96
VCC
O
EPROM power supply pin.
⎯
65
76
81
90
N.C.
O
Internally connected.
These pins always left open.
Address output pins.
*1 : MDP-64C-P02
*2 : MQP-64C-P01
*3 : For I/O circuit type, refer to “ ■I/O CIRCUIT TYPE” .
14
Function
MB89530A Series
■ I/O CIRCUIT TYPES
Type
Circuit
X1 (X1A)
N-ch
A
Remarks
Clock input
P-ch
Oscillator feedback resistance
• High speed side = approx. 1 MΩ
• Low speed side = approx. 10 MΩ
P-ch
X0 (X0A)
N-ch
Standby control
Mode input
B
R
• Hysteresis input
• Pull-down resistance built-in to
MB89535A
MB89537A/537AC
MB89538A/538AC
• Pull-up resistance approx. 50 kΩ
• Hysteresis input
R
P-ch
Reset output
C
N-ch
Reset input
R
Pull-up control
resistor
P-ch
P-ch
D
N-ch
• CMOS I/O
• Software pull-up resistance can be
used. Approx. 50 kΩ
Digital output
Digital output
Port input
R
Pull-up control
resistors
P-ch
P-ch
• CMOS I/O
• Software pull-up resistance can be
used. Approx. 50 kΩ
Digital output
E
N-ch
Digital output
Port input
Resource input
(Continued)
15
MB89530A Series
(Continued)
Type
Circuit
N-ch
G
Remarks
Digital output
• N-ch open drain output
• Hysteresis input
• CMOS input
Resource input
Port input
• N-ch open drain output
• Analog input (A/D converter)
P-ch
H
N-ch
Digital output
Analog input
R
P-ch
Pull-up control resistors
I
• Hysteresis input
• CMOS input
• Software pull-up resistance can be
used. Approx. 50 kΩ
Resource
Port
R
P-ch
Pull-up control resistors
J
Port
16
• CMOS input
• Software pull-up resistance can be
used. Approx. 50 kΩ
MB89530A Series
■ HANDLING DEVICES
1. Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded (to prevent latch-up) . When
CMOS integrated circuit devices are subjected to applied voltages higher than Vcc at input and output pins (other
than medium- and high-withstand voltage pins), or to voltages lower than Vss, as well as when voltages in excess
of rated levels are applied between Vcc and Vss, the phenomenon known as latch-up can occur.
When a latch-up condition occurs, supply current can increase dramatically and may destroy semiconductor
elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings.
Also when switching power on or off to analog systems, care must be taken that analog power supplies (AVCC,
AVR) and analog input signals do not exceed the level of the digital power supply.
2. Power Supply Voltage Fluctuations
Even within the warranted operating range of the Vcc supply voltage, sudden changes in supply voltage can
cause abnormal operation. As a measure for stability, it is recommended that the Vcc ripple fluctuation (peak to
peak value) should be kept within 10% of the reference Vcc value on commercial power supply (50 Hz/60 Hz),
and instantaneous voltage fluctuations such as at power-on and shutdown should be kept within a transient
variability limit of 0.1V/ms.
3. Treatment of Unused Input Pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected
to pull-up or pull-down resistance.
4. Treatment of N.C. Pins
Any pins marked ’NC’ (not connected) must be left open.
5. Treatment of Power Supply Pins on Models with Built-in A/D Converter
Even when A/D converters are not in use, pins should be connected so that AVCC = VCC, and AVSS = AVR = VSS.
6. Precautions for Use of External Clock
Even when an external clock signal is used, an oscillator stabilization wait period is used after a power-on reset,
or escape from sub clock mode or stop mode.
7. Execution of Programs on RAM
Debugging of programs executed on RAM cannot be performed even when using the MB89PV530.
8. Wild Register Functions
Wild registers cannot be debugged with the MB89PV530 and tools. To verify operations, actual in-device testing
on the MB89P538 or MB89F538 is advised.
17
MB89530A Series
9. Details on handling the C terminal of the MB89530 series
The MB89530 series contains the following products. The regulator integrated model and the regulator-less
model have different performance characteristics.
Part No.
Operation Voltage
integrated model
Terminal type
Terminal treatments
MB89PV530
MB89P538
MB89F538
Not included
2.7 V to 5.5 V
N.C. terminal
Included
Fixed to VCC
Not included
3.5 V to 5.5 V
Included
2.2 V to 5.5 V
Not included
Not required
C terminal
Fixed to VSS
0.1 µF capacitor
connected
MB89537A/537AC
MB89538A/538AC
N.C. terminal
Not required
MB89535A
Although these product models have the same internal resources, the operation sequence after a power-on
reset is different between the regulator integrated model and regulator-less model.
The operation sequence after a power-on reset of each model is shown below.
Power supply (VCC)
Voltage step-down circuit stabilization time
+ oscillation stabilization time
(219/FCH) + (218/FCH)
CPU operation of regulator
integrated model (MB89F538 only)
Oscillation stabilization time (218/FCH)
CPU operation of regulator-less
model (exclude MB89F538)
CPU started on regulator-less
model (Reset vector)
CPU started on regulator
integrated model (Reset vector)
FCH : Crystal oscillator frequency
As above, the regulator integrated model starts the CPU behind the regulator-less model. This is because the
regulator requires a settling time for normal operation.
The MB89P538 offers a choice of regulator-integrated and regulator-less models selectable depending on the
C-terminal treatment. Use the right one for your mask board.
10. Note to Noise in the External Reset Pin (RST)
If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST).
18
MB89530A Series
■ PROGRAMMING AND ERASING FLASH MEMORY ON THE MB89F538
1. Flash Memory
The flash memory is located between 4000H and FFFFH in the CPU memory map and incorporates a flash
memory interface circuit that allows read access and program access from the CPU to be performed in the same
way as MASK ROM. Programming and erasing flash memory is also performed via the flash memory interface
circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the
control of the CPU, providing an efficient method of updating program and data.
2. Flash Memory Features
•
•
•
•
•
•
•
•
48 Kbytes × 8-bit configuration (16 Kbytes + 8 Kbytes + 8 Kbytes + 16 Kbytes sectors)
Automatic programming algorithm (Embedded algorithm* : Equivalent to MBM29LV200)
Includes an erase pause and restart function
Data polling and toggle bit for detection of program/erase completion
Detection of program/erase completion via CPU interrupt
Compatible with JEDEC-standard commands
Sector Protection (sectors can be combined in any combination)
No. of program/erase cycles : 10,000 (Min)
*: Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.
3. Procedure for Programming and Erasing Flash Memory
Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or
erase flash memory, the program must first be copied from flash memory to RAM so that programming can be
performed without program access from flash memory.
4. Flash Memory Register
• Flash memory control status register (FMCS)
Address
bit7
007AH
bit6
bit5
bit4
INTE RDYINT
WE
RDY
R/W
R/W
R
R/W
bit3
bit2
Reserved Reserved
R/W
R/W
bit0
Initial value
⎯
Reserved
000X00-0B
⎯
R/W
bit1
5. Sector Configuration
The table below shows the sector configuration of flash memory and lists the addresses of each sector for both
during CPU access a flash memory programming.
• Sector configuration of flash memory
Flash Memory
CPU Address
Programmer Address*
16 Kbytes
FFFFH to C000H
1FFFFH to 1C000H
8 Kbytes
BFFFH to A000H
1BFFFH to 1A000H
8 Kbytes
9FFFH to 8000H
19FFFH to 18000H
16 Kbytes
7FFFH to 4000H
17FFFH to 14000H
* : Programmer address
The programmer address is the address to be used instead of the CPU address when programming data from
a parallel flash memory programmer. Use the programmer address on programming or erasing using a generalpurpose parallel programmer.
19
MB89530A Series
6. ROM Programmer Adaptor and Recommended ROM Programmers
Part number
Package
Adaptor Part No.
Recommended Programmer
Manufacturer and Model
Sunhayato Corp.
Flash Support Group, Inc.
MB89F538-101PF
MB89F538-201PF
FPT-64P-M06
Flash-64QF-32DP-8LF
MB89F538-101PFM
MB89F538-201PFM
FPT-64P-M09
Flash-64QF2-32DP-8LF2
MB89F538-101P-SH
MB89F538-201P-SH
DIP-64P-M01
Flash-64SD-32DP-8LF
AF9708*
AF9709*
* : For the version of the programmer, contact the Flash Support Group, Inc.
• Enquiries
Sunhayato Corp. : TEL
: +81-3-3984-7791
FAX
: +81-3-3971-0535
Advanced Interconnectics : http://www.advantest.co.jp/en-index.shtml
Flash Support Group, Inc. : FAX
: +81-53-428-8377
E-mail : [email protected]
20
MB89530A Series
■ ONE-TIME WRITING SPECIFICATIONS WITH PROM AND EPROM MICROCONTROLLERS
The MB89P538 has a PROM mode with functions equivalent to the MBM27C1001, allowing writing with a general
purpose ROM writer using a proprietary adapter. Note, however, that the use of electronic signature mode is
not supported.
• ROM writer adapters
With some ROM writers, stability of writing performance is enhanced by placing an 0.1 µF capacitor between
the Vcc and Vss pins. The following table lists adapters for use with ROM writers.
ROM Writer Adapters
Part number
Package
Compatible adapter
MB89P538-101PF
MB89P538-201PF
FPT-64P-M06
ROM-64QF-32DP-8LA2*1
MB89P538-101PFM
MB89P538-201PFM
FPT-64P-M09
ROM-64QF2-32DP-8LA
MB89P538-101P-SH
MB89P538-201P-SH
DIP-64P-M01
ROM-64SD-32DP-8LA2*1
LCC-64P-M16*2
ROM-64BCC-32DP-8LA-FJ
MB89P538-101PV
MB89P538-201PV
Inquiries should be addressed to Sunhayato Corp. :
TEL
: +81-3-3984-7791
FAX
: +81-3-3971-0535
Advanced Interconnectics : http://www.advantest.co.jp/en-index.shtml
*1 : Version 3 or later should be used.
*2 : Only for ES
• Memory map for EPROM mode
The following illustration shows a memory map for EPROM mode. There are no PROM options.
Normal operating mode
0000H
EPROM mode (corresponding
addresses on EPROM writer)
0000H
I/O
0080H
RAM
0100H
0200H
0880H
General
purpose
register
Prohibited
Prohibited
4000H
4000H
Program
(EPROM)
ROM
FFFFH
FFFFH
Prohibited
1FFFFH
21
MB89530A Series
• Recommended screening conditions
Before one-time writing of microcontroller programs to PROM, high temperature aging is recommended as a
screening process for chips before they are mounted.
Program, verify
High temperature aging
+150 °C, 48h
Read
Mount
• About writing yields
The nature of chips before one-time writing of microcontroller programs to PROM prevents the use of all-bit
writing tests. Therefore it is not possible to guarantee writing yields of 100% in some cases.
22
MB89530A Series
■ EPROM WRITING TO PIGGY-BACK/EVALUATION CHIPS
This section describes methods of writing to EPROM on piggy-back/evaluation chips.
• EPROM model
MBM27C512-20TV
• Writer adapter
For writing to EPROM using a ROM writer, use one of the writer adapters shown below (manufactured by
Sunhayato Corp.) .
Package
Adapter socket model
LCC-32 (rectangular)
ROM-32LC-28DP-YG
Inquiries should be addressed to Sunhayato Corp. :
TEL
: +81-3-3984-7791
FAX
: +81-3-3971-0535
Advanced Interconnectics : http://www.advantest.co.jp/en-index.shtml
• Memory Space
Normal operating mode
0000H
(Corresponding address on
ROM writer)
0000H
I/O
0080H
Prohibited
RAM
0880H
Prohibited
4000H
4000H
PROM
48 Kbytes
FFFFH
EPROM
FFFFH
• Writing to EPROM
1) Set up the EPROM writer for the MBM27C512.
2) Load program data to the ERPOM writer, in the area 4000H to FFFFH.
3) Use the EPROM writer to write to the area 4000H to FFFFH.
23
MB89530A Series
Low voltage
oscillator circuit
(32.786 kHz)
P64/X1A*1
CMOS I/O port
Port 0
Sub clock
P63/INT13/X0A*1
8
Port 1
■ BLOCK DIAGRAM
8
P00 to P07
Port 6
Clock control
Watch prescaler
4
CMOS I/O port
CMOS I/O port
Main clock
6-bit PPF03
P31/SCK1 (UCK1)
/LMCO
8-bit
PWM timer 2
P33/SI1 (UI1)
Port 3
P30/PPG03/MCO
8-bit
PWM timer 1
P34/PTO2
UART/SIO
P35/PWC
P21/PPG01
P22/PPG02
P23 to P27
CMOS I/O port
P40/INT20/EC
SIO
P41/INT21/SCK2
UART
P42/INT22/
SO2/SDA
N-ch I/O
I2C
P43/INT23/
SI2/SCL
16-bit timer/
counter 1
P44/INT24/UCK2
External interrupt 2
(level)
P45/INT25/UO2
P46/INT26/UI2
P47/INT27/ADST*2
CMOS I/O port
PWC
P36/WTO
P37/PTO1
P20/PWCK
Port 4
21-bit time
base timer
Internal data bus
Reset circuit
(watchdog timer)
RST
P32/SO1 (UO1)
12-bit PPG02
Oscillator circuit
Clock controller
Port 2
12-bit PPG01
X0
X1
P10 to P17
External interrupt 1
(edge)
N-ch output
CMOS I/O port
RAM (512 Kbytes/1 Kbyte/2 Kbytes)
F2MC-8L
CPU
8
10-bit
A/D converter
Port 5
P60/INT10 to P62/INT12
8
P50/AN0 to P57/AN7
AVCC
AVR
AVSS
Wild register
ROM (16 Kbytes/32 Kbytes/48 Kbytes)
Other pins
MOD0, MOD1, MOD2*2, VCC, VSS, C/N.C.
*1 : P63/INT13, P64 pins for single-clock system and X0A, X1A pins dual-clock system
*2 : P47/INT27/ADST pins are MOD2 pin for MB89F538.
24
MB89530A Series
■ CPU CORE
1. Memory Space
The MB89530A series has 64 Kbytes of memory space, containing all I/O, data areas, and program areas. The
I/O area is located at the lowest addresses, with the data area placed immediately above. The data area can
be partitioned into register areas, stack areas, or direct access areas depending on the application. The program
area is located at the opposite end of memory, closest to the highest addresses, and the highest part of this
area is assigned to the tables of interrupt and reset vectors and vector call instructions. The following diagram
shows the structure of memory space in the MB89530A series.
• Memory Map
MB89535A
0000H
MB89537A/537AC
0000H
0200H
General
purpose
register
I/O
0080H
0080H
RAM
0100H
0000H
I/O
I/O
0080H
MB89PV530
MB89P538/F538
MB89538A/538AC
RAM
0100H
0200H
General
purpose
register
RAM
0100H
0200H
General
purpose
register
0280H
0480H
Open
0C80H
0C91H
Open
0C80H
Wild register
0C91H
0880H
Wild register
0C91H
Wild register
Open
Open
Open
Open
0C80H
4000H
8000H
ROM
C000H
ROM
FFC0H
FFFFH
FFC0H
Vector tables*2
External ROM*1
ROM
FFFFH
FFC0H
Vector tables*2
FFFFH
Vector tables*2
*1 : The external ROM area is on the MB89PV530 only.
*2 : Vector tables (reset, interrupt, vector call instructions)
25
MB89530A Series
2. Registers
The F2MC-8L series has two types of registers, dedicated-use registers within the CPU, and general-purpose
registers in memory.
Program counter (PC)
: 16-bit length, shows the location where instructions are stored.
Accumulator (A)
: 16-bit length, a temporary memory register for calculation operations.
The lower byte is used for 8-bit data processing instructions.
Temporary accumulator (T) : 16-bit length, performs calculations with the accumulator.
The lower byte is used for 8-bit data processing instructions.
Index register (IX)
: 16-bit length, a register for index modification.
Extra pointer (EP)
: 16-bit length, a pointer indicating memory addresses.
Stack pointer (SP)
: 16-bit length, indicates stack areas.
Program status (PS)
: 16-bit length, contains register pointer and condition code.
16 bits
Initial value
FFFDH
: Program counter
PC
A
: Accumulator
Not fixed
T
: Temporary accumulator
Not fixed
IX
: Index register
Not fixed
EP
: Extra pointer
Not fixed
SP
: Stack pointer
Not fixed
PS
: Program status
I-flag = 0, IL1, 0 = 11
Other bits not fixed
In addition, the PS register can be divided so that the upper 8 bits are used as a register bank pointer (RP), and
the lower 8 bits as a condition code register (CCR). (Refer to the following illustration.)
• Program status register configuration
15
PS
14
13
12
10
9
8
Open Open Open
RP
RP
26
11
7
6
5
4
3
2
1
0
H
I
IL1
IL0
N
Z
V
C
CCR
MB89530A Series
The RP register shows the address of the register bank currently being used, so that the RP value and the actual
address are related by the conversion rule shown in the following illustration.
• General purpose register area real address conversion principle
Operation code
lower
RP upper
"0"
Address
generated
"0"
"0"
"0"
"0"
"0"
"0"
"1"
R4
R3
R2
R1
R0
b2
b1
b0
A15 A14 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
The CCR register has bits that show the content of results of calculations and transferred data, and bits that
control CPU operation during interrupts.
H-flag
I-flag
IL1, 0
N-flag
Z-flag
V-flag
C-flag
: Set to “1” if calculations result in carry or borrow operations from bit 3 to bit 4, otherwise set to “0”.
This flag is used for decimal correction instructions.
: This flag is set to “1” if interrupts are enabled, and “0” if interrupts are prohibited.
The default value at reset is “0”.
: Indicates the level of the currently permitted interrupts.
Only interrupt requests having a more powerful level than the value of these bits will be processed.
:
:
:
:
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
1
Strength
Strong
Weak
Set to “1” if the highest bit is “1” after a calculation, otherwise cleared to “0”.
Set to “1” if a calculation result is “0”, otherwise cleared to “0”.
Set to “1” if a two’s complement overflow results during a calculation, otherwise cleared to “0”.
Set to “1” if a calculation results in a carry or borrow operation from bit 7, otherwise cleared to “0”.
This is also the shift-out value in a shift instruction.
In addition, the following general purpose registers are available.
General purpose registers: 8 bits length, used to contain data.
The general purpose registers are 8-bit registers located in memory. There are eight such registers per bank,
and the MB89530A series have up to 32 banks for use. The bank currently in use is indicated by the register
bank pointer (RP).
27
MB89530A Series
•Register bank configuration
Address at this location =
0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
32 banks
Memory area
28
MB89530A Series
■ I/O MAP
Address
Register
name
00H
PDR0
Port 0 data register
01H
DDR0
Port 0 direction register
02H
PDR1
Port 1 data register
03H
DDR1
Port 1 direction register
Register description
04H to 06H
Write/Read
Initial value
R/W
XXXXXXXXB
W
0 0 0 0 0 0 0 0B
R/W
XXXXXXXXB
W
0 0 0 0 0 0 0 0B
(Reserved area)
07H
SYCC
System clock control register
R/W
X -1 MM1 0 0B
08H
STBC
Standby control register
R/W
0 0 0 1 0 - - -B
09H
WDTC
Watchdog control register
R/W
0 - - - XXXXB
0AH
TBTC
Time base timer control register
R/W
0 0 - - - 0 0 0B
0BH
WPCR
Watch prescaler control register
R/W
0 0 - - 0 0 0 0B
0CH
PDR2
Port 2 data register
R/W
XXXXXXXXB
0DH
DDR2
Port 2 direction register
R/W
0 0 0 0 0 0 0 0B
0EH
PDR3
Port 3 data register
R/W
XXXXXXXXB
0FH
DDR3
Port 3 direction register
R/W
0 0 0 0 0 0 0 0B
10H
PDR4
Port 4 data register
R/W
XXXX 1 1 XXB
11H
DDR4
Port 4 direction register
R/W
0 0 0 0 - - 0 0B
12H
PDR5
Port 5 data register
R/W
11111111B
13H
PDR6
Port 6 data register
R
XXXXXXXXB
14H to 21H
(Reserved area)
22H
SMC11
Serial mode control register 1 (UART)
R/W
0 0 0 0 0 0 0 0B
23H
SRC1
Serial rate control register (UART)
R/W
- - 0 1 1 0 0 0B
24H
SSD1
Serial status and data register (UART)
R/W
0 0 1 0 0 - 1XB
25H
SIDR1/
SODR1
Serial input/output data register (UART)
R/W
XXXXXXXXB
26H
SMC12
Serial mode control register 2 (UART)
R/W
- - 1 0 0 0 0 1B
27H
CNTR1
PWM control register 1
R/W
0 0 0 0 0 0 0 0B
28H
CNTR2
PWM control register 2
R/W
0 0 0 - 0 0 0 0B
29H
CNTR3
PWM control register 3
R/W
- 0 0 0 - - - -B
2AH
COMR1
PWM compare register 1
W
XXXXXXXXB
2BH
COMR2
PWM compare register 2
W
XXXXXXXXB
2CH
PCR1
PWC pulse width control register 1
R/W
0 0 0 - - 0 0 0B
2DH
PCR2
PWC pulse width control register 2
R/W
0 0 0 0 0 0 0 0B
2EH
RLBR
PWC reload buffer register
R/W
XXXXXXXXB
2FH
SMC21
Serial mode control register 1 (UART/SIO)
R/W
0 0 0 0 0 0 0 0B
30H
SMC22
R/W
0 0 0 0 0 0 0 0B
31H
SSD2
Serial mode control register 2 (UART/SIO)
Serial status and data register (UART/SIO)
R/W
0 0 0 0 1 - - -B
32H
SIDR2/
SODR2
Serial data register (UART/SIO)
R/W
XXXXXXXXB
33H
SRC2
Baud rate generator reload register
R/W
XXXXXXXXB
(Continued)
29
MB89530A Series
Address
Register
name
34H
ADC1
35H
ADC2
Register description
Write/Read
Initial value
A/D control register 1
R/W
0 0 0 0 0 0 - 0B
A/D control register 2
R/W
- 0 0 0 0 0 0 1B
36H
ADDL
A/D data register low
R/W
XXXXXXXXB
37H
ADDH
A/D data register high
R/W
- - - - - - 0 0B
38H
PPGC2
PPG2 control register (12-bit PPG)
R/W
0 0 0 0 0 0 0 0B
39H
PRL22
PPG2 reload register 2 (12-bit PPG)
R/W
0X0 0 0 0 0 0B
3AH
PRL21
PPG2 reload register 1 (12-bit PPG)
R/W
XX0 0 0 0 0 0B
3BH
PRL23
PPG2 reload register 3 (12-bit PPG)
R/W
XX0 0 0 0 0 0B
3CH
TMCR
16-bit timer control register
R/W
- - 0 0 0 0 0 0B
3DH
TCHR
16-bit timer counter register high
R/W
0 0 0 0 0 0 0 0B
3EH
TCLR
16-bit timer counter register low
R/W
0 0 0 0 0 0 0 0B
3FH
EIC1
External interrupt 1 control register 1
R/W
0 0 0 0 0 0 0 0B
40H
EIC2
External interrupt 1 control register 2
R/W
0 0 0 0 0 0 0 0B
R/W
- - - - - - - 0B
41H to 48H
49H
(Reserved area)
DDCR
DDC select register
4AH to 4BH
(Reserved area)
4CH
PPGC1
PPG1 control register (12-bit PPG)
R/W
0 0 0 0 0 0 0 0B
4DH
PRL12
PPG1 reload register 2 (12-bit PPG)
R/W
0X0 0 0 0 0 0B
4EH
PRL11
PPG1 reload register 1 (12-bit PPG)
R/W
XX0 0 0 0 0 0B
4FH
PRL13
PPG1 reload register 3 (12-bit PPG)
R/W
XX0 0 0 0 0 0B
2
R/W
- - - - - 0 0 0B
2
R
0 0 0 0 0 0 0 0B
2
50H
51H
IACR
IBSR
I C address control register
I C bus status register
52H
IBCR
I C bus control register
R/W
0 0 0 0 0 0 0 0B
53H
ICCR
I2C clock control register
R/W
0 0 0 XXXXXB
2
R/W
- XXXXXXXB
2
R/W
XXXXXXXXB
54H
IADR
I C address register
55H
IDAR
I C data register
56H
EIE2
External interrupt 2 control register
R/W
0 0 0 0 0 0 0 0B
57H
EIF2
External interrupt 2 flag register
R/W
- - - - - - - 0B
58H
RCR1
6-bit PPG control register 1
R/W
0 0 0 0 0 0 0 0B
59H
RCR2
6-bit PPG control register 2
R/W
0X0 0 0 0 0 0B
5AH
CKR
Clock output control register
R/W
- - - - - - 0 0B
5BH to 6FH
(Reserved area)
70H
SMR
Serial mode register (SIO)
R/W
0 0 0 0 0 0 0 0B
71H
SDR
Serial data register (SIO)
R/W
XXXXXXXXB
72H
PURR0
Port 0 pull-up resistance register
R/W
11111111B
73H
PURR1
Port 1 pull-up resistance register
R/W
11111111B
74H
PURR2
Port 2 pull-up resistance register
R/W
11111111B
75H
PURR3
Port 3 pull-up resistance register
R/W
11111111B
76H
PURR4
Port 4 pull-up resistance register
R/W
1 1 1 1 - -1 1 B
77H
WREN
Wild register enable register
R/W
- - 0 0 0 0 0 0B
(Continued)
30
MB89530A Series
(Continued)
Address
Register
name
78H
WROR
79H
Register description
Write/Read
Initial value
Wild register data test register
R/W
- - 0 0 0 0 0 0B
PURR6
Port 6 pull-up resistance register
R/W
---11111B
7AH
FMCS
Flash memory control status resister
R/W
0 0 0X0 0 - 0B
7BH
ILR1
Interrupt level setting register 1
W
1 1 1 1 1 1 1 1B
7CH
ILR2
Interrupt level setting register 2
W
1 1 1 1 1 1 1 1B
7DH
ILR3
Interrupt level setting register 3
W
1 1 1 1 1 1 1 1B
7EH
ILR4
Interrupt level setting register 4
7FH
ITR
Interrupt test register
C80H
WRARH1
C81H
W
1 1 1 1 1 1 1 1B
Access prohibited
XXXXXX0 0B
Upper address setting register 1
R/W
XXXXXXXXB
WRARL1
Lower address setting register 1
R/W
XXXXXXXXB
C82H
WRDR1
Data setting register 1
R/W
XXXXXXXXB
C83H
WRARH2
Upper address setting register 2
R/W
XXXXXXXXB
C84H
WRARL2
Lower address setting register 2
R/W
XXXXXXXXB
C85H
WRDR2
Data setting register 2
R/W
XXXXXXXXB
C86H
WRARH3
Upper address setting register 3
R/W
XXXXXXXXB
C87H
WRARL3
Lower address setting register 3
R/W
XXXXXXXXB
C88H
WRDR3
Data setting register 3
R/W
XXXXXXXXB
C89H
WRARH4
Upper address setting register 4
R/W
XXXXXXXXB
C8AH
WRARL4
Lower address setting register 4
R/W
XXXXXXXXB
C8BH
WRDR4
Data setting register 4
R/W
XXXXXXXXB
C8CH
WRARH5
Upper address setting register 5
R/W
XXXXXXXXB
C8DH
WRARL5
Lower address setting register 5
R/W
XXXXXXXXB
C8EH
WRDR5
Data setting register 5
R/W
XXXXXXXXB
C8FH
WRARH6
Upper address setting register 6
R/W
XXXXXXXXB
C90H
WRARL6
Lower address setting register 6
R/W
XXXXXXXXB
C91H
WRDR6
Data setting register 6
R/W
XXXXXXXXB
• Description of write/read symbols :
R/W : read/write enabled
R
: Read only
W
: Write only
• Description of initial values :
0 : This bit initialized to “0”.
1 : This bit initialized to “1”.
X : The initial value of this bit is not determined.
M : The initial value of this bit is a mask option.
- : This bit is not used.
Note : Do not use reserved spaces.
31
MB89530A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC,
AVCC
VSS − 0.3
VSS + 6.0
V
AVR
VSS − 0.3
VSS + 6.0
V
MB89535A/537A/538A*2
MB89537AC/538AC
MB89F538/P538
MB89PV530
VSS − 0.3
VCC + 0.3
V
Other than P42, P43
VSS − 0.3
VSS + 6.0
V
P42, P43
VSS − 0.3
VCC + 0.3
V
Other than P42, P43
VSS − 0.3
VSS + 6.0
V
P42, P43
ICLAMP
− 2.0
+ 2.0
mA
*3
Σ| ICLAMP |
⎯
20
mA
*3
IOL
⎯
15
mA
“L” level average output
current
IOLAV
⎯
4
mA
“L” level maximum total
output current
ΣIOL
⎯
100
mA
“L” level average total output
current
ΣIOLAV
⎯
40
mA
“H” level maximum output
current
IOH
⎯
−15
mA
“H” level average output
current
IOHAV
⎯
−4
mA
“H” level maximum total
output current
ΣIOH
⎯
−50
mA
“H” level average total
output current
ΣIOHAV
⎯
−20
mA
Current consumption
PD
⎯
300
mW
Operating temperature
TA
−40
+85
°C
Tstg
−55
+150
°C
Supply voltage*1
Input voltage*1
VI
Output voltage*1
VO
Maximum clamp current
Total maximum clamp
current
“L” level maximum output
current
Storage temperature
Average value
(operating current × operating duty)
Average value
(operating current × operating duty)
Average value
(operating current × operating duty)
Average value
(operating current × operating duty)
*1 : The parameter is based on AVss = Vss = 0 V.
*2 : AVcc and Vcc are to be used at the same potential. AVR should not exceed AVcc + 0.3 V.
(Continued)
32
MB89530A Series
(Continued)
*3 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40, P41, P44 to P47, P60 to P64
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is
provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on result.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
33
MB89530A Series
2. Recommended Operating Conditions
(AVss = Vss = 0 V)
Parameter
Supply voltage
Operating temperature
Symbol
VCC,
AVCC
Value
Unit
Remarks
Min
Max
2.2*
5.5
V
Range warranted for
normal operation
1.5
5.5
V
RAM status in stop
mode
2.7*
5.5
V
Range warranted for
normal operation
1.5
5.5
V
RAM status in stop
mode
3.5
5.5
V
Range warranted for
normal operation
3.0
5.5
V
RAM status in stop
mode
AVR
3.5
AVCC
V
TA
−40
+85
°C
MB89535A
MB89537A/538A
MB89537AC/
538AC
MB89P538
MB89PV530
MB89F538
* : Varies according to frequency used, and instruction cycle.
Refer to “Operating voltage vs. operating frequency (MB89P538/MB89PV530) ”, “Operating voltage vs. operating
frequency (MB89535A/537A/538A/537AC/538AC) ”, “Operating voltage vs. operating frequency (MB89F538) ”
and “5. A/D Converter Electrical Characteristics”.
34
MB89530A Series
• Operating voltage vs. operating frequency (MB89P538/MB89PV530)
Range of warranted analog precision : VCC = AVCC = 3.5 V to 5.5 V
5.5
Operating voltage VCC (V)
5.0
4.0
3.5
3.0
2.7
2.2
2.0
1.0
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0 10.0 11.0 12.0
12.5
Operating frequency (MHz)
(at instruction cycle = 4 / FCH)
4.0
2.0
0.8
0.4
0.32
Minimum instruction execution time (Instruction cycles) (µs)
indicates warranted operation at TA = −10 °C to +55 °C
• Operating voltage vs. operating frequency (MB89535A/537A/538A/537AC/538AC)
Range of warranted analog precision : VCC = AVCC = 3.5 V to 5.5 V
Operating voltage VCC (V)
5.5
5.0
4.0
3.5
3.0
2.7
2.2
2.0
1.0
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0 10.0 11.0 12.0
12.5
Operating frequency (MHz)
(at instruction cycle = 4 / FCH)
4.0
2.0
0.8
0.4
0.32
Minimum instruction execution time (Instruction cycles) (µs)
35
MB89530A Series
• Operating voltage vs. operating frequency (MB89F538)
Range of warranted analog precision : VCC = AVCC = 3.5 V to 5.5 V
Operating voltage VCC (V)
5.5
5.0
4.0
3.5
3.0
2.0
1.0
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0 10.0 11.0 12.0
12.5
Operating frequency (MHz)
4.0
2.0
0.8
0.4
0.32
Minimum instruction execution time (Instruction cycles) (µs)
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
36
MB89530A Series
3. DC Characteristics
(1) Supply Voltage at 5.0 (V)
(AVCC = VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Parameter
“H” level
input voltage
Symbol
Pin name
Condition
VIH
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P64,
SI1, SI2
VIHS
RST, MOD0, MOD1,
INT20 to INT27, UCK1,
UI1, INT10 to INT13,
SCK1, EC, PWCK,
PWC, SCK2, UCK2,
UI2, ADST
Value
Unit
Typ
Max
⎯
0.7 VCC
⎯
VCC + 0.3
V
⎯
0.8 VCC
⎯
VCC + 0.3
V
⎯
VSS + 1.4
⎯
VSS + 5.5
V
With SMB input
buffer selected*
⎯
0.7 VCC
⎯
VSS + 5.5
V
With I2C input
buffer selected*
VIL
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P64,
SI1, SI2
⎯
VSS − 0.3
⎯
0.3 VCC
V
VILS
RST, MOD0, MOD1,
INT20 to INT27, UCK1,
UI1, INT10 to INT13,
SCK1, EC, PWCK,
PWC, SCK2, UCK2,
UI2, ADST
⎯
VSS − 0.3
⎯
0.2 VCC
V
⎯
VSS − 0.3
⎯
VSS + 0.6
V
With SMB input
buffer selected*
⎯
VSS − 0.3
⎯
0.3 VCC
V
With I2C input
buffer selected*
VSS − 0.3
⎯
VCC + 0.3
V
⎯
VSS + 5.5
V
4.0
⎯
⎯
V
⎯
⎯
0.4
V
VIHSMB
SCL, SDA
VIHI2C
“L” level
input voltage
VILSMB
SCL, SDA
VILI2C
Open drain
output applied
voltage
“H” level
output voltage
VD1
P50 to P57
VD2
P42, P43
VOH
P00 to P07, P10 to P17,
IOH =
P20 to P24, P30 to P37,
−2.0 mA
P40, P41, P44 to P47
P25 to P27
“L” level
output
voltage
Remarks
Min
VOL
IOH =
−3.0 mA
P00 to P07, P10 to P17,
P20 to P27, P30 to P37, IOL =
P40 to P47, P50 to P57, 4.0 mA
RST
(Continued)
37
MB89530A Series
(AVCC = VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Parameter
Input leak
current
(Hi-Z output
leak current)
Open drain
output leak
current
Pull-up
resistance
Pin name
Symbol
ILI
Condition
Unit
Remarks
+5
µA
With no pull-up resistance specified
5
µA
Min
Typ
Max
P00 to P07, P10 to P17,
P20 to P27, P30 to P37, 0.0 V < VI <
P40 to P47, P50 to P57, VCC
P60 to P64
−5
⎯
0.0 V < VI <
VSS + 5.5 V
⎯
⎯
ILIOD
P42, P43
RPULL
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
VI = 0.0 V
P40, P41, P44 to P47,
P60 to P64, RST
FCH = 10.0 MHz
VCC = 5.0 V
tinst = 0.4 µs
ICC1
FCH = 10.0 MHz
VCC = 5.0 V
tinst = 6.4 µs
ICC2
Supply
current
Value
25
40
100
kΩ
With pull-up
resistance specified. The RST signal is excluded.
⎯
15
20
mA
MB89P538/
PV530
⎯
6
10
mA MB89F538
⎯
8
13
MB89535A/7A/8A
mA MB89537AC/
538AC
⎯
5
8.5
mA
⎯
1.5
3
mA MB89F538
⎯
1.5
3
MB89535A/7A/8A
mA MB89537AC/
538AC
⎯
5
7
Sleep mode
mA MB89P538/
PV530
⎯
3
5
mA
VCC
ICCS1
ICCS2
FCH = 10.0 MHz
VCC = 5.0 V
tinst = 0.4 µs
FCH = 10.0 MHz
VCC = 5.0 V
tinst = 6.4 µs
MB89P538/
PV530
Sleep mode
MB89F538
⎯
2.5
5
Sleep mode
MB89535A/7A/8A
mA
MB89537AC/
538AC
⎯
1.5
3
Sleep mode
mA MB89P538/
PV530
⎯
1
2
mA
2
Sleep mode
MB89535A/7A/8A
mA
MB89537AC/
538AC
⎯
1
Sleep mode
MB89F538
(Continued)
38
MB89530A Series
(Continued)
Parameter
Pin name
Symbol
FCL =
32.768 kHz
VCC = 5.0 V
TA = +25 °C
ICCL
VCC
Supply
current
ICCLS
FCL =
32.768 kHz
VCC = 5.0 V
TA = +25 °C
⎯
3
7
⎯
400
800
Sub mode
mA MB89P538/
PV530
µA
Sub mode
MB89F538
⎯
50
85
µA
Sub mode
MB89535A/7A/8A
MB89537AC/
538AC
⎯
30
50
µA
Sub, sleep mode
MB89P538/
PV530
⎯
15
30
µA
Sub, sleep mode
MB89F538
⎯
15
30
µA
Sub, sleep mode
MB89535A/7A/8A
MB89537AC/
538AC
ICCT
FCL =
32.768 kHz
VCC = 5.0 V
TA = +25 °C
⎯
5
15
µA
Watch mode,
main stop
ICCH
TA = +25 °C
⎯
3
10
µA
Sub, stop modes
FCH = 10.0 MHz
⎯
4
6
mA
A/D conversion
running
TA = +25 °C
⎯
1
5
µA
A/D stopped
f = 1 MHz
⎯
5
15
pF
IA
AVCC
IAH
Input
capacitance
(AVCC = VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Value
Condition
Unit
Remarks
Min Typ Max
CIN
Except VCC, VSS, AVCC,
AVSS
* : The MB89PV530/P538/537AC/538AC have a built-in I2C function, and a choice of input buffers by software setting.
MB89535A/537A/538A have no built-in I2C functions, and therefore this standard does not apply.
39
MB89530A Series
(2) Supply Voltage at 3.0 (V) (except MB89F538)
(AVCC = VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Parameter
“H” level
input voltage
Symbol
Pin name
Condition
VIH
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P64,
SI1, SI2
VIHS
RST, MOD0, MOD1,
INT20 to INT27, UCK1,
UI1, INT10 to INT13,
SCK1, EC, PWCK,
PWC, SCK2, UCK2,
UI2, ADST
Value
Unit
Typ
Max
⎯
0.7 VCC
⎯
VCC + 0.3
V
⎯
0.8 VCC
⎯
VCC + 0.3
V
⎯
VSS + 1.4
⎯
VSS + 5.5
V
With SMB
input buffer
selected*
⎯
0.7 VCC
⎯
VSS + 5.5
V
With I2C
input buffer
selected*
VIL
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P64,
SI1, SI2
⎯
VSS − 0.3
⎯
0.3 VCC
V
VILS
RST, MOD0, MOD1,
INT20 to INT27, UCK1,
UI1, INT10 to INT13,
SCK1, EC, PWCK, PWC,
SCK2, UCK2, UI2, ADST
⎯
VSS − 0.3
⎯
0.2 VCC
V
⎯
VSS − 0.3
⎯
VSS + 0.6
V
With SMB
input buffer
selected*
0.3 VCC
V
With I2C
input buffer
selected*
VCC + 0.3
V
VSS + 5.5
V
VIHSMB
SCL, SDA
VIHI2C
“L” level
input voltage
VILSMB
SCL, SDA
⎯
VILI2C
Open drain
output
applied
voltage
“H” level
output
voltage
“L” level
output
voltage
Remarks
Min
VD1
P50 to P57
VD2
P42, P43
VOH
P00 to P07, P10 to P17,
P20 to P24, P30 to P37, IOH = −2.0 mA
P40, P41, P44 to P47
P25 to P27
VOL
⎯
VSS − 0.3
⎯
VSS − 0.3
⎯
2.4
⎯
⎯
V
⎯
⎯
0.4
V
IOH = −3.0 mA
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
IOL = 4.0 mA
P40 to P47, P50 to P57,
RST
(Continued)
40
MB89530A Series
(Continued)
Parameter
(AVCC = VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Pin name
Symbol
Condition
Input leak
current
(Hi-Z
output leak
current)
ILI
Open drain
output leak
current
ILIOD
P42, P43
RPULL
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
VI = 0.0 V
P40, P41, P44 to P47,
P60 to P64, RST
Pull-up
resistance
P00 to P07, P10 to P17,
P20 to P27, P30 to P37, 0.0 V < VI <
P40 to P47, P50 to P57, VCC
P60 to P64
Unit
Min
Typ
Max
−5
⎯
+5
µA
⎯
⎯
5
µA
25
70
100
kΩ
Remarks
With no pull-up
resistance
specified
With pull-up
resistance specified.
The RST signal is
excluded.
ICC1
FCH = 10.0 MHz
tinst = 0.4 µs
⎯
6
10
mA
ICC2
FCH = 10.0 MHz
tinst = 6.4 µs
⎯
1.5
3
mA
ICCS1
FCH = 10.0 MHz
tinst = 0.4 µs
⎯
2
4
mA Sleep mode
ICCS2
FCH = 10.0 MHz
tinst = 6.4 µs
⎯
1
2
mA Sleep mode
⎯
1
3
mA
Sub modes
MB89P538/PV530
ICCL
FCL =
32.768 kHz
VCC = 3.0 V
TA = +25 °C
⎯
20
50
µA
Sub modes
MB89535A/7A/8A
MB89537AC/538AC
ICCLS
FCL =
32.768 kHz
VCC = 3.0 V
TA = +25 °C
⎯
15
30
µA
Sub, sleep modes
ICCT
FCL =
32.768 kHz
VCC = 3.0 V
TA = +25 °C
⎯
5
15
µA
Watch mode, main
stop
ICCH
TA = +25 °C
⎯
1
5
µA
Sub, stop modes
FCH = 10.0 MHz
⎯
1
3
mA
A/D conversion
running
TA = +25 °C
⎯
1
5
µA
A/D stopped
f = 1 MHz
⎯
5
15
pF
VCC
Supply
current
IA
AVCC
IAH
Input
capacitance
0.0 V < VI < VSS
+ 5.5 V
Value
CIN
Except VCC, VSS, AVCC,
AVSS
* : The MB89PV530/P538/537AC/538AC have a built-in I2C function, and a choice of input buffers by software setting.
MB89535A/537A/538A have no built-in I2C functions, and therefore this standard does not apply.
41
MB89530A Series
4. AC Characteristics
(1) Reset Timing
(VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Condition
tZLZH
⎯
RST “L” pulse width
Value
Min
Max
48 tHCYL
⎯
Unit
ns
Notes: • tHCYL is the main clock oscillator period.
• If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may
cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the
external reset pin (RST).
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Parameter
Power on time
Power shutoff time
Symbol
Condition
tR
tOFF
Value
Unit
Min
Max
⎯
0.5
50
ms
⎯
1
⎯
ms
Remarks
Waiting time until
power-on
Note : Be sure that the power supply will come on within the selected oscillator stabilization period. Also, when
varying the supply voltage during operation, it is recommended that the supply voltage be increased gradually.
tR
tOFF
2.2 V
VCC
0.2 V
42
0.2 V
0.2 V
MB89530A Series
(3) Clock Timing Standards
(AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Parameter
Symbol Pin name
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rise,
fall time
Condition
Value
Min
Typ
Max
Unit
Remarks
FCH
X0, X1
1
⎯
12.5
MHz
Main clock
FCL
X0A, X1A
⎯
32.768
⎯
kHz
Sub clock
tHCYL
X0, X1
80
⎯
1000
ns
Main clock
tLCYL
X0A, X1A
⎯
30.5
⎯
µs
Sub clock
PWH
PWL
X0
20
⎯
⎯
ns
External clock
PWHL
PWLL
X0A
⎯
15.2
⎯
µs
External clock
tCR
tCF
X0
⎯
⎯
10
ns
External clock
⎯
• X0, X1 timing and application conditions
tHCYL
PWH
PWL
tCR
tCF
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Clock application conditions
Using a crystal oscillator
or
ceramic oscillator
X0
X1
X0
FCH
C1
Using an external clock
signal
C2
X1
Open
FCH
43
MB89530A Series
• X0A, X1A timing and application conditions
tLCYL
PWHL
PWLL
tCR
tCF
0.8 VCC
0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
• Clock application conditions
Using a crystal oscillator
or
ceramic oscillator
X0A
Using an external clock
signal
X1A
X0A
Rd
FCL
C1
X1A
Open
FCL
C2
(4) Instruction Cycle
(AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Parameter
Instruction cycle
(minimum instruction
execution time)
44
Symbol
Rated value
Unit
Remarks
4/FCH, 8/FCH, 16/FCH, 64/FCH
µs
Operating at FCH = 12.5 MHz
(4/FCH)
tinst = 0.32 µs
2/FCL
µs
Operating at FCL = 32.768 kHz
tinst = 61.036 µs
tinst
MB89530A Series
(5) Serial I/O Timing
(VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Condition
Serial clock cycle time
tSCYC
SCK, UCK
SCK↓→SO
tSLOV
SCK, SO, UCK, UO
Valid SI→SCK↑
tIVSH
SI, SCK, UI, UCK
SCK↑→valid SI hold time
tSHIX
SCK, SI, UCK, UI
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
SCK↓→SO time
tSLOV
SCK, SO, UCK, UO
Valid SI→SCK↑
tIVSH
SI, SCK, UI, UCK
SCK↑→ valid SI hold time
tSHIX
SCK, SI, UCK, UI
Internal
clock
operation
SCK, UCK
External
clock
operation
Value
Unit
Min
Max
2 tinst
⎯
µs
−200
+200
ns
200
⎯
ns
200
⎯
ns
1 tinst
⎯
µs
1 tinst
⎯
µs
0
200
ns
200
⎯
ns
200
⎯
ns
Note : For tinst refer to “ (4) Instruction Cycle”.
Internal shift clock mode
tSCYC
SCK
UCK
2.4 V
0.8 V
0.8 V
tSLOV
SO
UO
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
SI
UI
0.8 VCC
0.2 VCC
External shift clock mode
tSLSH
tSHSL
SCK
UCK
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLOV
SO
UO
2.4 V
0.8 V
tIVSH
SI
UI
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.2 VCC
45
MB89530A Series
(6) Peripheral Input Timing
(VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Condition
Peripheral input “H” level
pulse width 1
tILIH1
Peripheral input “L” level
pulse width 1
tIHIL1
INT10 to INT13,
INT20 to INT27,
EC, PWC, PWCK
Peripheral input “H” level
pulse width 2
tILIH2
Peripheral input “L” level
pulse width 2
tIHIL2
Value
Max
⎯
2 tinst
⎯
µs
⎯
2 tinst
⎯
µs
⎯
28 tinst
⎯
µs
⎯
28 tinst
⎯
µs
ADST
Note : For tinst refer to “ (4) Instruction Cycle”.
tIHIL1
EC, INT, PWC, PWCK
tILIH1
0.8 VCC
0.2 VCC
tILIH2
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tIHIL2
ADST
46
Unit
Min
0.2 VCC
0.8 VCC
MB89530A Series
(7) I2C Timing
(VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Symbol
Pin
name
Condition
Start condition output
tSTA
SCL
SDA
⎯
Stop condition output
tSTO
SCL
SDA
⎯
Start condition detection
tSTA
SCL
SDA
Stop condition detection
tSTO
Restart condition output
Restart condition detection
Parameter
Value
Min
Max
1 / 4 tinst ×
m × n − 20
1 / 4 tinst ×
m × n + 20
Unit Remarks
ns
Master
only
1 / 4 tinst ×
1 / 4 tinst ×
(m × n + 8) − 20 (m × n + 8) + 20
ns
Master
only
⎯
1 / 4 tinst × 6 + 40
⎯
ns
SCL
SDA
⎯
1 / 4 tinst × 6 + 40
⎯
ns
tSTASU
SCL
SDA
⎯
1 / 4 tinst ×
1 / 4 tinst ×
(m × n + 8) − 20 (m × n + 8) + 20
ns
tSTASU
SCL
SDA
⎯
1 / 4 tinst × 4 + 40
⎯
ns
SCL output “L” width
tLOW
SCL
⎯
1 / 4 tinst ×
m × n − 20
1 / 4 tinst ×
m × n + 20
ns
Master
only
SCL output “H” width
tHIGH
SCL
⎯
1 / 4 tinst ×
1 / 4 tinst ×
(m × n + 8) − 20 (m × n + 8) + 20
ns
Master
only
SDA output delay time
tDO
SDA
⎯
1 / 4 tinst × 4 − 20 1 / 4 tinst × 4 + 20
ns
Setup after SDA output
interrupt interval
tDOSU
SDA
⎯
1 / 4 tinst × 4 − 20
⎯
ns
SCL input “L” width
tLOW
SCL
⎯
1 / 4 tinst × 6 + 40
⎯
ns
SCL input “H” width
tHIGH
SCL
⎯
1 / 4 tinst × 2 + 40
⎯
ns
SDA input setup
tSU
SDA
⎯
40
⎯
ns
SDA input hold
tHO
SDA
⎯
0
⎯
ns
Master
only
Notes : • For tinst refer to “ (4) Instruction Cycle”.
• The value “m” in the above table is the value from the shift clock frequency setting bits (CS4, CS3) in the
I2C clock control register “ICCR”. For details, refer to the register description in the hardware manual.
• The value ’n’ in the above table is the value from the shift clock frequency setting bits (CS2, CS0) in the
I2C clock control register “ICCR”. For details, refer to the register description in the hardware manual.
• tDOSU appears when the interrupt period is longer than the SCL “L” width.
• The rated values for SDA and SCL assume a start up time of 0 ns.
47
MB89530A Series
• I2C interface [Data sending (master/slave) ]
tSU
tDO
tDO
tSU
tDOSU
SDA
ACK
tSTASU
tSTA
tLOW
SCL
tHO
9
1
• I2C interface [Data receiving (master/slave) ]
tHO
tSU
tDO
tDO
tDOSU
SDA
ACK
tHIGH
tLOW
tSTO
SCL
6
48
7
8
9
MB89530A Series
5. A/D Converter Electrical Characteristics
(1) MB89535A/537A/537AC/538A/538AC/P538/PV530
(VCC = 3.5 V to 5.5 V, AVSS = VSS = 0 V, TA = −40 °C to +85 °C)
Parameter
Symbol Pin name
Condition
⎯
Resolution capability
Total error
Linear error
Differential linear error
⎯
Zero transition voltage
VOT
Full scale transition
voltage
VFST
Inter-channel variation
Conversion time
Sampling time
Analog input current
Analog input voltage
Reference voltage
Reference voltage
supply current
⎯
⎯
IAIN
VAIN
⎯
IR
IRH
AN0 to
AN7
AVR
AVR = AVCC
Value
Min
Typ
Max
⎯
⎯
⎯
⎯
AVSS −
1.5 LSB
⎯
⎯
⎯
⎯
AVSS +
0.5 LSB
10
±3.0
±2.5
±1.9
AVSS +
2.5 LSB
AVR −
3.5 LSB
AVR −
1.5 LSB
AVR +
1.5 LSB
⎯
60 tinst
16 tinst
⎯
⎯
⎯
400
⎯
4.0
⎯
⎯
10
AVR
AVCC
⎯
5
⎯
⎯
⎯
⎯
⎯
0
AVSS + 3.5
A/D running
⎯
A/D off
⎯
Unit
Remarks
bit
LSB
LSB
LSB
mV
AVCC = VCC
mV
LSB
µs *
µs
µA
V
V
µA
µA
* : Includes sampling time.
Note : For tinst refer to “4. AC Characteristics (4) Instruction Cycle”.
(2) MB89F538
(VCC = 3.5 V to 5.5 V, AVSS = VSS = 0 V, TA = −40 °C to +85 °C)
Parameter
Symbol Pin name
⎯
Resolution capability
Total error
Linear error
Differential linear error
⎯
Zero transition voltage
VOT
Full scale transition
voltage
VFST
Inter-channel variation
Conversion time
Sampling time
Analog input current
Analog input voltage
Reference voltage
Reference voltage
supply current
Condition
⎯
⎯
IAIN
VAIN
⎯
IR
IRH
AN0 to
AN7
AVR
AVR = AVCC
Value
Min
Typ
Max
⎯
⎯
⎯
⎯
AVSS −
1.5 LSB
⎯
⎯
⎯
⎯
AVSS +
0.5 LSB
10
±5.0
±2.5
±1.9
AVSS +
4.5 LSB
AVR −
6.5 LSB
AVR −
1.5 LSB
AVR +
1.5 LSB
⎯
60 tinst
16 tinst
⎯
⎯
⎯
400
⎯
4.0
⎯
⎯
10
AVR
AVCC
⎯
5
⎯
⎯
⎯
⎯
⎯
0
AVSS + 3.5
A/D running
⎯
A/D off
⎯
Unit
Remarks
bit
LSB
LSB
LSB
mV
AVCC = VCC
mV
LSB
µs *
µs
µA
V
V
µA
µA
* : Includes sampling time.
Note : For tinst refer to “4. AC Characteristics (4) Instruction Cycle”.
49
MB89530A Series
(3) A/D Converter Terms and Definitions
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
• Linear error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000”←→“00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1110”←→“11 1111 1111”) , compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
The deviation from the theoretical input voltage required to produce a change of 1 LSB in output code.
• Total error (Unit : LSB)
The difference between theoretical conversion value and actual conversion value.
Theoretical input/output
characteristics
Total error
VFST
3FFH
3FFH
3FEH
1.5 LSB
3FDH
004H
003H
VOT
002H
Digital output
Digital output
3FEH
3FDH
Actual conversion
characteristics
(1 LSB I N +
0.5 LSB)
004H
VNT
003H
002H
1 LSB
001H
001H
Actual
conversion
characteristics
Theoretical
characteristics
0.5 LSB
AVSS
AVR
Analog input
1 LSB =
VFST − VOT
1022
(V)
AVSS
AVR
Analog input
Total error in digital output N =
VNT − {1 LSB × N + 0.5 LSB}
1 LSB
(Continued)
50
MB89530A Series
(Continued)
Zero transition error
Full-scale transition error
Actual
conversion
characteristics
004H
Theoretical characteristics
Actual
conversion
characteristics
3FFH
Digital output
Digital output
003H
002H
Actual
conversion
characteristics
001H
VOT (actual
measurement value)
AVSS
Actual conversion
characteristics
Analog input
Linear error
Differential linear error
N + 1H
(1 LSB × N + VOT)
3FDH
VFST
004H
003H
002H
001H
AVR
Analog input
Actual conversion
characteristics
3FEH
Digital output
VFST (actual
measurement
value)
3FDH
3FCH
(actual
VNT measurement
value)
Actual conversion
characteristics
Theoretical
characteristics
VOT (actual measurement value)
AVSS
AVR
Analog input
Analog input linear
= VNT − {1 LSB × N + VOT}
1 LSB
error in digital output N
Digital output
3FFH
3FEH
Theoretical characteristics
Actual
conversion
V (N + 1) T
characteristics
NH
N − 1H
N − 2H
AVSS
VNT
Actual conversion
characteristics
Analog input
AVR
Differential linear
= V (N + 1) T − VNT −1
1 LSB
error in digital output N
51
MB89530A Series
(4) Precautionary Information
• Input Impedance of Analog Input Pins
The A/D converter of MB89530A has a sample & hold circuit as shown below, which uses a sample-and-hold
capacitor to obtain the voltage at the analog input pin for 8 instruction cycles following the start of A/D conversion.
For this reason if the external circuits providing the analog input signal have high output impedance, the analog
input voltage may not stabilize within the analog input sampling time. It is therefore recommended that the output
impedance of external circuits be reduced to 10 kΩ or less.
• MB89535A/537A/537AC/538A/538AC Analog Input Equivalent Circuit
Sample-and-hold circuit
C = 45 pF
Analog input pin
Comparator
R = 2.2 kΩ
If analog input impedance is
10 kΩ or more, the use of a
capacitor of approximately
0.1 µF is recommended.
Closes 8 instruction cycles
after the start of A/D conversion
Analog channel selector
• MB89P538 and MB89PV530 Analog Input Equivalent Circuit
Sample-and-hold circuit
C = 64 pF
Analog input pin
Comparator
R = 3 kΩ
If analog input impedance is
10 kΩ or more, the use of a
capacitor of approximately
0.1 µF is recommended.
Closes 8 instruction cycles
after the start of A/D conversion
Analog channel selector
• MB89F538 Analog Input Equivalent Circuit
Sample-and-hold circuit
C = 30 pF
Analog input pin
Comparator
R = 3.2 kΩ
If analog input impedance is
10 kΩ or more, the use of a
capacitor of approximately
0.1 µF is recommended.
Closes 8 instruction cycles
after the start of A/D conversion
Analog channel selector
• About error
The smaller the absolute value |AVR - AVss| is, the greater the relative error becomes.
52
MB89530A Series
6. Flash Memory
• Flash memory programming/erase characteristics
Parameter
Sector erase
time
Per 1 sector,
Constant value independent
with sector capacitance
Programming
Per 1 byte
time
Conditions
TA = +25 °C,
VCC = 5.0 V
Chip erase time
Program/Erase cycle
⎯
Value
Unit
Min
Typ
Max
⎯
1
15
s
⎯
8
3600
µs
⎯
5
⎯
s
10000
⎯
⎯
cycle
Remarks
*
*
* : Excludes internal programming time before erase.
53
MB89530A Series
■ EXAMPLE CHARACTERISTICS (MB89538A)
(1) Power Supply Current (External Clock)
ICC1 vs. VCC
ICCS1 vs. VCC
14
5
(TA = + 25 ˚C)
12
12.5 MHz
4
8
ICCS1 (mA)
10 MHz
10
ICC1 (mA)
(TA = + 25 ˚C)
12.5 MHz
8 MHz
6
5 MHz
10 MHz
3
8 MHz
2
5 MHz
4
1
2 MHz
1 MHz
2
0
2 MHz
1 MHz
0
2
3
4
5
6
7
2
3
4
VCC (V)
(2) “H” Level Input Voltage/ “L” Level Input Voltage (CMOS Input)
VIN vs. VCC
4
(TA = + 25 ˚C)
VIN (V)
3
2
1
0
2
3
4
5
6
7
VCC (V)
(3) “H” Level Input Voltage / ”L” Level Input Voltage (Hysteresis Input)
VIN vs. VCC
4
VIH
(TA = + 25 ˚C)
VIN (V)
3
VIL
2
1
0
2
3
4
5
VCC (V)
54
5
VCC (V)
6
7
6
7
MB89530A Series
(4) Pull-up Resistor Value
RPULL vs. VCC
1000
Pull-up (kΩ)
(TA = + 25 ˚C)
100
10
1
0
2
3
4
5
6
VCC (V)
(5) ”H” Level Output Voltage
VCC - VOH1 vs. IOH
VCC - VOH2 vs. IOH
1.6
0.9
0.8
1.2
0.7
VCC - VOH2 (V)
VCC - VOH1 (V)
(TA = + 25 ˚C, VCC = 5 V)
1.4
1.0
0.8
0.6
0.4
(TA = + 25 ˚C, VCC = 5 V)
0.6
0.5
0.4
0.3
0.2
0.2
0.1
0.0
0.0
0
2
4
6
8
10
0
2
IOH (mA)
4
6
8
10
IOH (mA)
(6) ”L” Level Output Voltage
VCC - VOL vs. IOL
0.9
(TA = + 25 ˚C, VCC = 5 V)
0.8
VCC - VOL (V)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
2
4
6
8
10
IOL (mA)
55
MB89530A Series
(7) AD Converter Characteristic Example
Linearity Error
3.0
2.5
(VCC = AVR = 5 V, FCH = 10 MHz)
2.0
Error (LSB)
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
0
128
256
384
512
640
768
896
1024
768
896
1024
768
896
1024
Conversion characteristic
Differential linearity error
2.5
2.0
1.5
Error (LSB)
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
0
128
256
384
512
640
Conversion characteristic
Total Error
4.0
3.0
(VCC = AVR = 5 V, FCH = 10 MHz)
Error (LSB)
2.0
1.0
0.0
-1.0
-2.0
-3.0
-4.0
0
128
256
384
512
640
Conversion characteristic
56
MB89530A Series
■ MASK OPTIONS
Part number
MB89535A
MB89537A
MB89537AC
MB89538A
MB89538AC
MB89F538-101
MB89F538-201
MB89P538-101
MB89P538-201
MB89PV530-101
Method of
specification
Specify at time
of mask order
Setting
not possible
Setting
not possible
Setting
not possible
1
Main clock
Select oscillator
stabilization wait period
(FCH* = 10 MHz)
approx.214/FCH*
(approx.1.6 ms)
approx.217/FCH*
(approx.13.1 ms)
approx.218/FCH*
(approx.26.2 ms)
Selection
available
218/FCH*
(approx. 26.2 ms)
218/FCH*
(approx. 26.2 ms)
218/FCH*
(approx. 26.2 ms)
2
Clock mode selection
• 2-system clock mode
• 1-system clock mode
Selection
available
No
MB89PV530-201
• 101 : 1-system clock mode
• 201 : 2-system clock mode
* : FCH: Main clock frequency
57
MB89530A Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB89535AP
MB89537AP
MB89537ACP
MB89538AP
MB89538ACP
MB89P538P-101
MB89P538P-201
MB89F538P-101
MB89F538P-201
DIP-64P-M01
MB89535AP, MB89537AP and MB89538AP
do not have I2C functions.
MB89535APF
MB89537APF
MB89537ACPF
MB89538APF
MB89538ACPF
MB89P538PF-101
MB89P538PF-201
MB89F538PF-101
MB89F538PF-201
FPT-64P-M06
MB89535APF, MB89537APF and
MB89538APF do not have I2C functions.
MB89535APFM
MB89537APFM
MB89537ACPFM
MB89538APFM
MB89538ACPFM
MB89P538PFM-101
MB89P538PFM-201
MB89F538PFM-101
MB89F538PFM-201
FPT-64P-M09
MB89535APFM, MB89537APFM and
MB89538APFM do not have I2C functions.
MB89535APFV
MB89537APFV
MB89537ACPFV
MB89538APFV
MB89538ACPFV
FPT-64P-M03
MB89535APFV, MB89537APFV and
MB89538APFV do not have I2C functions.
MB89535APV4
MB89537APV4
MB89537ACPV4
MB89538APV4
MB89538ACPV4
LCC-64P-M19
MB89535APV4, MB89537APV4, and
MB89538APV4 do not have I2C functions.
MB89P538-101PV*
MB89P538-201PV*
LCC-64P-M16*
MB89PV530C-101
MB89PV530C-201
MDP-64C-P02
MB89PV530CF-101
MB89PV530CF-201
MQP-64C-P01
* : Only for ES
58
MB89530A Series
■ PACKAGE DIMENSIONS
64-pin plastic SH-DIP
Lead pitch
1.778mm(70mil)
Package width ×
package length
17 × 58 mm
Sealing method
Plastic mold
Mounting height
5.65 mm MAX
(DIP-64P-M01)
64-pin plastic SH-DIP
(DIP-64P-M01)
Note: Pins width and pins thickness include plating thickness.
+0.22
+.009
58.00 –0.55 2.283 –.022
INDEX-1
17.00±0.25
(.669±.010)
INDEX-2
+0.70
4.95 –0.20
+.028
.195 –.008
+0.50
0.70 –0.19
+.020
.028 –.007
0.27±0.10
(.011±.004)
+0.20
3.30 –0.30
.130
+.008
–.012
1.378
.0543
C
+0.40
–0.20
+.016
–.008
1.778(.0700)
0.47±0.10
(.019±.004)
19.05(.750)
+0.50
0.25(.010)
M
2001 FUJITSU LIMITED D64001S-c-4-5
1.00 –0
+.020
0~15°
.039 –.0
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
59
MB89530A Series
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.0 × 10.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.32g
Code
(Reference)
P-LFQFP64-10×10-0.50
(FPT-64P-M03)
64-pin plastic LQFP
(FPT-64P-M03)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
* 10.00±0.10(.394±.004)SQ
48
0.145±0.055
(.006±.002)
33
49
32
Details of "A" part
0.08(.003)
+0.20
1.50 –0.10
+.008
.059 –.004
INDEX
64
0˚~8˚
17
(Mounting height)
0.10±0.10
(.004±.004)
(Stand off)
"A"
LEAD No.
1
16
0.50(.020)
C
0.20±0.05
(.008±.002)
0.08(.003)
M
2003 FUJITSU LIMITED F64009S-c-5-8
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
60
MB89530A Series
64-pin plastic QFP
Lead pitch
1.00 mm
Package width ×
package length
14 × 20 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP64-14×20-1.00
(FPT-64P-M06)
64-pin plastic QFP
(FPT-64P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
24.70±0.40(.972±.016)
* 20.00±0.20(.787±.008)
51
0.17±0.06
(.007±.002)
33
52
32
18.70±0.40
(.736±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
+0.35
3.00 –0.20
+.014
.118 –.008
64
(Mounting height)
20
0~8˚
1
19
1.00(.039)
0.42±0.08
(.017±.003)
0.20(.008)
+0.15
M
0.25 –0.20
1.20±0.20
(.047±.008)
+.006
.010 –.008
(Stand off)
"A"
0.10(.004)
C
2003 FUJITSU LIMITED F64013S-c-5-5
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
61
MB89530A Series
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12 × 12 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LQFP64-12×12-0.65
(FPT-64P-M09)
64-pin plastic LQFP
(FPT-64P-M09)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
* 12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.0057±.0022)
33
49
32
0.10(.004)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
(Mounting height)
0.25(.010)
INDEX
0~8˚
64
17
1
0.65(.026)
C
"A"
16
0.32±0.05
(.013±.002)
0.13(.005)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
M
2003 FUJITSU LIMITED F64018S-c-3-5
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
62
MB89530A Series
64-pin plastic BCC
Lead pitch
0.50 mm
Package width ×
package length
9.00 mm × 9.00 mm
Sealing method
Plastic mold
Mounting height
0.80 mm MAX
Weight
0.10g
(LCC-64P-M19)
64-pin plastic BCC
(LCC-64P-M19)
49
8.20(.323)TYP
8.10(.319)TYP
(0.80(.031)MAX)
(Mount height)
9.00±0.10(.354±.004)
33
0.50(.020)
TYP
33
0.50±0.10
(.020±.004)
49
0.50(.020)
TYP
8.25(.325)
REF
INDEX AREA
9.00±0.10
(.354±.004)
8.20(.323)
TYP
8.10(.319)
TYP
7.00(.276)
REF
0.50±0.10
(.020±.004)
"A"
1
17
0.075±0.025 17 "C"
(.003±.001)
(Stand off)
Details of "A" part
0.05(.002)
C
2002 FUJITSU LIMITED C64019S-c-1-1
0.60±0.06
(.024±.002)
0.30±0.06
(.012±.002)
0.14(.006)MIN.
0.70±0.06
(.028±.002)
0.30±0.06
(.012±.002)
7.00(.276)REF
"B"
1
8.25(.325)REF
Details of "B" part
0.55±0.06
(.022±.002)
C0.2(.008)
0.55±0.06
(.022±.002)
Details of "C" part
0.55±0.06
(.022±.002)
0.55±0.06
(.022±.002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
63
MB89530A Series
64-pin plastic BCC
Lead pitch
0.50 mm
Package width ×
package length
9.00 mm × 9.00 mm
Sealing method
Plastic mold
Mounting height
0.80 mm MAX
(LCC-64P-M16)
64-pin plastic BCC
(LCC-64P-M16)
8.20(.323)TYP
7.00(.276)REF
9.00±0.10(.354±.004)
49
(0.80(.031)MAX)
(Mount height) 0.50(.020)
TYP
33
33
0.50±0.10
(.020±.004)
49
0.50(.020)
TYP
8.15(.321)
REF
7.00(.276)
REF
8.20(.323)
TYP
9.00±0.10
(.354±.004)
INDEX AREA
0.50±0.10
(.020±.004)
1
17
17
0.075±0.025
(.003±.001)
(Stand off)
0.40±0.06
(.016±.002)
1
8.15(.321)REF
Details of "B" part
Details of "A" part
0.14(.006)
MIN
"B"
"A"
"C"
C0.2(.008)
Details of "C" part
0.45±0.06
(.018±.002)
0.45±0.06
(.018±.002)
0.05(.002)
0.30±0.06
(.012±.002)
C
2001 FUJITSU LIMITED C64016S-c-2-1
0.45±0.06
(.018±.002)
0.45±0.06
(.018±.002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
64
MB89530A Series
64-pin ceramic MDIP
Lead pitch
70mil (1.778mm)
Row spacing
750mil (15.24mm)
Motherboard
material
Ceramic
Mounted
packing material
Plastic
(MDP-64C-P02)
64-pin ceramic MDIP
(MDP-64C-P02)
0°~9°
56.90±0.64
(2.240±.025)
15.24(.600)
TYP
18.75±0.30
(.738±.012)
2.54±0.25
(.100±.010)
33.02(1.300)REF
INDEX AREA
0.25±0.05
(.010±.002)
1.27±0.25
(.050±.010)
10.16(.400)MAX
1.778±0.25
(.070±.010)
C
19.05±0.30
(.750±.012)
+0.13
0.46 –0.08
+.005
.018 –.003
55.12(2.170)REF
0.90±0.13
(.035±.005)
1994 FUJITSU LIMITED M64002SC-1-4
3.43±0.38
(.135±.015)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
65
MB89530A Series
(Continued)
64-pin ceramic MQFP
Lead pitch
1.00 mm
Lead shape
Straight
Motherboard
material
Ceramic
Mounted package
material
Plastic
(MQP-64C-P01)
64-pin ceramic MQFP
(MQP-64C-P01)
18.70(.736)TYP
INDEX AREA
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.00(.472)TYP
+0.40
1.20 –0.20
.047
1.00±0.25
(.039±.010)
+.016
–.008
1.00±0.25
(.039±.010)
1.27±0.13
(.050±.005)
22.30±0.33
(.878±.013)
24.70(.972)
TYP
0.30(.012)
TYP
1.27±0.13
(.050±.005)
18.12±0.20
12.02(.473)
(.713±.008)
TYP
10.16(.400)
14.22(.560)
TYP
TYP
0.30(.012)TYP
7.62(.300)TYP
18.00(.709)
TYP
0.40±0.10
(.016±.004)
0.40±0.10
(.016±.004)
+0.40
1.20 –0.20
+.016
.047 –.008
9.48(.373)TYP
11.68(.460)TYP
0.50(.020)TYP
C
10.82(.426)
0.15±0.05 MAX
(.006±.002)
1994 FUJITSU LIMITED M64004SC-1-3
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
66
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB89530A Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
1
■ FEATURES
• Wide range of package options
Changes are as follows :
• Two types of QFP packages
(1 mm pitch, 0.65 mm pitch)
• LQFP package (0.5 mm pitch)
• SH-DIP package
↓
• QFP package (1.00 mm pitch)
• Two types of LQFP packages
(0.65 mm pitch, 0.50 mm pitch)
• SH-DIP package (1.778 mm pitch)
• BCC package (0.50 mm pitch)
2
■ FEATURES
• External interrupt 2
Changes are as follows :
(8 channels) →
(except for MB89F538 : 8 channels, MB89F538 : 7
channels)
8 independent inputs → 8 or 7 independent input
5
■ MODEL DIFFERENCES AND SELECTION
CONSIDERATIONS
Added the rows of LCC-64P-M19 and LCC-64P-M16
■ PIN ASSIGNMENTS
Changed the pins : P33/SI1 (U1) → P33/SI1 (UI1)
9
Added the pin assignment for the LCC-64P-M19 and
LCC-64P-M16
10
11
to
13
Added the table footnote “* : Only for ES”
■ PIN DESCRIPTIONS
Changed the Pin no. :
QFP → BCC
For the function of MB89P538 in the pin name C,
changes are as follows :
Fixed at VSS →
If “Available” is selected for the step-down circuit
stabilization time, VCC is fixed.
If “Unavailable” is selected for the step-down circuit
stabilization time, VSS is fixed.
13
Changed the table footnote :
* 5 : FPT-64P-M03 → * 5 : FPT-64P-M03/M09
* 6 : FPT-64P-M09 → * 6 : LCC-64P-M19/M16
18
■ HANDLING DEVICES
9. Details on handling the C terminal of the
MB89530 series
20
■ PROGRAMMING AND ERASING FLASH
Changed in the Recommended Programmer
MEMORY ON THE MB89F538
Manufacturer and Model :
6. ROM Programmer Adaptor and Recommended
Ando Electric Co. Ltd. → Flash Support Group, Inc.
ROM Programmers
21
■ ONE-TIME WRITING SPECIFICATIONS WITH Added the row of part number MB89P538-101PV,
PROM AND EPROM MICROCONTROLLERS MB89P538-201PV
• ROM writer adapters
Added “*2 : Only for ES”
Changed in the figure :
(219/Fch) → (219/FCH) + (218/FCH)
(Continued)
67
MB89530A Series
(Continued)
Page
Section
Change Results
24
■ BLOCK DIAGRAM
Changed in the diagram :
X1↔ → X1←⎯
1KB RAM/2KB RAM
→ RAM (512 Kbytes/1 Kbyte/2 Kbytes)
32KB ROM/48KB ROM
→ ROM (16 Kbytes/32 Kbytes/48 Kbytes)
MOD0, MOD1, C, VCC, VSS →
MOD0, MOD1, MOD2*2, VCC, VSS
31
■ I/O MAP
For the initial value with 7A, the change is as follows :
0 0 0 0 0 0 - 0B → 0 0 0X0 0 - 0B
35
■ ELECTRICAL CHARACTERISTICS
2. Recommended Operating Conditions
• Operating voltage vs. operating frequency
(MB89P538/MB89PV530)
• Operating voltage vs. operating frequency
(MB89535A/537A/538A/537AC/538AC)
Changed in the diagram :
(at instruction cycle = 4/FC)
→ (at instruction cycle = 4/FCH)
43
■ ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(3) Clock Timing Standards
Changed for the“Symbol” with “Input clock pulse width” :
PWHH → PWHL
44
Changed in the X0A, X1A timing and application
conditions :
PWLH → PWHL
Added “Rd” in the Clock application conditions
56
■ EXAMPLE CHARACTERISTICS (MB89538A)
(7) AD Converter Characteristic Example
Changed in the figure :
Fc = 10 MHz → FCH = 10 MHz
58
■ ORDERING INFORMATION
Added the rows of LCC-64P-M19 and LCC-64P-M16
Added the “* : Only for ES”
62
■ PACKAGE DIMENSIONS
Changed the package name :
64-pin, Plastic QFP → 64-pin plastic LQFP
63
Added the 64-pin, Plastic BCC (LCC-64P-M19)
64
Added the 64-pin, Plastic BCC (LCC-64P-M16)
The vertical lines marked in the left side of the page show the changes.
68
MB89530A Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
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