FSQ500N Green Mode Fairchild Power Switch (FPS™) Features Description The FSQ500N is specially designed for low cost, small set-top box, DSL, home appliance auxiliary power supplies. This device combines a current-mode Pulse Width Modulator (PWM) with a SenseFET. The integrated PWM controller features include: a fixed oscillator, Under-Voltage Lockout (UVLO) protection, Overload Protection (OLP), Leading-Edge Blanking (LEB), an optimized gate turn-on/turn-off driver, Thermal Shutdown (TSD) protection with hysteresis, and temperature-compensated precision-current sources for loop compensation. When compared to a linear power supply, the FSQ500N reduces total size and weight, while increasing efficiency, productivity, and system reliability. This device provides a basic platform for cost-effective flyback converters. Single-Chip 700V SenseFET Power Switch Precision Fixed Operating Frequency: 130kHz No-Load Consumption 250mW at 265VAC with Burst Mode Internal Startup Switch Soft-Start Time Tuned by External Capacitor Under-Voltage Lockout (UVLO) with Hysteresis Pulse-by-Pulse Current Limit Overload Protection (OLP) and Internal Thermal Shutdown Function (TSD) with Hysteresis Auto-Restart Mode No Need for Auxiliary Bias Winding Applications STB and DSL Power Supply (1) Home Appliance, IH Cooker, Auxiliary Power Supply (2) 230VAC ± 15% (3) Adapter Related Resources Maximum Output Power AN-4137-Design Guidelines for Off-line Flyback Converters using FPS AN-4141-Troubleshooting and Design Tips for Fairchild Power Switch (FPStm) Flyback Applications AN-4147-Design Guidelines for RCD Snubber of Flyback AN6075- (Flyback) -AN-6075-Compact GreenMode Adapter Using FSQ500L for Low Cost 4.0W Open (4) Frame 6.5W 85-265VAC Open (4) Frame (3) Adapter 3.5W 5.5W Notes: 1. The junction temperature can limit the maximum output power. 2. 230VAC or 100/115VAC with doubler. 3. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient. 4. Maximum practical continuous power in an open frame design at 50°C ambient. Ordering Information Part Number Operating Temperature Range Eco Status Package Packing Method FSQ500N -40°C to +85°C RoHS 8-Lead, Molded Dual Inline Package (MDIP), JEDEC MS-001, .300 Inch Wide Rail For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2009 Fairchild Semiconductor Corporation FSQ500N • Rev. 1.0.0 www.fairchildsemi.com FSQ500N — Green Mode Fairchild Power Switch (FPS™) October 2009 FSQ500N — Green Mode Fairchild Power Switch (FPS™) Application Circuit Diagram AC IN DC OUT Drain PWM VFB VCC GND Figure 1. Typical Application Circuit Internal Block Diagram Figure 2. Internal Block Diagram © 2009 Fairchild Semiconductor Corporation FSQ500N • Rev. 1.0.0 www.fairchildsemi.com 2 Drain NC VCC VFB 8-DIP NC GND GND GND Figure 3. Package / Pin Diagram Pin Definitions Pin # Name 1 NC No connection VCC This pin is connected to a storage capacitor. A high-voltage regulator connected between pin 8 (VSTR) and this pin provides the supply voltage to the FSQ500N at startup and when switching during normal operation. The FSQ500N eliminates the need for auxiliary bias winding and associated external components. 3 VFB This pin is internally connected to the non-inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin reaches 4.5V, the overload protection triggers, which shuts down the FPS. 4, 5, 6 GND 7 NC 8 Drain 2 Description This pin is the control ground and the SenseFET source. No connection High-voltage power SenseFET drain connection © 2009 Fairchild Semiconductor Corporation FSQ500N • Rev. 1.0.0 www.fairchildsemi.com 3 FSQ500N — Green Mode Fairchild Power Switch (FPS™) Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter VDS Drain Pin Voltage VCC Supply Voltage VFB Feedback Voltage Range PD Total Power Dissipation IDM Drain Current Pulsed TJ Operating Junction Temperature Storage Temperature TSTG (7) ESD Min. (5) Max. 700 V 10 -0.3 Unit V VCC V 1.42 W 0.41 A -40 +150 °C -55 +150 °C (6) Human Body Model, JESD22-A114 2.5 Charged Device Model, JESD22-C101 2 KV Notes: 5. LDMOS available drain voltage is -0.3V ~ 700V. 6. Repetitive rating: pulse width is limited by maximum junction temperature. 7. Meet JEDEC Standards JESD 22-A114 and JESD 22-C101 Thermal Impedance Symbol (8)(9) θJA Parameter Junction-to-Ambient Thermal Resistance Value Unit 88 °C/W (8)(10) θJC Junction-to-Case Thermal Resistance 19 °C/W Note: 8. All items are tested with the standards JESD 51-2 and JESD 51-10 (DIP Package). 9. θJA Free-standing, with no heat-sink, under natural convection. 10. θJC, Junction to lead thermal characteristics under ΘJA test condition. TC is measured on the source #7 pin closed to plastic interface for ΘJA thermo couple is mounted on soldering. © 2009 Fairchild Semiconductor Corporation FSQ500N • Rev. 1.0.0 www.fairchildsemi.com 4 FSQ500N — Green Mode Fairchild Power Switch (FPS™) Absolute Maximum Ratings TJ = 25°C unless otherwise specified. Symbol Parameter Test Conditions Min. Typ. Max. Unit SenseFET Section BVDSS Drain-Source Breakdown Voltage VCC = 6.5V, VFB = 0V, ID = 150μA IDSS Zero-Gate-Voltage Drain Current VCC = 6.5V, VFB = 0V, VDS = 700V RDS(ON) CISS COSS tr tf Drain-Source On-State Resistance Input Capacitance (11) Output Capacitance Rise Time Fall Time (11) (11) (11) 700 V 150 μA TJ = 25°C, ID = 25mA 25 29 Ω TJ = 100°C, ID = 25mA 35 41 Ω VGS = 6.5V 42 pF VDS = 40V, fS = 1MHz 25 pF VDS = 350V, ID = 25mA 100 ns VDS = 350V, lD = 25mA 50 ns Control Section fS ΔfS IFB(Burst) IFB(Normal) Switching Frequency VCC = 6.5V, VFB = 1.0V Switching Frequency Variation (11) Feedback Source Current -25°C < TJ < 125°C ±7 % μA VCC = 6.5V 200 225 250 μA 54 60 66 % 0 % VCC = 6.5V, VFB = 4.0V VCC = 6.5V, VFB = 0V Shutdown Delay Current Enable Voltage ±5 122 Minimum Duty Ratio VDLY_EN kHz 110 Maximum Duty Ratio VSTOP 140 98 DMIN UVLO Threshold Voltage 130 VCC = 6.5V, VFB = 0V DMAX VSTART 120 VFB = 0V, VCC Sweep 5.5 6.0 6.5 V After Turn-on, VFB = 0V, VCC Sweep 4.5 5.0 5.5 V VFB = VSD, VCC Sweep from 6V 6.0 6.5 7.0 V 0.75 0.80 0.85 V 0.70 0.75 0.80 V 30 50 80 mV Burst-Mode Section VBURH VBURL Burst Mode Voltage VCC = 6.5V, VFB Sweep HYS Protection Section ILIM Peak Current Limit di/dt = 150mA/µs 280 320 360 mA VSD Shutdown Feedback Voltage VCC = 6.5V, VFB Sweep 4.1 4.5 4.9 V VCC = 6.5V, VFB = 4.0V 4 5 6 μA IDELAY Shutdown Delay Current tLEB Leading-Edge Blanking Time tCLD Current Limit Delay Time TSD HYS (11) (11) Thermal Shutdown Temperature 130 (11) 250 ns 100 ns 140 150 °C °C 80 Total Device Section IOP-BURST Operating Supply Current (Control Part Only) IOP-FB VCC = 6.5V, VFB = 0V 360 430 500 760 880 μA μA VCC = 6.5V, VFB = 4V 640 Startup Charging Current VCC = VFB = 0V, VDS = 40V 3.3 VCCREG Supply Shunt Regulator VDS = 40V, VFB = 0V 6.0 6.5 7.0 V VCCREG_ Supply Shunt Regulator During (11) TSD 5.2 5.7 6.2 V ICH TSD mA Note: 11. These parameters, although guaranteed, are not 100% tested in production. © 2009 Fairchild Semiconductor Corporation FSQ500N • Rev. 1.0.0 www.fairchildsemi.com 5 FSQ500N — Green Mode Fairchild Power Switch (FPS™) Electrical Characteristics These characteristic graphs are measured at TA = 25°C. Operating Supply Current (IOP) vs Temperature Switching Frequency (fS) vs Temperature 140 480 460 135 420 fS (KHZ) IOP (μA) 440 400 380 360 130 125 120 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 Temperature (℃) 65 80 95 110 125 Figure 5. Switching Frequency (fS) vs. Temperature UVLO Threshold Voltage (VSTOP) vs Temperature UVLO Threshold Voltage (VSTART) vs Temperature 6.5 5.5 6.3 5.3 6.1 5.1 VSTOP (V) VSTART (V) 50 Temperature (℃) Figure 4. Operating Supply Current (IOP_Burst) vs. Temperature 5.9 5.7 5.5 4.9 4.7 4.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 Temperature (℃) 35 50 65 80 95 110 125 Temperature (℃) Figure 6. UVLO Threshold Voltage (VSTART) vs. Temperature Figure 7. UVLO Threshold Voltage (VSTOP) vs. Temperature Burst Mode Voltage (VBURL) vs Temperature Burst Mode Voltage (VBURH) vs Temperature 850 800 830 780 810 760 VBURL (mV) VBURH (mV) 35 790 770 740 720 700 750 -40 -25 -10 5 20 35 50 65 80 95 110 -40 125 -10 5 20 35 50 65 80 95 110 125 Temperature (℃) Temperature (℃) Figure 8. Burst-Mode Voltage (VBURH) vs. Temperature © 2009 Fairchild Semiconductor Corporation FSQ500N • Rev. 1.0.0 -25 Figure 9. Burst-Mode Voltage (VBURL) vs. Temperature www.fairchildsemi.com 6 FSQ500N — Green Mode Fairchild Power Switch (FPS™) Typical Performance Characteristics These characteristic graphs are measured at TA = 25°C. Shutdown Feedback Voltage (VSD) vs Temperature Maximum Duty Ratio (DMAX) vs Temperature 64.0 5.0 63.0 4.8 62.0 VSD (V) DMAx (%) 61.0 60.0 59.0 58.0 4.6 4.4 4.2 57.0 56.0 4.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature (℃) 35 50 65 80 95 110 125 Temperature (℃) Figure 10. Maximum Duty Ratio (DMAX) vs. Temperature Figure 11. Shutdown Feedback Voltage (VSD) vs. Temperature Shutdown Delay Current (IDELAY) vs Temperature Peak Current Limit (ILIM) vs Temperature 5.5 360.0 350.0 5.3 340.0 330.0 IDELAY (μA) ILIM (mA) 20 320.0 310.0 300.0 290.0 280.0 5.1 4.9 4.7 4.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 Temperature (℃) Figure 12. 5 20 35 50 65 80 95 110 125 Temperature (℃) Peak Current Limit (ILIM) vs. Temperature Figure 13. Shutdown Delay Current (IDELAY) vs. Temperature Supply Shunt Regulator (VCCREG) vs Temperature 7.0 VCCRGE (V) 6.8 6.6 6.4 6.2 6.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (℃) Figure 14. Supply Shunt Regulator (VCCREG) vs. Temperature © 2009 Fairchild Semiconductor Corporation FSQ500N • Rev. 1.0.0 www.fairchildsemi.com 7 FSQ500N — Green Mode Fairchild Power Switch (FPS™) Typical Performance Characteristics (Continued) 1. Startup and VCC Regulation: At startup, an internal high-voltage current source supplies the internal bias and charges the external capacitor (CA) connected to the VCC pins, as illustrated in Figure 15. An internal high-voltage regulator (HV/REG) located between the Drain and VCC pins regulates the VCC to 6.5V and supplies operating current. Therefore, FSQ500N needs no auxiliary bias winding. VCC VCC IDELAY VFB VO SenseFET OSC 2 FOD817A IFB D1 CB D2 + VFB* KA431 8R Gate driver R - Transformer OLP VSD Rsense D VCC 3 6.5V Figure 16. 2 ICH HV/REG 3. Protection Circuits: The FSQ500N has two selfprotective functions: overload protection (OLP) and thermal shutdown (TSD). While OLP is implemented as auto-restart mode, there is no switching when TSD triggers. Once the overload condition is detected; switching is terminated, the senseFET remains off, and HV/REG turns off. This causes VCC to fall. When VCC falls below the under-voltage lockout (UVLO) stop voltage of 5.0V, the protection is reset and the startup circuit charges the VCC capacitor. When VCC reaches the start voltage of 6.0V, the FSQ500N resumes its normal operation. If the fault condition is still not removed, the senseFET and HV/REG remain off and VCC drops to VSTOP again. In this manner, the autorestart can alternately enable and disable the switching of the power senseFET until the fault condition is eliminated, as shown in Figure 17. ISTART CA VREF Figure 15. UVLO Startup Block 2. Feedback Control: FSQ500N employs current-mode control, as shown in Figure 16. An opto-coupler (such as the FOD817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor makes it possible to control the switching duty cycle. When the reference pin voltage of the regulator exceeds the internal reference voltage of 2.5V, the opto-coupler LED current increases, pulling down the feedback voltage and reducing the duty cycle. This typically occurs when the line input voltage increases or the output load current decreases. Because these protection circuits are fully integrated into the IC without external components, reliability is improved without increasing cost. VDS 2.1 Pulse-by-Pulse Current Limit: Because currentmode control is employed, the peak current through the senseFET is limited by the non-inverting input of PWM comparator (VFB*), as shown in Figure 16. Assuming that 225µA current source flows only through the internal resistor (8R + R = 12kΩ), the cathode voltage of diode D2 is about 2.7V. Since D1 is blocked when the feedback voltage (VFB) exceeds 2.7V, the maximum voltage of the cathode of D2 is clamped at this voltage, clamping VFB*. Therefore, the peak value of the current through the senseFET is limited. OLP occurs Power on OLP removed VCC 6.5V 6.0V 5.0V t 2.2 Leading-Edge Blanking (LEB): At the instant the internal senseFET is turned on, a high-current spike occurs through the senseFET, caused by primaryside capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the Rsense resistor would lead to incorrect feedback operation in the current mode PWM control. To counter this effect, the FPS employs a leading-edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (tLEB = 250ns) after the senseFET turns on. © 2009 Fairchild Semiconductor Corporation FSQ500N • Rev. 1.0.0 Pulse Width Modulation (PWM) Circuit Normal operation Figure 17. Fault situation Normal operation Auto Restart Protection Waveforms www.fairchildsemi.com 8 FSQ500N — Green Mode Fairchild Power Switch (FPS™) Functional Description VFB Power on VDS TSD occurs TSD removed VCC 6.5V 6.0V 5.7V t Normal operation Figure 19. Over-Temperature Protection (OTP) 4. Soft-Start: The soft-start time is tuned by an external VCC capacitor (CA), which increases PWM comparator non-inverting input voltage together with the senseFET current slowly after it starts. Before VCC reaches VSTART, CA is charged by the current ICH-ISTART, where ICH and ISTART are described in Figure 15. After VCC reaches VSTART, all internal blocks are activated, so that the current consuming inside IC becomes IOP. Therefore, CA is charged by the current ICH-IOP, which makes the increasing slope of VCC become sluggish. VCC is shifted by 6.0V negatively (it is performed in soft-start block in Figure 2), then VCC -6.0V is an input of one of the input terminals of the PWM comparator. The drain current follows VCC -6.0V instead of the VFB* because of the low-dominant feature of the PWM comparator. The softstart time can be made long or short by selecting CA, as described in Figure 20. During tS/S, IDELAY is disabled to avoid unwanted OLP. Typically, tS/S is around 4.6ms with 27µF of CA. Overload protection 4.5V 2.7V tS/S VCC T12= CB*(4.5-2.7)/IDELAY T1 Figure 18. T2 6.5V 6V VCCREG VSTART 5V VSTOP t Overload Protection 3.2 Thermal Shutdown (TSD): The senseFET and the control IC in one package makes it easy for the control IC to detect an abnormal over temperature of the senseFET. When the temperature exceeds ~140°C, the thermal shutdown triggers. When TSD triggers, delay current is disabled, switching operation stops, and VCC through the internal high-voltage current source is set to 5.7V from 6.5V, as shown in Figure 19. Since the TSD signal prohibits the senseFET from switching, there is no switching until the junction temperature decreases sufficiently. If the junction temperature is lower than 60°C typically, TSD signal is removed and VCC is set to 6.5V again. While VCC increases from 5.7V to 6.5V, the soft-start function makes the senseFET turn on and off with no voltage and/or current stress. © 2009 Fairchild Semiconductor Corporation FSQ500N • Rev. 1.0.0 Normal operation Fault situation t1 t1=CA×6V/(ICH-ISTART) t2 t tS/S=CA×0.5V/(ICH-IOP) Figure 20. Soft-Start Function The peak value of the drain current of the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. It also helps to prevent transformer saturation and reduce stress on the secondary diode during startup. www.fairchildsemi.com 9 FSQ500N — Green Mode Fairchild Power Switch (FPS™) 3.1 Overload Protection (OLP): Overload is defined as the load current exceeding its normal level due to an unexpected abnormal event. In this situation, the protection circuit should trigger to protect the SMPS. However, even when the SMPS is in the normal operation, the overload protection circuit can be triggered during the load transition. To avoid this undesired operation, the overload protection circuit is designed to trigger after a specified time to determine whether the situation is transient or a true overload. Because of the pulse-by-pulse current limit capability, the maximum peak current through the senseFET is limited and, therefore, the maximum input power is restricted with a given input voltage. If the output consumes more than this maximum power, the output voltage (VO) decreases below the set voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (VFB). If VFB exceeds 2.7V, D1 is blocked and the 5µA current source starts to charge CB slowly up to VCC. In this condition, VFB continues increasing until it reaches 4.5V, when the switching operation is terminated, as shown in Figure 18. The delay time for shutdown is the time required to charge CB from 2.7V to 4.5V with 5µA. In general, a 10 ~ 50ms delay is typical for most applications. This protection is implemented in autorestart mode. Vo Voset VFB 0.80V 0.75V IDS VDS time t1 Switching disabled t2 t3 Switching disabled t4 Figure 21. Burst-Mode Operation © 2009 Fairchild Semiconductor Corporation FSQ500N • Rev. 1.0.0 www.fairchildsemi.com 10 FSQ500N — Green Mode Fairchild Power Switch (FPS™) 5. Burst Operation: To minimize power dissipation in standby mode, the FPS enters burst-mode operation. During the burst-mode operation, IFB(Burst) decreases half of IFB(Normal). As the load decreases, the feedback voltage decreases. As shown in Figure 21, the device automatically enters burst mode when the feedback voltage drops below VBURL (750mV). At this point, switching stops and the output voltages start to drop at a rate dependent on standby current load. This causes the feedback voltage to rise. Once it passes VBURH (800mV), switching resumes. The feedback voltage then falls and the process repeats. Burst mode alternately enables and disables switching of the power senseFET, reducing switching loss in standby mode. FSQ500N — Green Mode Fairchild Power Switch (FPS™) Package Dimensions 9.83 9.00 6.67 6.096 8.255 7.61 3.683 3.20 5.08 MAX 7.62 0.33 MIN 3.60 3.00 (0.56) 2.54 0.56 0.355 0.356 0.20 9.957 7.87 1.65 1.27 7.62 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994 E) DRAWING FILENAME AND REVSION: MKT-N08FREV2. Figure 22. 8-Lead, Molded Dual Inline Package (MDIP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FSQ500N • Rev. 1.0.0 www.fairchildsemi.com 11 FSQ500N — Green Mode Fairchild Power Switch (FPS™) © 2009 Fairchild Semiconductor Corporation FSQ500N • Rev. 1.0.0 www.fairchildsemi.com 12