FSL137MRIN Green-Mode Fairchild Power Switch (FPS™) Features Description Advanced Soft Burst Mode for Low Standby Power and Low Audible Noise Random Frequency Fluctuation (RFF) for Low EMI Pulse-by-Pulse Current Limit The FSL137MRIN is an integrated Pulse Width Modulation (PWM) controller and SenseFET specifically designed for offline Switched Mode Power Supplies (SMPS) with minimal external components. The PWM controller includes an integrated fixed-frequency oscillator, Line Over-Voltage Protection (LOVP), UnderVoltage Lockout (UVLO), Leading-Edge Blanking (LEB), optimized gate driver, internal soft-start, temperaturecompensated precise current sources for loop compensation, and self-protection circuitry. Under 50 mW Standby Power Consumption at 265 VAC, No-load Condition with Burst Mode Overload Protection (OLP), Over-Voltage Protection (OVP), Abnormal Over-Current Protection (AOCP), Internal Thermal Shutdown (TSD) with Hysteresis, Output-Short Protection (OSP), and Under-Voltage Lockout (UVLO) with Hysteresis, Line Over-Voltage Protection (LOVP) Low Operating Current (0.4 mA) in Burst Mode Internal Startup Circuit Compared with a discrete MOSFET and PWM controller solution, the FSL137MRIN reduces total cost, component count, size, and weight; while simultaneously increasing efficiency, productivity, and system reliability. This device provides a basic platform suited for cost-effective design of flyback converters. Internal High-Voltage SenseFET: 700 V Built-in Soft-Start: 15 ms Auto-Restart Mode Applications Power Supply for Home Appliances, LCD Monitors, STBs, and DVD Players Ordering Information Output Power Table(2) (1) Part Number Package FSL137MRIN 8-DIP Operating Current RDS(ON) Junction Limit (Max.) Temperature (Typ.) -40°C ~ +125°C 1.3 A 4.75 230 VAC ±15% Adapter(3) 25 W 85-265 VAC Open Adapter(3) Frame(4) 30 W Open Frame(4) 15 W 20 W Notes: 1. Lead-free package per JEDEC J-STD-020B. 2. The junction temperature can limit the maximum output power. 3. Typical continuous power in a non-ventilated enclosed adapter measured at 50C ambient temperature. 4. Maximum practical continuous power in an open-frame design at 50C ambient temperatures. © 2012 Fairchild Semiconductor Corporation FSL137MRIN • Rev. 1.0.3 www.fairchildsemi.com FSL137MRIN — Green-Mode Fairchild Power Switch (FPS™) October 2013 FSL137MRIN — Green-Mode Fairchild Power Switch (FPS™) Application Circuit VO AC IN VSTR VIN Drain PWM GND VCC FB Figure 1. Typical Application Circuit Internal Block Diagram VSTR VCC Drain 5 2 6, 7, 8 ICH Vburst 0.35V / 0.5V VREF Soft Burst VCC Good 7.5V / 12V Random VCC VREF 2.0µA IDELAY FB OSC 90µA IFB Soft-Start PWM 3 S Q R Q Gate Driver 3R R LEB (300ns) tON<tOSP(1.0μs) LPF VAOCP 1 GND VOSP TSD S Q R Q VSD 7.0V VCC Good VCC VOVP 24.5V VIN_H / VIN_L 4 VIN Figure 2. © 2012 Fairchild Semiconductor Corporation FSL137MRIN • Rev. 1.0.3 Internal Block Diagram www.fairchildsemi.com 2 1. GND 8. Drain 2. VCC 7. Drain FSL137MRIN 3. FB 6. Drain 4. VIN 5. VSTR Figure 3. Pin Assignments (Top View) Pin Definitions Pin # Name 1 GND Ground. This pin is the control ground and the SenseFET source. 2 VCC Power Supply. This pin is the positive supply input, which provides the internal operating current for both startup and steady-state operation. FB Feedback. This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin reaches 7 V, the overload protection triggers, which shuts down the FPS. 4 VIN Line Over-Voltage Input. This is the input pin of line voltage. The voltage, which is divided by resistors, is the input of this pin. If this pin voltage is higher than VINH voltage, the LOVP triggers, which shuts down the FPS. Do not leave this pin floating. If LOVP is not used, this pin should be directly connected to GND. 5 VSTR Startup. This pin is connected directly, or through a resistor, to the high-voltage DC link. At startup, the internal high-voltage current source supplies internal bias and charges the external capacitor connected to the VCC pin. Once VCC reaches 12 V, the internal current source (ICH) is disabled. Drain SenseFET Drain. High-voltage power SenseFET drain connection. 3 Description FSL137MRIN — Green-Mode Fairchild Power Switch (FPS™) Pin Configuration 6 7 8 © 2012 Fairchild Semiconductor Corporation FSL137MRIN • Rev. 1.0.3 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VSTR VSTR Pin Voltage 700 V VDS Drain Pin Voltage 700 V VCC VCC Pin Voltage 26 V VFB Feedback Pin Voltage -0.3 10.0 V VIN VIN Pin Voltage -0.3 10.0 V IDM Drain Current Pulsed 12 A ID Continuous Switching Drain Current(5) 3 A 230 mJ 1.5 W 150 C EAS PD TJ (6) Single-Pulsed Avalanche Energy Total Power Dissipation (TC=25C) (7) Maximum Junction Temperature (8) Operating Junction Temperature -40 +125 C TSTG Storage Temperature -55 +150 C ESD Electrostatic Discharge Capability Human Body Model, JESD22-A114 4.5 Charged Device Model, JESD22-C101 2.0 kV Notes: 5. Repetitive peak switching current when the inductive load is assumed: limited by maximum duty (DMAX=0.73) and junction temperature (see Figure 4). 6. L=45 mH, starting TJ=25C. 7. Infinite cooling condition (refer to the SEMI G30-88). 8. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics. FSL137MRIN — Green-Mode Fairchild Power Switch (FPS™) Absolute Maximum Ratings IDS DMAX fSW Figure 4. Repetitive Peak Switching Current Thermal Impedance TA=25°C unless otherwise specified. Symbol θJA ΨJL Parameter Junction-to-Ambient Thermal Impedance Junction-to-Lead Thermal Impedance (9) (10) Value Unit 85 °C/W 11 °C/W Notes: 9. JEDEC recommended environment, JESD51-2, and test board, JESD51-10, with minimum land pattern. 10. Measured on drain pin #7, close to the plastic interface under Rthja test condition. © 2012 Fairchild Semiconductor Corporation FSL137MRIN • Rev. 1.0.3 www.fairchildsemi.com 4 TJ = 25C unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit SenseFET Section BVDSS Drain-Source Breakdown Voltage VCC=0 V, ID=250 A IDSS Zero-Gate-Voltage Drain Current VDS=560 V, TA=125C Drain-Source On-State Resistance VGS=10 V, ID=1 A 4.00 RDS(ON) (11) 700 V 250 µA 4.75 Ω CISS Input Capacitance VDS=25 V, VGS=0 V, f=1 MHz 315 pF COSS Output Capacitance(11) VDS=25 V, VGS=0 V, f=1 MHz 47 pF tr Rise Time VDS=325 V, ID=4 A, RG=25 Ω 34 ns tf Fall Time VDS=325 V, ID=4 A, RG=25 Ω 32 ns td(on) Turn-On Delay VDS=325 V, ID=4 A, RG=25 Ω 11.2 ns td(off) Turn-Off Delay VDS=325 V, ID=4 A, RG=25 Ω 28.2 ns Control Section Switching Frequency(11) VCC=14 V, VFB=4 V Switching Frequency Variation(11) -25C < TJ < 125C DMAX Maximum Duty Ratio VCC=14 V, VFB=4 V DMIN Minimum Duty Ratio VCC=14 V, VFB=0 V Feedback Source Current VFB=0 V fS fS IFB VSTART VSTOP tSS VRECOMM UVLO Threshold Voltage Internal Soft-Start Time 61 61 65 67 73 kHz ±5 ±10 % 67 73 % 0 % 115 µA 90 VFB=0 V, VCC Sweep 11 12 13 After Turn-on, VFB =0 V 7.0 7.5 8.0 VSTR=40 V, VCC Sweep Recommended VCC Range 15 13 V ms 23 V V FSL137MRIN — Green-Mode Fairchild Power Switch (FPS™) Electrical Characteristics Burst Mode Section VBURH VBURL Burst-Mode Voltage VCC=14 V, VFB Sweep 0.45 0.50 0.55 0.30 0.35 0.40 Hys 150 V mV Protection Section ILIM Peak Drain Current Limit di/dt=300 mA/s 1.1 1.3 1.5 A VSD Shutdown Feedback Voltage VCC=14 V, VFB Sweep 6.45 7.00 7.55 V Shutdown Delay Current VCC=14 V, VFB=4 V 1.2 2.0 2.8 µA IDELAY tLEB Leading-Edge Blanking Time(10,12) VOVP Over-Voltage Protection VCC Sweep 23.0 24.5 26.0 V VINH Line Over-Voltage Protection Threshold Voltage VCC=14 V, VIN Sweep 1.885 1.950 2.015 V VINHYS Line Over-Voltage Protection Hysteresis VCC=14 V, VIN Sweep tOSP VOSP tOSP_FB TSD THYS Threshold Time Output-Short Protection(11) Threshold VFB VFB Blanking Time Thermal Shutdown Temperature(11) 300 ns 0.06 V OSP Triggered when tON<tOSP & VFB>VOSP (Lasts Longer than tOSP_FB) 0.7 1.0 1.3 µs 1.8 2.0 2.2 V 2.0 2.5 3.0 µs Shutdown Temperature 125 135 145 C Hysteresis 60 C Continued on the following page… © 2012 Fairchild Semiconductor Corporation FSL137MRIN • Rev. 1.0.3 www.fairchildsemi.com 5 TJ = 25C unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit 0.3 0.4 0.5 mA 1.2 1.5 mA Total Device Section IOP Operating Supply Current, (Control Part in Burst Mode) VCC=14 V, VFB=0 V IOPS Operating Switching Current, (Control Part and SenseFET Part) VCC=14 V, VFB=2 V Start Current VCC=11 V (Before VCC Reaches VSTART) 85 120 155 µA Startup Charging Current VCC=VFB=0 V, VSTR=40 V 0.7 1.0 1.3 mA Minimum VSTR Supply Voltage VCC=VFB=0 V, VSTR Sweep ISTART ICH VSTR Notes: 11. These parameters are guaranteed; not 100% tested in production. 12. tLEB includes gate turn-on time. © 2012 Fairchild Semiconductor Corporation FSL137MRIN • Rev. 1.0.3 26 V FSL137MRIN — Green-Mode Fairchild Power Switch (FPS™) Electrical Characteristics (Continued) www.fairchildsemi.com 6 1.20 1.20 1.15 1.15 1.10 1.10 1.05 1.05 Normalized Normalized Characteristic graphs are normalized at TA=25°C. 1.00 0.95 0.90 1.00 0.95 0.90 0.85 0.85 0.80 -40'C -20'C 0'C 0.80 -40'C -20'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C 0'C Operating Supply Current (IOP) vs. TA Figure 6. 1.20 1.20 1.15 1.15 1.10 1.10 1.05 1.05 Normalized Normalized Figure 5. 1.00 0.95 0.90 Operating Switching Current (IOPS) vs. TA 1.00 0.95 0.90 0.85 0.85 0.80 -40'C -20'C 0'C 0.80 -40'C -20'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C 0'C Figure 8. 1.20 1.30 1.15 1.20 1.10 1.10 1.05 Normalized Normalized Startup Charging Current (ICH) vs. TA 1.40 1.00 0.90 0.80 0.70 Peak Drain Current Limit (ILIM) vs. TA 1.00 0.95 0.90 0.85 0.60 -40'C -20'C 0'C 0.80 -40'C -20'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C Temperature [ °C] Figure 9. 25'C 50'C 75'C 90'C 110'C 120'C 125'C Temperature [ °C] Temperature [ °C] Figure 7. 25'C 50'C 75'C 90'C 110'C 120'C 125'C Temperature [ °C] Temperature [ °C] FSL137MRIN — Green-Mode Fairchild Power Switch (FPS™) Typical Performance Characteristics 25'C 50'C 75'C 90'C 110'C 120'C 125'C Temperature [ °C] Feedback Source Current (IFB) vs. TA © 2012 Fairchild Semiconductor Corporation FSL137MRIN • Rev. 1.0.3 0'C Figure 10. Shutdown Delay Current (IDELAY) vs. TA www.fairchildsemi.com 7 1.20 1.20 1.15 1.15 1.10 1.10 1.05 1.05 Normalized Normalized Characteristic graphs are normalized at TA=25°C. 1.00 0.95 0.90 0.85 1.00 0.95 0.90 0.85 0.80 -40'C -20'C 0'C 0.80 -40'C -20'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C 0'C Temperature [ °C] Temperature [ °C] UVLO Threshold Voltage (VSTART) vs. TA Figure 12. 1.20 1.20 1.15 1.15 1.10 1.10 1.05 1.05 Normalized Normalized Figure 11. 1.00 0.95 0.90 UVLO Threshold Voltage (VSTOP) vs. TA 1.00 0.95 0.90 0.85 0.85 0.80 -40'C -20'C 0'C 0.80 -40'C -20'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C 0'C Figure 14. 1.20 1.20 1.15 1.15 1.10 1.10 1.05 1.05 Normalized Normalized Shutdown Feedback Voltage (VSD) vs. TA 1.00 0.95 0.90 1.00 0.95 0.90 0'C 0.80 -40'C -20'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C Switching Frequency(fS) vs. TA © 2012 Fairchild Semiconductor Corporation FSL137MRIN • Rev. 1.0.3 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C Temperature [ °C] Temperature [ °C] Figure 15. Over-Voltage Protection (VOVP) vs. TA 0.85 0.85 0.80 -40'C -20'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C Temperature [ °C] Temperature [ °C] Figure 13. 25'C 50'C 75'C 90'C 110'C 120'C 125'C FSL137MRIN — Green-Mode Fairchild Power Switch (FPS™) Typical Performance Characteristics Figure 16. Maximum Duty Ratio (DMAX) vs. TA www.fairchildsemi.com 8 Characteristic graphs are normalized at TA=25°C. 1.20 1.20 1.15 1.15 1.10 1.05 Normalized Normalized 1.10 1.00 0.95 1.05 1.00 0.95 0.90 0.90 0.85 0.85 0.80 -40'C -25'C 0'C 25'C 50'C 75'C 0.80 -40'C -25'C 90'C 110'C 120'C 125'C Temperature [ °C] Figure 17. 25'C 50'C 75'C 90'C 110'C 120'C 125'C Temperature [ °C] Line OVP (VINH) vs. TA © 2012 Fairchild Semiconductor Corporation FSL137MRIN • Rev. 1.0.3 0'C Figure 18. Hysteresis of LOVP (VINHYS) vs. TA FSL137MRIN — Green-Mode Fairchild Power Switch (FPS™) Typical Performance Characteristics www.fairchildsemi.com 9 1. Startup: At startup, an internal high-voltage current source supplies the internal bias and charges the external capacitor (CVCC) connected to the VCC pin, as illustrated in Figure 19. When VCC reaches 12 V, the FSL137MRIN begins switching and the internal highvoltage current source is disabled. Normal switching operation continues and the power is supplied from the auxiliary transformer winding unless VCC goes below the stop voltage of 7.5 V. 3. Feedback Control: This device employs CurrentMode control, as shown in Figure 20. An opto-coupler (such as the FOD817) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the RSENSE resistor makes it possible to control the switching duty cycle. When the reference pin voltage of the shunt regulator exceeds the internal reference voltage of 2.5 V, the opto-coupler LED current increases, pulling down the feedback voltage and reducing drain current. This typically occurs when the input voltage is increased or the output load is decreased. VDC CVCC VCC 3.1 Pulse-by-Pulse Current Limit: Because CurrentMode control is employed, the peak current through the SenseFET is limited by the inverting input of PWM comparator (VFB*), as shown in Figure 20. Assuming that the 90 μA current source flows only through the internal resistor (3R + R =25 kΩ), the cathode voltage of diode D2 is about 2.8 V. Since D1 is blocked when the feedback voltage (VFB) exceeds 2.84 V, the maximum voltage of the cathode of D2 is clamped at this voltage. Therefore, the peak value of the current through the SenseFET is limited. VSTR 2 5 ICH VREF VCC Good 7.5V/12.0V Internal Bias Figure 19. 3.2 Leading-Edge Blanking (LEB): At the instant the internal SenseFET is turned on, a high-current spike usually occurs through the SenseFET, caused by primary-side capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the RSENSE resistor leads to incorrect feedback operation in Current-Mode PWM control. To counter this effect, the LEB circuit inhibits the PWM comparator for tLEB (300 ns) after the SenseFET is turned on. Startup Block 2. Soft-Start: The internal soft-start circuit increases PWM comparator inverting input voltage, together with the SenseFET current, slowly after startup. The typical soft-start time is 15 ms. The pulse width to the power switching device is progressively increased to establish the correct working conditions for the transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased to smoothly establish the required output voltage. This helps prevent transformer saturation and reduces stress on the secondary diode during startup. FSL137MRIN — Green-Mode Fairchild Power Switch (FPS™) Functional Description Drain 6,7,8 VREF VCC IDELAY VOUT VFB IFB FB OSC 3R PWM 3 D1 FOD817 Gate Driver D2 VFB* CFB R LEB(300ns) KA431 OSP VOSP AOCP RSENSE VAOCP GND 1 OLP VSD Figure 20. © 2012 Fairchild Semiconductor Corporation FSL137MRIN • Rev. 1.0.3 Pulse Width Modulation Circuit www.fairchildsemi.com 10 B VDS increasing until it reaches 7.0 V, when the switching operation is terminated, as shown in Figure 22. The delay for shutdown is the time required to charge CFB from 2.5 V to 7.0 V with 2.0 µA. A 25 ~ 50 ms delay is typical for most applications. This protection is implemented as auto-restart. VFB Overload Protection B Fault occurs Power on 7.0V 2.5V t12= CFB×(7.0-2.5)/Idelay t1 Fault removed Figure 22. 12.0V 7.5V t Figure 21. Fault situation Normal operation Auto-Restart Protection Waveforms Overload Protection Drain 4.1 Overload Protection (OLP): Overload is defined as the load current exceeding its normal level due to an unexpected abnormal event. In this situation, the protection circuit should trigger to protect the SMPS. However, even when the SMPS is in normal operation, the overload protection circuit can be triggered during the load transition. To avoid this undesired operation, the overload protection circuit is designed to trigger only after a specified time to determine whether it is a transient situation or a true overload situation. Because of the pulse-by-pulse current-limit capability, the maximum peak current through the SenseFET is limited and, therefore, the maximum input power is restricted with a given input voltage. If the output consumes more than this maximum power, the output voltage (VOUT) decreases below the set voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, increasing the feedback voltage (VFB). If VFB exceeds 2.5 V, D1 is blocked and the 2.0 µA current source starts to charge CFB slowly up. In this condition, VFB continues © 2012 Fairchild Semiconductor Corporation FSL137MRIN • Rev. 1.0.3 t 4.2 Abnormal Over-Current Protection (AOCP): When the secondary rectifier diodes or the transformer pins are shorted, a steep current with extremely high di/dt can flow through the SenseFET during the minimum turn-on time. Even though the FSL137MRIN has overload protection, it is not enough to protect the FSL137MRIN in that abnormal case; due to the severe current stress imposed on the SenseFET until OLP is triggered. The internal AOCP circuit is shown in Figure 23. When the gate turn-on signal is applied to the power SenseFET, the AOCP block is enabled and monitors the current through the sensing resistor. The voltage across the resistor is compared with a preset AOCP level. If the sensingresistor voltage is greater than the AOCP level, the set signal is applied to the S-R latch, resulting in the shutdown of the SMPS. VCC Normal operation t2 FSL137MRIN — Green-Mode Fairchild Power Switch (FPS™) 4. Protection Circuits: The FSL137MRIN has several self-protective functions; such as Overload Protection (OLP), Abnormal Over-Current Protection (AOCP), Output-Short Protection (OSP), Over-Voltage Protection (OVP), and Thermal Shutdown (TSD). All the protections are implemented as auto-restart. Once a fault condition is detected, switching is terminated and the SenseFET remains off. This causes VCC to fall. When VCC falls to the Under-Voltage Lockout (UVLO) stop voltage of 7.5 V, the protection is reset and the startup circuit charges the VCC capacitor. When VCC reaches the start voltage of 12.0 V, normal operation resumes. If the fault condition is not removed, the SenseFET remains off and VCC drops to stop voltage again. In this manner, the auto-restart can alternately enable and disable the switching of the power SenseFET until the fault condition is eliminated. Because these protection circuits are fully integrated into the IC without external components, reliability is improved without increasing cost. 6,7,8 OSC 3R PWM VFB* Gate Driver R LEB (300ns) RSENSE Q GND S VAOCP Q R Figure 23. 1 VCC Good Abnormal Over-Current Protection www.fairchildsemi.com 11 4.6 Line Over-Voltage Protection (LOVP): If the line input voltage is increased to an undesirable level, high line input voltage creates high-voltage stress on the entire system. To protect from this abnormal condition, LOVP is included. It is comprised of detecting VIN using divided resistors. When VIN is higher than 1.95 V, this condition is recognized as an abnormal error and PWM switching shuts down until VIN decreases to around 1.89 V (60 mV hysteresis). VINH = 1.95 V VIN VINL = 1.89 V VAC MOSFET Drain Current Rectifier Diode Current ILIM VFB*=0.5V → VFB=2.0V VFB* IDS ILm 0 tOFF tON Output Short Occurs 1.0μs 1.0μs LOVP t LOVP triggered VOUT VSTART = 12.0 V VCC IOUT 0 t OSP Triggered OSP VSTOP = 7.5 V Figure 25. 0 Line Over-Voltage Protection t Figure 24. Unlike previous FPS families, FSL137MRIN’s VIN pin can detect the AC line over-voltage protection function. When line input voltage exceeds pre-determined level at the VIN pin, the controller initiates a fault signal and shuts down PWM output. To prevent erroneous activation of LOVP, the LOVP function is triggered when line over-voltage lasts more than specific time. Another important feature of LOVP function is auto-recovery. The controller continuously monitors line input voltage even under fault condition and turns PWM output on when over-voltage condition disappears. Equation (1) calculates the level of input over voltage to RMS value: Output-Short Protection 4.4 Over-Voltage Protection (OVP): If the secondary-side feedback circuit malfunctions or a solder defect causes an opening in the feedback path; the current through the opto-coupler transistor becomes almost zero. Then VFB climbs up in a similar manner to overload situation, forcing the preset maximum current to be supplied to the SMPS until the overload protection is triggered. Because more energy than required is provided to the output, the output voltage may exceed the rated voltage before the overload protection is triggered, resulting in the breakdown of the devices in the secondary side. To prevent this situation, an OVP circuit is employed. In general, the VCC is proportional to the output voltage and the FSL137MRIN uses VCC instead of directly monitoring the output voltage. If VCC exceeds 24.5 V, an OVP circuit is triggered, resulting in the termination of the switching operation. To avoid undesired activation of OVP during normal operation, VCC should be designed below 24.5 V. R1 R 2 VIN _ ovp 1.95 R 1 (1) The resistance of divided resistor can be adjusted as necessary. Small resistance can bring relatively large stand-by power consumption at light-load condition. To avoid this situation, a several MΩ resistor is recommended. For stable operation, a several MΩ resistor should accompany a capacitor with hundreds of pF capacitance between the VIN pin and GND. 4.5 Thermal Shutdown (TSD): The SenseFET and the control IC on a die in one package makes it easier for the control IC to detect the temperature of the SenseFET. If the temperature exceeds ~135C, the thermal shutdown is triggered and stops operation. The FSL137MRIN operates in Auto-Restart Mode until the temperature decreases to around 75C, when normal operation resumes. © 2012 Fairchild Semiconductor Corporation FSL137MRIN • Rev. 1.0.3 FSL137MRIN — Green-Mode Fairchild Power Switch (FPS™) 4.3. Output-Short Protection (OSP): If the output is shorted, steep current with extremely high di/dt can flow through the SenseFET during the minimum turnon time. Such a steep current creates high-voltage stress on the drain of the SenseFET when turned off. To protect the device from this abnormal condition, OSP is included. It is comprised of detecting VFB and SenseFET turn-on time. When the VFB is higher than 2.0 V and the SenseFET turn-on time is lower than 1.0 μs, this condition is recognized as an abnormal error and PWM switching shuts down until VCC reaches VSTART again. An abnormal condition output short is shown in Figure 24. www.fairchildsemi.com 12 6. Random Frequency Fluctuation (RFF): Fluctuating switching frequency of an SMPS can reduce EMI by spreading the energy over a wide frequency range. The amount of EMI reduction is directly related to the switching frequency variation, which is limited internally. The switching frequency is determined randomly by external feedback voltage and an internal free-running oscillator at every switching instant. RFF effectively scatters EMI noise around typical switching frequency (67 kHz) and can reduce the cost of the input filter included to meet the EMI requirements (e.g. EN55022). IDS VO fSW t ΔfSW VFB fSW t(μs) fSW+1/2ΔfSW 0.50V 0.35V t No repetition fSW-1/2ΔfSW IDS Soft Burst t(ms) Figure 27. t VDS Random Frequency Fluctuation FSL137MRIN — Green-Mode Fairchild Power Switch (FPS™) 5. Soft Burst Mode: To minimize power dissipation in Standby Mode, the FSL137MRIN enters Burst-Mode operation. As the load decreases, the feedback voltage decreases. As shown in Figure 26, the device automatically enters Burst Mode when the feedback voltage drops below VBURL (350 mV). At this point, switching stops and the output voltages start to drop at a rate dependent on standby current load. This causes the feedback voltage to rise. Once it passes VBURH (500 mV), switching resumes. The feedback voltage then falls and the process repeats. Burst Mode alternately enables and disables SenseFET switching, reducing switching loss in Standby Mode. t t1 Figure 26. Switching Disabled t2 t3 Switching Disabled t4 Burst-Mode Operation © 2012 Fairchild Semiconductor Corporation FSL137MRIN • Rev. 1.0.3 www.fairchildsemi.com 13 FSL137MRIN — Green-Mode Fairchild Power Switch (FPS™) Package Dimensions 9.83 9.00 6.67 6.096 8.255 7.61 3.683 3.20 5.08 MAX 7.62 0.33 MIN 3.60 3.00 (0.56) 2.54 0.56 0.355 0.356 0.20 9.957 7.87 1.65 1.27 7.62 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994 E) DRAWING FILENAME AND REVSION: MKT-N08FREV2. Figure 28. 8-Lead, MDIP, JEDEC MS-001, .300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/N0/N08F.pdf. © 2012 Fairchild Semiconductor Corporation FSL137MRIN • Rev. 1.0.3 www.fairchildsemi.com 14 FSL137MRIN — Green-Mode Fairchild Power Switch (FPS™) © 2012 Fairchild Semiconductor Corporation FSL137MRIN • Rev. 1.0.3 www.fairchildsemi.com 15