FSL306LR Green Mode Fairchild Buck Switch Features Description The FSL306LR integrate Pulse Width Modulator (PWM) and SenseFET is specifically designed for highperformance offline buck, buck-boost, and non-isolation flyback Switched Mode Power Supplies (SMPS) with minimal external components. This device integrates a high-voltage power regulator that enables operation without auxiliary bias winding. An internal transconductance amplifier reduces external components for the feedback compensation circuit. Built-in Avalanche Rugged SenseFET: 650 V Fixed Operating Frequency: 50 kHz No-Load Power Consumption: < 25 mW at 230 VAC with External Bias; <120 mW at 230 VAC without External Bias No Need for Auxiliary Bias Winding Fixed 650 ms Restart Time for Safe Auto-Restart Mode of All Protections Frequency Modulation for Attenuating EMI Pulse-by-Pulse Current Limiting Ultra-Low Operating Current: 250 µA Built-in Soft-Start and Startup Circuit Adjustable Peak Current Limit Built-in Transconductance (Error) Amplifier Various Protections: Overload Protection (OLP), Over-Voltage Protection (OVP), Feedback Open Loop Protection (FB_OLP), AOCP (Abnormal OverCurrent Protection), Thermal Shutdown (TSD) Applications SMPS for Home Appliances and Industrial Applications SMPS for Auxiliary Power The integrated PWM controller includes: 10 V regulator for no external bias circuit, Under-Voltage Lockout (UVLO), Leading-Edge Blanking (LEB), an optimized gate turn-on / turn-off driver, EMI attenuator, Thermal Shutdown (TSD), temperature-compensated precision current sources for loop compensation, and faultprotection circuitry. Protections include: Overload Protection (OLP), Over-Voltage Protection (OVP), Feedback Open Loop Protection (FB_OLP), and Abnormal Over-Current Protection (AOCP). FSL306LR offers good soft-start performance during startup. The internal high-voltage startup switch and the BurstMode operation with very low operating current reduce the power loss in Standby Mode. As the result, it is possible to reach power loss of 120 mW without external bias and 25 mW with external bias when input voltage is 230 VAC. Ordering Information Typical Output Power(1) Part Number FSL306LRN FSL306LRLX Operating Junction Temperature -40°C ~125°C PKG Packing Method 7-DIP Rail 7-LSOP Tape & Reel Current RDS(ON),MAX Limit 0.45 A 18 Ω 85 VAC ~ 265 VAC & Open Frame(2) Flyback Buck Application(3) Application 3W 7W Notes: 1. The junction temperature can limit the maximum output power. 2. Maximum practical continuous power in an open-frame design at 50°C ambient. 3. Based on 15 V output voltage condition. Output voltage can limit the maximum output power. © 2013 Fairchild Semiconductor Corporation FSL306LRN / FSL306LRL • Rev.1.0.3 www.fairchildsemi.com FSL306LRN — Green Mode Fairchild Buck Switch April 2014 + + DC OUT _ HV-DC INPUT VCOMP Drain Drain VFB VCC ILIMIT GND _ Figure 1. Buck Converter Application Figure 2. Non-Isolation Flyback Converter Application Block Diagram Figure 3. Internal Block Diagram © 2013 Fairchild Semiconductor Corporation FSL306LRN / FSL306LRL • Rev.1.0.3 www.fairchildsemi.com 2 FSL306LR — Green Mode Fairchild Buck Switch Application Diagrams Drain GND VCC Drain 7DIP ILIMIT VFB Vcomp Figure 4. Pin Configuration Pin Definitions Pin # Name 1 GND Ground. SenseFET source terminal on the primary side and internal control ground. 2 VCC Positive Supply Voltage Input. This pin is the positive supply input, which provides the internal operating current for startup and steady-state operation. This pin voltage is regulated to 10 V, without the external bias circuit, via internal switch (see Figure 3). When the external bias voltage is higher than 10 V, it disables the internal high-voltage regulator and reduces power consumption. 3 ILIMIT Peak Current Limit. Adjusts the peak current limit of the SenseFET. The internal 50 µA current source is diverted to the parallel combination of an internal 46 kΩ (3R + R) resistors and any external resistor to GND on this pin to determine the peak current limit. 4 VFB Feedback Voltage. Inverting input of the transconductance amplifier. This pin controls converter output voltage by outputting a current proportional to the difference between the reference voltage and the output voltage divided by external resistors. 5 VCOMP Comp Voltage. Output of the transconductance amplifier. The compensation networks are placed between the VCOMP and GND pins to achieve stability and good dynamic performance. Drain Drain. High-voltage power SenseFET drain connection. In addition, during startup and steadystate operation; the internal high-voltage current source supplies internal bias and charges the external capacitor connected to the VCC pin. Once VCC reaches 8 V, all internal blocks are activated. The internal high-voltage current source is enabled until VCC reaches 10 V. After that, the internal high-voltage regulator turns on and off regularly to maintain VCC at 10 V. 6,7 Description © 2013 Fairchild Semiconductor Corporation FSL306LRN / FSL306LRL • Rev.1.0.3 www.fairchildsemi.com 3 FSL306LR — Green Mode Fairchild Buck Switch Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = 25 °C, unless otherwise specified. Symbol Parameter Min. Max. Unit 650.0 V VDS Drain Pin Voltage -0.3 VCC Supply Voltage -0.3 26.0 V VCOMP VCOMP Pin Voltage -0.3 Internally Clamped Voltage(4) V VFB Feedback Voltage -0.3 12.0 V ILIMIT Current Limit Pin Voltage -0.3 12.0 V (5) IDM Drain Current Pulsed 2.8 A EAS Single Pulsed Avalanche Energy(6) 10.5 mJ PD Total Power Dissipation 1.25 W TJ TSTG Operating Junction Temperature (7) -40 Maximum Junction Temperature Storage Temperature -55 125 °C 150 °C 150 °C Notes: 4. VCOMP is clamped by internal clamping diode (11 V, ICLAMP_MAX < 100 μA) 5. Repetitive rating: pulse width is limited by maximum junction temperature. 6. L=10 mH, starting TJ=25C. 7. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics. Thermal Impedance TA=25°C unless otherwise specified. Symbol θJA Parameter Junction-to-Ambient Thermal Impedance (8) Value Unit 100 °C/W Note: 8. JEDEC recommended environment, JESD51-2, and test board, JESD51-3, with minimum land pattern. ESD Capability Symbol ESD Parameter Value (9) 4 Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101 (9) 2 Unit kV Note: 9. Meets JEDEC standards JESD 22-A114 and JESD 22-C101. © 2013 Fairchild Semiconductor Corporation FSL306LRN / FSL306LRL • Rev.1.0.3 www.fairchildsemi.com 4 FSL306LR — Green Mode Fairchild Buck Switch Absolute Maximum Ratings TA = 25C unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit SenseFET Section BVDSS Drain Source Breakdown Voltage VCC = 0 V, ID = 250 µA IDSS Zero Gate Voltage Drain Current VDS = 520 V, TA = 125°C Drain-Source On-State Resistance VGS = 10 V, ID = 0.3 A 12 CISS Input Capacitances VGS = 0 V, VDS = 25 V, f = 1 MHz 97 COSS Output Capacitance VGS = 0 V, VDS = 25 V, f = 1 MHz 13.6 pF CRSS Reverse Transfer Capacitance VGS = 0 V, VDS = 25 V, f = 1 MHz 2.4 pF tr Rise Time VDD = 325 V, ID = 0.7 A 7.6 ns tf Fall Time VDD = 325 V, ID = 0.7 A 26.1 ns RDS(ON) 650 V 250 µA 18 Ω pF Control Section fOSC fM ton.max VSTART VSTOP Switching Frequency Frequency Modulation VCOMP = 2.5 V (10) 45 VCOMP = 2.5 V, Randomly Maximum Turn-On Time UVLO Threshold Voltage 50 55 ±3 kHz kHz VCOMP = 2.5 V 11.2 13.3 15.4 µs VCOMP = 0 V, VCC Sweep 7.2 8.0 8.8 V After Turn On 6.3 7.0 7.7 V IPK Current Limit Source Current VCOMP = 2.5 V 35 50 65 µA tSS Soft-Start Time VCOMP = 2.5 V 7 10 13 ms Burst Mode Section VBURH Burst-mode HIGH Threshold Voltage VCC = 15 V, VCOMP Increase 0.58 0.65 0.72 V VBURL Burst-mode LOW Threshold Voltage 0.52 0.59 0.66 V HYSBUR VCC = 15 V, VCOMP Decrease Burst-mode Hysteresis 60 mV Protection Section ILIM Peak Current Limit VCOMP = 2.5 V, di/dt = 300 mA/µs, tCLD Current Limit Delay VOLP Overload Protection VAOCP Abnormal Over-Current Protection(10) VCOMP = 2.5 V tLEB VFB_OLP 0.40 0.45 (10) VCOMP Increase 0.50 A 200 ns 2.7 3.0 3.3 V 0.8 1.0 1.2 V Leading-Edge Blanking Time(10) 200 ns FB Open Loop Protection VFB Decrease 0.4 0.5 0.6 VOVP Over-Voltage Protection VCC Increase 23.0 24.5 26.0 V TSD Thermal Shutdown Temperature(10) 125 135 150 °C HYSTSD tDELAY tRESTART TSD Hysteresis Temperature(10) (10) Over Load Protection Delay 60 VCOMP > 3 V Restart Time After Protection(10) V °C 40 ms 650 ms Transconductance Amplifier Section Transconductance of Error Amplifier 190 240 290 µmho VREF Gm Voltage Feedback Reference 2.45 2.50 2.55 V IEA.SR Output Sourcing Current VFB = VREF - 0.05 V -12 µA IEA.SK Output Sink Current VFB = VREF + 0.05 V 12 µA Continued on the following page… © 2013 Fairchild Semiconductor Corporation FSL306LRN / FSL306LRL • Rev.1.0.3 www.fairchildsemi.com 5 FSL306LR — Green Mode Fairchild Buck Switch Electrical Characteristics TA = 25C unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit High-Voltage Regulator Section VHVREG HV Regulator Voltage VCOMP = 0 V, VDRAIN = 40 V 9 10 11 V Total Device Section IOP1 Operating Supply Current (Control Part Only, without Switching) 0 V < VCOMP < VBURL 0.25 0.35 mA IOP2 Operating Supply Current (While Switching) VBURL < VCOMP < VOLP 0.8 1.3 mA ICH Startup Charging Current VCC = 0 V, VDRAIN > 40 V ISTART Startup Current VCC = Before VSTART, VCOMP = 0 V 120 6 VDRAIN Minimum Drain Supply Voltage VCC = VCOMP = 0 V, VDRAIN Increase 35 mA 155 µA V Notes: 10. Though guaranteed by design, they are not 100% tested in production. © 2013 Fairchild Semiconductor Corporation FSL306LRN / FSL306LRL • Rev.1.0.3 www.fairchildsemi.com 6 FSL306LR — Green Mode Fairchild Buck Switch Electrical Characteristics HV Regulator Voltage (VHVREG) 1.15 1.10 1.10 1.05 1.05 Normalized Normalized Switching Frequency (fOSC) 1.15 1.00 0.95 0.90 1.00 0.95 0.90 0.85 0.85 ‐40 ‐20 0 25 50 75 100 125 ‐40 ‐20 Temperature (Ԩ) 25 50 75 100 125 Temperature (Ԩ) Figure 5. Operating Frequency vs. Temperature Figure 6. HV Regulator Voltage vs. Temperature Start Threshold Voltage (VSTART) Stop Threshold Voltage (VSTOP) 1.15 1.15 1.10 1.10 1.05 1.05 Normalized Normalized 0 1.00 0.95 0.90 1.00 0.95 0.90 0.85 0.85 ‐40 ‐20 0 25 50 75 100 125 ‐40 ‐20 Temperature (Ԩ) 0 25 50 75 100 125 Temperature (Ԩ) Figure 8. Stop Threshold Voltage vs. Temperature Burst Mode High Voltage (VBURH) Burst Mode Low Voltage (VBURL) 1.15 1.15 1.10 1.10 1.05 1.05 Normalized Normalized Figure 7. Start Threshold Voltage vs. Temperature 1.00 0.95 0.90 1.00 0.95 0.90 0.85 0.85 ‐40 ‐20 0 25 50 75 100 125 ‐40 Temperature (Ԩ) 0 25 50 75 100 125 Temperature (Ԩ) Figure 9. Burst Mode High Voltage vs. Temperature © 2013 Fairchild Semiconductor Corporation FSL306LRN / FSL306LRL • Rev.1.0.3 ‐20 Figure 10. Burst Mode Low Voltage vs. Temperature www.fairchildsemi.com 7 FSL306LR — Green Mode Fairchild Buck Switch Typical Performance Characteristics Feedback Voltage Reference (VREF) 1.15 1.10 1.10 1.05 1.05 Normalized Normalized Operating Supply Current (IOP1) 1.15 1.00 0.95 1.00 0.95 0.90 0.90 0.85 0.85 ‐40 ‐20 0 25 50 75 100 ‐40 125 ‐20 0 Figure 11. Operating Supply Current 1 vs. Temperature 75 100 125 Figure 12. Feedback Voltage Reference vs. Temperature Transconductance of gm amp (Gm) FB Open Loop Protection (VFB_OLP) 1.15 1.15 1.10 1.10 1.05 1.05 Normalized Normalized 50 Temperature (Ԩ) Temperature (Ԩ) 1.00 0.95 0.90 1.00 0.95 0.90 0.85 0.85 ‐40 ‐20 0 25 50 75 100 125 ‐40 ‐20 0 Temperature (Ԩ) 25 50 75 100 125 Temperature (Ԩ) Figure 14. FB Open Loop Protection Voltage vs. Temperature Figure 13. Transconductance of gm Amplifier vs. Temperature Overload Protection (VOLP) Over‐Voltage Protection (VOVP) 1.15 1.15 1.10 1.10 1.05 1.05 Normalized Normalized 25 1.00 0.95 1.00 0.95 0.90 0.90 0.85 0.85 ‐40 ‐20 0 25 50 75 100 ‐40 125 0 25 50 75 100 125 Temperature (Ԩ) Temperature (Ԩ) Figure 15. Overload Protection vs. Temperature © 2013 Fairchild Semiconductor Corporation FSL306LRN / FSL306LRL • Rev.1.0.3 ‐20 Figure 16. Over-Voltage Protection vs. Temperature www.fairchildsemi.com 8 FSL306LR — Green Mode Fairchild Buck Switch Typical Performance Characteristics (Continued) 1. Startup and High-Voltage Regulator 3. Feedback Control During startup, an internal high-voltage current source (ICH) of the high-voltage regulator supplies the internal bias current (ISTART) and charges the external capacitor (CA) connected to the VCC pin, as illustrated in Figure 17. This internal high-voltage current source is enabled until VCC reaches 10 V. During steady-state operation, this internal high-voltage regulator (HVREG) maintains the VCC with 10 V and provides operating current (IOP) for all internal circuits. Therefore, FSL306LR needs no external bias circuit. The high-voltage regulator is disabled when the external bias is higher than 10 V. employs current-mode control with a transconductance amplifier for feedback control, as shown in Figure 19. Two resistors are typically used on the VFB pin to sense output voltage. An external compensation circuit is recommended on the VCOMP pin to control output voltage. A built-in transconductance amplifier accurately controls output voltage without external components, such as Zener diode and transistor. Figure 19. Pulse Width Modulation (PWM) Circuit 3.1 Transconductance Amplifier (gm Amplifier) The output of the transconductance amplifier sources and sinks the current, respectively, to and from the compensation circuit connected on the VCOMP pin (see Figure 20). This compensated VCOMP pin voltage controls the switching duty cycle by comparing with the voltage across the RSENSE. When the feedback pin voltage exceeds the internal reference voltage (VREF) of 2.5 V; the transconductance amplifier sinks the current from the compensation circuit, VCOMP is pulled down, and the duty cycle is reduced. This typically occurs when input voltage is increased or output load is decreased. A two-pole and one-zero compensation network is recommended for optimal output voltage control and AC dynamics. Typically 220 nF, 220 kΩ, and 330 pF are used for CC1, RC1, and CC2, respectively. Figure 17. Startup and HVREG Block 2. Oscillator Block The oscillator frequency is set internally and the FSL306LR have random frequency fluctuation functions. Fluctuation of the switching frequency can reduce EMI by spreading the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. The amount of EMI reduction is directly related to the range of the frequency variation. The range of frequency variation is fixed internally; however, its selection is randomly chosen by the combination of an external feedback voltage and an internal freerunning oscillator. This randomly chosen switching frequency effectively spreads the EMI noise near switching frequency and allows the use of a costeffective inductor instead of an AC input line filter to satisfy world-wide EMI requirements. Figure 20. Characteristics of gm Amplifier 3.2 Pulse-by-pulse Current Limit Because current-mode control is employed, the peak current flowing through the SenseFET is limited by the inverting input of PWM comparator, as shown in Figure 19. Assuming that 50 µA current source flows only through the internal resistors (3R + R = 46 kΩ), Figure 18. Frequency Fluctuation Waveform © 2013 Fairchild Semiconductor Corporation FSL306LRN / FSL306LRL • Rev.1.0.3 www.fairchildsemi.com 9 FSL306LR — Green Mode Fairchild Buck Switch Functional Description 3.3 Leading Edge Blanking (LEB) At the instant the internal SenseFET is turned on; primary-side capacitance and secondary-side rectifier diode reverse recovery of flyback application, the freewheeling diode reverse recovery, and other parasitic capacitance of buck application typically cause a highcurrent spike through the SenseFET. Excessive voltage across the sensing resistor (RSENSE) leads to incorrect feedback operation in the current-mode control. To counter this effect, the FSL306LR have Leading-Edge Blanking (LEB) circuits (see Figure 19). This circuit inhibits the PWM comparator for a short time (tLEB) after the SenseFET is turned on. Figure 21. Overload Protection Internal Circuit 4. Protection Circuits The protective functions include Overload Protection (OLP), Over-Voltage Protection (OVP), Under-Voltage Lockout (UVLO), Feedback Open Loop Protection (FB_OLP), Abnormal Over-Current Protection (AOCP), and Thermal Shutdown (TSD). All of the protections operate in Auto-Restart Mode. Since these protection circuits are fully integrated inside the IC without external components, reliability is improved without increasing cost and PCB space. If a fault condition occurs, switching is terminated and the SenseFET remains off. At the same time, internal protection timing control is activated to decrease power consumption and stress on passive and active components during Auto-Restart. When internal protection timing control is activated, VCC is regulated with 10 V through the internal high-voltage regulator until switching is terminated. This internal protection timing control continues until restart time (650 ms) is counted. After counting to 650 ms, the internal high-voltage regulator is disabled and VCC is decreased. When VCC reaches the UVLO stop voltage VSTOP (7 V), the protection is reset and the internal highvoltage current source charges the VCC capacitor via the drain pin again. When VCC reaches the UVLO start voltage, VSTART (8 V), the FSL306LR resumes normal operation. In this manner, Auto-Restart can alternately enable and disable the switching of the power SenseFET until the fault condition is eliminated. Figure 22. Overload Protection (OLP) Waveform 4.2 Abnormal Over-Current Protection (AOCP) When output is shorted at high input voltage, much higher drain current peak than pulse-by-pulse current limit can flow through the SenseFET because turn on time is the same as the minimum turn-on time of FSL306LR. Even OLP is occasionally not enough to protect the FSL306LR in that abnormal case, since severe current stress is imposed on the SenseFET until OLP is triggered. FSL306LR includes the internal Abnormal Over-Current Protection (AOCP) circuit shown in Figure 23. The voltage across the RSENSE is compared with a preset AOCP level (VAOCP) after tLEB and, if the voltage across the RSENSE is greater than the AOCP level, the set signal is triggered after four switching times by an internal 2-bit counter, shutting down the SMPS, as shown in Figure 24. This LEB time can inhibit mis-triggering due to the leading-edge spike. 4.1 Overload Protection (OLP) Overload is defined as the load current exceeding a preset level due to an unexpected event. In this situation, the protection circuit should be activated to protect the SMPS. However, even when the SMPS operates normally, the OLP circuit can be enabled during the load transition or startup. To avoid this undesired operation, an internal fixed delay (40 ms) circuit determines whether it is a transient situation or a true overload situation (see Figure 21). The current-mode feedback path limits the maximum power current and, when the output consumes more than this maximum power, the output voltage (VO) decreases below its rated voltage. This reduces feedback pin voltage, which increases the output current of the internal transconductance amplifier. Eventually VCOMP is increased. When VCOMP © 2013 Fairchild Semiconductor Corporation FSL306LRN / FSL306LRL • Rev.1.0.3 Figure 23. AOCP Circuit Figure 24. AOCP Waveform www.fairchildsemi.com 10 FSL306LR — Green Mode Fairchild Buck Switch reaches 3 V, the internal fixed OLP delay (40 ms) is activated. After this delay, the switching operation is terminated, as shown in Figure 22. the cathode voltage of diode D2 is about 2.4 V. Since D1 is blocked when VCOMP exceeds 2.4 V, the maximum voltage of the cathode of D2 is clamped at this voltage. Therefore, the peak value of the current of the SenseFET is limited. 5. Soft-Start The internal soft-start circuit slowly increases the SenseFET current after it starts. The typical soft-start time is 10 ms, as shown in Figure 27, where progressive increments of the SenseFET current are allowed during startup. The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is gradually increased to smoothly establish the required output voltage. Soft-start also helps to prevent transformer saturation and reduces stress on the secondary diode. 4.4 Over-Voltage Protection (OVP) If any feedback loop components fail due to a soldering defect, VCOMP climbs up in manner similar to the overload situation, forcing the preset maximum current to be supplied to the SMPS until the OLP is triggered. In this case, excessive energy is provided to the output and the output voltage may exceed the rated voltage before the OLP is activated. To prevent this situation, an Over-Voltage Protection (OVP) circuit is employed. In general, output voltage can be monitored through VCC and, when VCC exceeds 24.5 V, OVP is triggered, resulting in termination of switching operation. To avoid undesired activation of OVP during normal operation, VCC should be designed below 24.5 V (see Figure 25). Figure 27. Internal Soft-Start 6. Burst Mode Operation To minimize power dissipation in Standby Mode, the FSL306LR enters Burst Mode. As the load decreases, the comp voltage (VCOMP) decreases. As shown in Figure 28, the device automatically enters Burst Mode when the feedback voltage drops below VBURL. At this point, switching stops and the output voltages start to drop at a rate dependent on the standby current load. This causes VCOMP to rise. Once it passes VBURH, switching resumes. VCOMP then falls and the process repeats. Burst Mode alternately enables and disables switching of the SenseFET and reduces switching loss in Standby Mode. Figure 25. Over Voltage Protection Circuit 4.5 Feedback Open Loop Protection (FB_OLP) In the event of a feedback loop failure, especially a shorted lower-side resistor of the feedback pin; not only does VCOMP rise in a similar manner to the overload situation, but VFB starts to drop to IC ground level. Although OLP and OVP also can protect the SMPS in this situation, FB_OLP can reduce stress on SenseFET more. If there is no FB_OLP, output voltage is much higher than rated voltage before OLP or OVP trigger. When VFB drops below 0.5 V, FB_OLP is activated, switching off. To avoid undesired activation during startup, this function is disabled during soft-start time. OSC 3R VOUT PWM R RH LEB VFB FB_OLP S Q R Q Gate driver RSENSE 4 FB_OLP RL VFB_OLP Figure 26. Feedback Open-loop Protection Circuit Figure 28. Burst Mode Operation © 2013 Fairchild Semiconductor Corporation FSL306LRN / FSL306LRL • Rev.1.0.3 www.fairchildsemi.com 11 FSL306LR — Green Mode Fairchild Buck Switch 4.3 Thermal Shutdown (TSD) The SenseFET and control IC integrated on the same package makes it easier to detect the temperature of the SenseFET. When the junction temperature exceeds 135°C, thermal shutdown is activated. The FSL306LR are restarted after the temperature decreases to 60°C. 8. Adjusting Current Limit As output load condition is reduced, the switching loss becomes the largest power loss factor. FSL306LR uses the VCOMP pin voltage to monitor output load condition. As output load decreases, VCOMP decreases and switching frequency declines, as shown in Figure 29. Once VCOMP falls to 0.8 V, the switching frequency varies between 21 kHz and 23 kHz before Burst Mode operation. At Burst Mode operation, random frequency fluctuation still functions. As shown in Figure 30, a combined 46 kΩ internal resistance (3R + R) is connected to the inverting lead on the PWM comparator. An external resistance of Rx on the ILIMIT pin forms a parallel resistance with the 46 kΩ when the internal diodes are biased by the main current source of 50 µA. For example, FSL306LR have a typical SenseFET peak current limit of 0.45 A. Current limit can be adjusted to 0.3 A by inserting RX between the ILIMIT pin and the ground. The value of the RX can be estimated by the following equation: Switching frequency Random Frequency modulation range 0.45 A : 0.3 A = (46 kΩ + RX) : RX 53 kHz (1) 47 kHz 23 kHz 21 kHz VBURL VBURH 0.8V 1.9V VCOMP Figure 29. Green Mode Operation Figure 30. Current Limit Adjustment © 2013 Fairchild Semiconductor Corporation FSL306LRN / FSL306LRL • Rev.1.0.3 www.fairchildsemi.com 12 FSL306LR — Green Mode Fairchild Buck Switch 7. Green Mode Operation Application Input Voltage Auxilary Power Rated Output 12 V (150 mA) 85 ~ 300 VAC Power Supply Rated Power 2.05 W 5 V (50 mA) Key Design Notes: Small current rating inductors (L1 & L2), an SMD-type resistor (R1), and an additional AC rectifying diode (D2) are placed for good EMI performance. External bias circuitry, a SMD-type resistor (R2), and a small-signal diode (D5) reduce power loss of the internal high-voltage regulator. Figure 31. Schematic Table 1. Bill of Materials Part Value Note Part Value Fuse F1 10 W Note Diode 1 W, Fusible Resistor Resistor R1 3.3 kΩ SMD 0805, 5% R2 10 Ω SMD 0805, 5% R3 20 kΩ SMD 0805, 1% R4 5.1 kΩ SMD 0805, 1% R5 220 kΩ SMD 0805, 5% Capacitor D1 S1M D2 S1M D3 ES1J D4 ES1J D5 1N4148 1 A / 1000 V General-Purpose Rectifier Fairchild Semiconductor 1 A / 1000 V General-Purpose Rectifier Fairchild Semiconductor 1 A / 600 V Ultra-Fast Recovery Rectifier Fairchild Semiconductor 1 A / 600 V Ultra-Fast Recovery Rectifier Fairchild Semiconductor C1 4.7 µF / 400 V Electrolytic C2 6.8 µF / 400 V Electrolytic C3 100 µF / 25 V Electrolytic C4 47 µF / 25 V Electrolytic L1 470 µH SYNTON C5 2.2 µF SMD 0805 L2 470 µH SYNTON C6 1 µF SMD 0805 L3 680 µH U1 FSL306LRN / FSL306LRL U2 KA78L05AIMTF C7 10 nF SMD 0805 C8 220 nF SMD 0805 C9 330 pF SMD 0805 © 2013 Fairchild Semiconductor Corporation FSL306LRN / FSL306LRL • Rev.1.0.3 High Conductance Fast Diode Fairchild Semiconductor Inductor PKS-0807-681K 3L Electronic Fairchild Semiconductor 0.1 A / 5 V Positive Voltage Regulator Fairchild Semiconductor www.fairchildsemi.com 13 FSL306LR — Green Mode Fairchild Buck Switch Typical Application Circuit 9.779 9.525 7 A 5 B NOTES : A. REFERENCE JEDEC MS-001, VARIATION BA EXCEPT FOR NUMBER OF LEADS. 6.477 6.223 B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009 PIN #1 D. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH AND TIE BAR EXTRUSIONS. E. DRAWING FILE NAME: MKT-NA07Drev1 4 1 (0.787) TOP VIEW 7.874 7.620 2.54 12° 12° 3.937 3.683 3.429 3.175 0.508 MIN SEATING PLANE 1.651 1.397 3.556 3.048 0.508 0.406 0.381 0.203 C 0.10 C 7.53 7.874 9.398 SIDE VIEW FRONT VIEW Figure 32. 7-Lead, Molded Dual Inline Package (MDIP), JEDEC MS-001, .300 inch Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2013 Fairchild Semiconductor Corporation FSL306LRN / FSL306LRL • Rev.1.0.3 www.fairchildsemi.com 14 FSL306LR — Green Mode Fairchild Buck Switch Physical Dimensions FSL306LR — Green Mode Fairchild Buck Switch Physical Dimensions (continued) MKT-MLSOP07ArevA Figure 33. 7-Lead, .300" Wide, Surface Mount Package (LSOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2013 Fairchild Semiconductor Corporation FSL306LRN / FSL306LRL • Rev.1.0.3 www.fairchildsemi.com 15 FSL306LR — Green Mode Fairchild Buck Switch © 2013 Fairchild Semiconductor Corporation FSL306LRN / FSL306LRL • Rev.1.0.3 www.fairchildsemi.com 16