FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13737-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90350 Series
MB90F352/S, MB90352/S
■ DESCRIPTION
The MB90350-series with 1 channel FULL-CAN* interface and FLASH ROM is especially designed for automotive
and industrial applications. Its main feature is the on-board CAN Interface, which conform to V2.0 Part A and Part
B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN
approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memory
up to 128 Kbytes. An internal voltage booster removes the necessity for a second programming voltage.
An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms
of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external
4 MHz clock.
The unit features a 4 channel Output Compare Unit and 6 channel Input Capture Unit with 2 separate 16-bit free
running timers. 2 channels UART constitute additional functionality for communication purposes.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH
Note : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
■ PACKAGE
64-pin Plastic LQFP
(FPT-64P-M09)
MB90350 Series
■ FEATURES
• Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed. (devices without
S-suffix only)
• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multiplied PLL clock).
• Built-in clock modulation circuit
• 16 Mbyte CPU memory space
• 24-bit internal addressing
• External Bus Interface
• 4 MByte external memory space
• Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• Enhanced multiply-divide instructions and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
• Increased processing speed
• 4-byte instruction queue
• Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 8 channels external interrupts are supported
• Automatic data transfer function independent of CPU
• Extended intelligent I/O service function (EI2OS) : up to 16 channels
• DMA : up to 16 channels
• Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Main timer mode (a timebase timer mode switched from the main clock mode)
• PLL timer mode (a timebase timer mode switched from the PLL clock mode)
• Watch mode (a mode that operates sub clock and clock timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking operation mode
• Process
• CMOS technology
• I/O port
• General-purpose input/output port (CMOS output)
- 49 ports (devices without S-suffix)
- 51 ports (devices with S-suffix)
(Continued)
2
MB90350 Series
(Continued)
• Timer
• Time-base timer, clock timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit × 10 channels, or 16-bit × 6 channels
• 16-bit reload timer : 4 channels
• 16- bit input/output timer
- 16-bit free run timer : 2 channels (FRT0 : ICU0/1, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)
- 16- bit input capture: (ICU) : 6 channels
- 16-bit output compare : (OCU) : 4 channels
• Full-CAN interface : 1 channel
• Compliant with Ver2.0A and Ver2.0B CAN specifications
• Flexible message buffering (mailbox and FIFO buffering can be mixed)
• CAN wake-up function
• UART (LIN/SCI) : 2 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available
• I2C interface* : 1 channel
• Up to 400 Kbit/s transfer rate
• DTP/External interrupt : 8 channels, CAN wakeup : 1 channel
• Module for activation of extended intelligent I/O service (EI2OS), DMA, and generation of external interrupt.
• Delay interrupt generator module
• Generates interrupt request for task switching.
• 8/10-bit A/D converter : 15 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)
• Program patch function
• Address matching detection for 6 address pointers.
• Internal voltage regulator
• Supports 3 V MCU core, offering low EMI and low power consumption figures
• Programmable input levels
• Automotive/CMOS-Schmitt (initial level is Automotive in Single chip mode)
• TTL level (initial level for External bus mode)
• Flash security function
• Protects the content of Flash (Flash device only)
* : I2C license :
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by
Philips.
3
MB90350 Series
■ PRODUCT LINEUP
Part Number
MB90F352/S, MB90352/S*1
MB90V340A-101/102
Parameter
F2MC-16LX CPU
CPU
System clock
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)
ROM
Boot-block, Flash memory
128 Kbytes
External
RAM
4 Kbytes
30 Kbytes
Yes
Emulator-specific
power supply*2
Technology
0.35 µm CMOS with regulator for internal power supply +
Flash memory charge pump for programming voltage
Operating
voltage range
3.5 V - 5.5 V : at normal operating (not using A/D converter)
4.0 V - 5.5 V : at using A/D converter/Flash programming
4.5 V - 5.5 V : at using external bus
Temperature range
Package
UART
I2C (400 kbit/s)
A/D
Converter
0.35 µm CMOS with
regulator for internal
power supply
5 V ± 10%
−40 °C to +105 °C (125 °C up to 16 MHz machine clock)
LQFP-64
PGA-299
2 channels
3 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
1 channel
1 channel
15 channels
10-bit or 8-bit resolution
Conversion time : Min 3 µs include sample time (per one channel)
16-bit Reload Timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
Supports External Event Count function
16-bit
I/O Timer
(2 channels)
Signals an interrupt when overflowing
Supports Timer Clear when a match with Output Compare (Channel 0, 4)
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7
16-bit Output
Compare
(4 channels)
Signals an interrupt when 16-bit I/O Timer match output compare registers.
A pair of compare registers can be used to generate an output signal.
16-bit Input Capture
(6 channels)
Rising edge, falling edge or rising & falling edge sensitive
Signals an interrupt upon external event
(Continued)
4
MB90350 Series
Part Number
MB90F352/S, MB90352/S*1
MB90V340A-101/102
Parameter
Supports 8-bit and 16-bit operation modes
8-bit reload counters × 12
8/16-bit
8-bit reload registers for L pulse width × 12
Programmable Pulse
8-bit reload registers for H pulse width × 12
Generator
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
6 channels (16-bit) /
8-bit prescaler + 8-bit reload counter
10 channels (8-bit)
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
1 channel
CAN Interface
External Interrupt
(8 channels)
2 channels
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA
D/A converter
1 channel
Subclock
(up to100 kHz)
devices with ‘S’-suffix and MB90V340A-102
: without subclock
devices without ‘S’-suffix and MB90V340A-101 : with subclock
I/O Ports
Virtually all external pins can be used as general purpose I/O port
All push-pull outputs
Bit-wise settable as input/output or peripheral signal
Settable as CMOS schmitt trigger/ automotive inputs (default)
TTL input level settable for external bus (30 terminals only for external bus)
Flash
Memory
Supports automatic programming, Embedded AlgorithmTM*3
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
*1 : The devices are under development.
*2 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
*3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
5
MB90350 Series
■ PIN ASSIGNMENTS
• MB90F352/S, MB90352/S
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
P15/AD13
P16/AD14
P17/AD15
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
P24/A20/IN0
RST
X1
X0
Vss
(TOP VIEW)
(LQFP-64P)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Vcc
49
32
P10/AD08/TIN1
P07/AD07/INT15
C
50
31
P25/A21/IN1/ADTG
51
30
P06/AD06/INT14
P44/SDA0/FRCK0
52
29
P05/AD05/INT13
P45/SCL0/FRCK1
53
28
P04/AD04/INT12
P30/ALE/IN4
54
27
P03/AD03/INT11
P31/RD/IN5
55
26
P02/AD02/INT10
P32/WRL/WR/INT10R
56
25
P01/AD01/INT9
P33/WRH
57
24
P00/AD00/INT8
P34/HRQ/OUT4
58
23
MD0
P35/HAK/OUT5
59
22
MD1
P36/RDY/OUT6
60
21
MD2
P37/CLK/OUT7
61
20
P41/X1A*
P60/AN0
62
19
P40/X0A*
P61/AN1
63
18
Vss
AVcc
64
17
P43/IN7/TX1
(FPT-64P-M09)
* : MB90F352/352
: X0A, X1A
MB90F352S/352S : P40, P41
6
P 4 2 /IN 6 /R X 1 /IN T 9 R
P 5 6 /A N 1 4
P55/AN13
P54/AN12/TOT3
P 53/A N 11/TIN 3
P 52/A N 10/S C K 2
P51/AN9/SOT2
P50/AN8/SIN2
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
AV ss
AVRH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MB90350 Series
■ PIN DESCRIPTION
Pin No.
LQFP64*
Pin name
46
X1
47
X0
45
RST
Circuit
type
A
E
P62 to P67
3 to 8
AN2 to AN7
I
10
O
P51
General purpose I/O port.
AN9
I
AN10
AN11
General purpose I/O port.
I
General purpose I/O port.
I
Analog input pin for A/D converter.
TIN3
Event input pin for reload timer3.
P54
General purpose I/O port.
AN12
I
P55, P56
AN13, AN14
IN6
RX1
I
General purpose I/O ports.
Analog input pins for A/D converter.
General purpose I/O port.
F
INT9R
Data sample input pin for input capture ICU6.
RX input pin for CAN1.
External interrupt request input pin for INT9.
P43
IN7
Analog input pin for A/D converter.
Output pin for reload timer3.
P42
17
Analog input pin for A/D converter.
Serial data output pin for UART2.
TOT3
16
Analog input pin for A/D converter.
Serial data output pin for UART2.
P53
14, 15
Analog input pin for A/D converter.
Serial data input pin for UART2.
SCK2
13
Analog input pins for A/D converter.
SIN2
P52
12
Reset input pin.
General purpose I/O port.
SOT2
11
Oscillation input pin.
Output pins for PPGs.
P50
AN8
Oscillation output pin.
General purpose I/O ports.
PPG4, 6, 8,
A, C, E
9
Function
General purpose I/O port.
F
TX1
Data sample input pin for input capture ICU7.
TX output pin for CAN1.
P40, P41
F
General purpose I/O ports
(devices with S-suffix and MB90V340A-101) .
X0A, X1A
B
Oscillation input pins for sub clock
(devices without S-suffix and MB90V340A-102) .
19, 20
(Continued)
7
MB90350 Series
Pin No.
LQFP64*
Pin name
Circuit
type
General purpose I/O ports.The register can be set to select whether to use
a pull-up resistor.This function is enabled in single-chip mode.
P00 to P07
24 to 31
AD00 to AD07
G
INT8 to INT15
33
AD08
General purpose I/O port.The register can be set to select whether to use
a pull-up resistor.This function is enabled in single-chip mode.
G
Event input pin for reload timer1.
P11
General purpose I/O.The register can be set to select whether to use a
pull-up resistor.This function is enabled in single-chip mode.
AD09
G
AD10
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
N
SIN3
External interrupt request input pin for INT11
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
P13
G
SOT3
AD12
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
G
SCK3
N
AD13
P16
38
G
AD14
Input/output pin for external bus address data bus bit 12.
This function is enabled when external bus is enabled.
Clock input/output pin for UART3.
P15
37
Input/output pin for external bus address data bus bit 11.
This function is enabled when external bus is enabled.
Serial data output pin for UART3.
P14
36
Input/output pin for external bus address data bus bit 10. This function is
enabled when external bus is enabled.
Serial data input pin for UART3.
INT11R
AD11
Input/output pin for external bus address data bus bit 9. This function is enabled when external bus is enabled.
Output pin for reload timer1.
P12
35
Input/output pin for external bus address data bus bit 8.
This function is enabled when external bus is enabled.
TIN1
TOT1
34
Input/output pins of external address data bus lower 8 bit. This function is
enabled when the external bus is enabled.
External interrupt request input pins for INT8 to INT15.
P10
32
Function
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 13.
This function is enabled when external bus is enabled.
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 14.
This function is enabled when external bus is enabled.
(Continued)
8
MB90350 Series
Pin No.
LQFP64*
Pin name
Circuit
type
P17
39
G
AD15
G
A16 to A19
PPG9, PPGB,
PPGD, PPGF
A20
Output pins for A20 of the external address bus. When the corresponding
bit in the external address output control register (HACR) is 0, the pin is
enabled as high address output pins A20.
IN0
Data sample input pin for input capture ICU0.
P25
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. In external bus mode, the pin is enabled as a generalpurpose I/O port when the corresponding bit in the external address output
control register (HACR) is 1.
A21
Output pin for A21 of the external address bus. When the corresponding bit
in the external address output control register (HACR) is 0, the pin is enabled as high address output pin A21.
IN1
Data sample input pin for input capture ICU1.
G
ADTG
Trigger input pin for A/D converter.
P44
SDA0
General purpose I/O port
H
FRCK0
SCL0
General purpose I/O port.
H
FRCK1
ALE
IN4
Serial clock I/O pin for I2C 0
Input for the 16-bit I/O Timer 1
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
P30
54
Serial data I/O pin for I2C 0
Input pin for the 16-bit I/O Timer 0
P45
53
Output pins for A16 to A19 of the external address bus.
When the corresponding bit in the external address output control register
(HACR) is 0, the pins are enabled as high address output pins A16 to A19.
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. In external bus mode, the pin is enabled as a generalpurpose I/O port when the corresponding bit in the external address output
control register (HACR) is 1.
G
51
52
Input/output pin for external bus address data bus bit 15.
This function is enabled when external bus is enabled.
Output pins for PPGs.
P24
44
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
General purpose I/O ports. The register can be set to select whether to use
a pull-up resistor. In external bus mode, the pin is enabled as a generalpurpose I/O port when the corresponding bit in the external address output
control register (HACR) is 1.
P20 to P23
40 to 43
Function
G
Address latch enable output pin. This function is enabled when external bus
is enabled.
Data sample input pin for input capture ICU4.
(Continued)
9
MB90350 Series
Pin No.
LQFP64*
Pin name
Circuit
type
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
P31
55
RD
Function
G
Read strobe output pin for data bus. This function is enabled when external
bus is enabled.
IN5
Data sample input pin for input capture ICU5.
P32
General purpose I/O port. The register can be set to select whether to use
pull-up resistor. This function is enabled either in single-chip mode or with
the WR/WRL pin output disabled.
56
G
WR/WRL
INT10R
External interrupt request input pin for INT10.
P33
57
Write strobe output pin for the data bus. This function is enabled when both
the external bus and the WR/WRL pin output are enabled. WRL is used to
write-strobe 8 lower bits of the data bus in 16-bit access. WR is used to
write-strobe 8 bits of the data bus in 8-bit access.
G
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the WRH pin output disabled.
WRH
Write strobe output pin for the 8 higher bits of the data bus. This function is
enabled when the external bus is enabled, when the external bus 16-bit
mode is selected, and when the WRH output pin is enabled.
P34
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the hold function disabled.
58
G
HRQ
Hold request input pin. This function is enabled when both the external bus
and the hold function are enabled.
OUT4
Waveform output pin for output compare OCU4.
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the hold function disabled.
P35
59
G
HAK
OUT5
Waveform output pin for output compare OCU5.
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the external ready function disabled.
P36
60
Hold acknowledge output pin. This function is enabled when both the
external bus and the hold function are enabled.
G
RDY
Ready input pin. This function is enabled when both the external bus and
the external ready function are enabled.
OUT6
Waveform output pin for output compare OCU6.
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the CLK output disabled.
P37
61
G
CLK
OUT7
CLK output pin. This function is enabled when both the external bus and
CLK output are enabled.
Waveform output pin for output compare OCU7.
(Continued)
10
MB90350 Series
(Continued)
Pin No.
LQFP64*
62, 63
Pin name
P60, P61
AN0, AN1
Circuit
type
I
Function
General purpose I/O ports.
Analog input pins for A/D converter.
64
AVCC
K
VCC power input pin for analog circuits.
2
AVRH
L
Reference voltage input for the A/D converter. This power supply must be
turned on or off while a voltage higher than or equal to AVRH is applied to
AVCC.
1
AVSS
K
VSS power input pin for analog circuits.
22, 23
MD1, MD0
C
Input pins for specifying the operating mode.
21
MD2
D
Input pins for specifying the operating mode.
49
VCC
Power (3.5 V to 5.5 V) input pin.
18, 48
VSS
Power (0 V) input pins.
50
C
K
This is the power supply stabilization capacitor pin. It should be connected
to a higher than or equal to 0.1 µF ceramic capacitor.
* : FPT-64P-M09
11
MB90350 Series
■ I/O CIRCUIT TYPE
Type
Circuit
X1
A
Remarks
Xout
Oscillation circuit
• High-speed oscillation feedback
resistor = approx. 1 MΩ
X0
Standby control signal
X1A
B
Xout
Oscillation circuit
• Low-speed oscillation feedback
resistor = approx. 10 MΩ
X0A
Standby control signal
Mask ROM device:
• CMOS Hysteresis input pin
C
R
Hysteresis
inputs
R
Hysteresis
inputs
D
Pull-down
Resistor
Flash device:
• CMOS input pin
Mask ROM device:
• CMOS Hysteresis input pin
• Pull-down resistor valule: approx. 50 kΩ
Flash device:
• CMOS input pin
• No Pull-down
CMOS Hysteresis input pin
• Pull-up resistor valule: approx. 50 kΩ
E
Pull-up
Resistor
R
Hysteresis
inputs
(Continued)
12
MB90350 Series
Type
Circuit
Remarks
Pout
Nout
F
R
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the standby-time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
pull-up control
pull-up
resistor
Pout
Nout
G
R
Hysteresis inputs
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the standby-time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
• TTL input (With the standby-time input
shutdown function)
• Programmalble pullup resistor: 50 kΩ
approx.
Automotive inputs
TTL input
Standby control for
input shutdown
Pout
Nout
H
• CMOS level output
(IOL = 3 mA, IOH = −3 mA)
• CMOS hysteresis inputs (With the standby-time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
R
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
(Continued)
13
MB90350 Series
Type
Circuit
Remarks
• CMOS level output(IOL = 4 mA)
• CMOS hysteresis inputs (With the standby-time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
• A/D analog input
Pout
Nout
R
I
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Analog input
• Power supply input protection circuit
K
ANE
L
AVR
• A/D converter reference voltage power
supply input pin, with the protection circuit
• Flash devices do not have a protection
circuit against VCC for pin AVRH
ANE
(Continued)
14
MB90350 Series
(Continued)
Type
Circuit
pull-up control
pull-up
registor
Pout
Nout
N
R
CMOS inputs
Remarks
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
• TTL input (With the standby-time input
shutdown function)
• Programmable pull-up registor:50 kΩ
approx
Automotive inputs
TTL input
Standby control for
input shutdown
Pout
Nout
R
O
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
• A/D analog input
CMOS inputs
Automotive inputs
Standby control for
input shutdown
Analog input
15
MB90350 Series
■ HANDLING DEVICES
Special care is required for the following when handling the device :
• Preventing latch-up
• Treatment of unused pins
• Using external clock
• Precautions for when not using a sub clock signal
• Notes on during operation of PLL clock mode
• Power supply pins (VCC/VSS)
• Pull-up/down resistors
• Crystal Oscillator Circuit
• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
• Connection of Unused Pins of A/D Converter
• Notes on Energization
• Stabilization of power supply voltage
• Initialization
• Port0 to port3 output during Power-on (External-bus mode)
• Notes on using CAN Function
• Flash security Function
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital
power-supply voltage.
2. Handling unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90350 Series
X0
Open
X1
4. Precautions for when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the
X1A pin open.
16
MB90350 Series
5. Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
6. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected inside of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
• Connect VCC and VSS to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
VCC and VSS in the vicinity of VCC and VSS pins of the device
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90350
Series
Vcc
Vss
Vss
Vcc
7. Pull-up/down resistors
The MB90350 Series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors).
Use external components where needed.
8. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
9. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN14) after
turning-on the digital power supply (VCC) .
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
10. Connection of Unused Pins of A/D Converter if A/D Converter is used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.
17
MB90350 Series
11. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
or more µs (0.2 V to 2.7 V)
12. Stabilization of power supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply
voltage operating range. Therefore, the VCC supply voltage should be stabilized.
For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak value) at
commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient
of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
13. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers,
turn on the power again.
14. Port 0 to port 3 output during Power-on (External-bus mode)
As shown below, when power is turned on in External-Bus mode, there is a possibility that output signal of
Port 0 to Port 3 might be unstable.
1/2 VCC
VCC
Port0 to Port3
Port0 to Port3 outputs
might be unstable
Port0 to Port3 outputs = Hi-Z
15. Notes on using CAN Function
To use CAN function, please set ’1’ to DIRECT bit of CAN Direct Mode Register (CDMR).
If DIRECT bit is set to ’0’ (initial value), wait states will be performed when accessing CAN registers.
Please refer to Hardware Manual of MB90350 series for detail of CAN Direct Mode Register.
16. Flash security Function
The security byte is located in the area of the flash memory.
If protection code 01H is written in the security bit, the flash memory is in the protected state by security.
Therefore please do not write 01H in this address if you do not use the security function.
Please refer to following table for the address of the security bit.
MB90F352
18
Flash memory size
Address for security bit
Embedded 1 Mbit Flash Memory
FE0001H
MB90350 Series
■ BLOCK DIAGRAMS
• MB90V340A-101/102
X0,X1
X0A,X1A *
RST
Clock
Controller
16LX
CPU
IO Timer 0
RAM 30 K
Input
Capture
6 ch
Output
Compare
4 ch
SOT4 to SOT2
SCK4 to SCK2
SIN4 to SIN2
AVCC
AVSS
AN14 to AN0
AVRH
Prescaler
3 ch
IO Timer 1
UART
3 ch
CAN
Controller
2 ch
16-bit Reload
Timer 4 ch
FRCK0
IN7 to IN4,
IN1 to IN0
OUT7 to OUT4
FRCK1
RX2 to RX1
TX2 to TX1
TIN3, TIN1
TOT3, TOT1
10-bit ADC
15 ch
ADTG
DA00
10-bit
DAC
1 ch
FMC-16 Bus
AD15 to AD00
A21 to A16
ALE
RD
External
Bus
Interface
WRL
WRH
HRQ
PPGF to PPG8,
PPG6, PPG4,
PPG2, PPG0
SDA0
SCL0
HAK
8/16-bit
PPG
12/8 ch
I2C
Interface
1 ch
RDY
CLK
External
Interrupt
INT15 to INT8
(INT11R to INT9R)
DMAC
* : MB90V340A-102
19
MB90350 Series
• MB90F352/S, MB90352/S
X0,X1
X0A,X1A*
RST
Clock
Controller
16LX
CPU
IO Timer 0
RAM
4K
Input
Capture
6 ch
ROM/Flash
128 K
SOT3, SOT2
SCK3, SCK2
SIN3, SIN2
AVCC
AVSS
AN14 to AN0
Output
Compare
4 ch
Prescaler
2 ch
IO Timer 1
UART
2 ch
CAN
Controller
1 ch
16-bit Reload
Timer 4 ch
IN7 to IN4,
IN1, IN0
OUT7 to OUT4
FRCK1
RX1
TX1
TIN3, TIN1
TOT3, TOT1
10-bit ADC
15 ch
AD15 to AD00
FMC-16 Bus
AVRH
ADTG
PPGF to PPG8
PPG6, PPG4
FRCK0
A21 to A16
ALE
RD
External
Bus
Interface
8/16-bit
PPG
10/6 ch
WRL
WRH
HRQ
HAK
RDY
SDA0
SCL0
CLK
I2C
Interface
1 ch
External
Interrupt
DMAC
* : Only for devices without ‘S’ Suffix
20
INT15 to INT8
(INT11R to INT9R)
MB90350 Series
■ MEMORY MAP
MB90V340A-101/102
FFFFFFH
ROM (FF bank)
MB90F352/S
MB90352/S
FFFFFFH
ROM (FF bank)
FF0000H
FEFFFFH
FF0000H
FEFFFFH
ROM (FE bank)
FE0000H
FDFFFFH
FE0000H
FDFFFFH
ROM (FE bank)
External access
area
C00100H
C000FFH
00FFFFH
008000H
007FFFH
ROM
(image of FF bank)
00FFFFH
008000H
007FFFH
Peripheral
007900H
0078FFH
ROM
(image of FF bank)
Peripheral
007900H
RAM 30 K
001100H
0010FFH
RAM 4 K
000100H
000100H
0000EFH
000000H
0000EFH
000000H
External access area
Peripheral
Peripheral
: No access
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without
using the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
21
MB90350 Series
■ I/O MAP
Address
Register
Abbreviation
Access
Resource name
Initial value
00H
Port 0 Data Register
PDR0
R/W
Port 0
XXXXXXXX
01H
Port 1 Data Register
PDR1
R/W
Port 1
XXXXXXXX
02H
Port 2 Data Register
PDR2
R/W
Port 2
XXXXXXXX
03H
Port 3 Data Register
PDR3
R/W
Port 3
XXXXXXXX
04H
Port 4 Data Register
PDR4
R/W
Port 4
XXXXXXXX
05H
Port 5 Data Register
PDR5
R/W
Port 5
XXXXXXXX
06H
Port 6 Data Register
PDR6
R/W
Port 6
XXXXXXXX
07H to 0AH
Reserved
0BH
Analog Input Enable Register 5
ADER5
R/W
Port 5, A/D
11111111
0CH
Analog Input Enable Register 6
ADER6
R/W
Port 6, A/D
11111111
0DH
Reserved
0EH
Input Level Select Register 0
ILSR0
R/W
Ports
00000000
0FH
Input Level Select Register 1
ILSR1
R/W
Ports
00000000
10H
Port 0 Direction Register
DDR0
R/W
Port 0
00000000
11H
Port 1 Direction Register
DDR1
R/W
Port 1
00000000
12H
Port 2 Direction Register
DDR2
R/W
Port 2
XX000000
13H
Port 3 Direction Register
DDR3
R/W
Port 3
00000000
14H
Port 4 Direction Register
DDR4
R/W
Port 4
XX000000
15H
Port 5 Direction Register
DDR5
R/W
Port 5
XX000000
16H
Port 6 Direction Register
DDR6
R/W
Port 6
00000000
W
UART2, UART3
X00XXXXX
17H to 19H
1AH
Reserved
SIN input Level Setting Register
DDRA
Reserved
1BH
1CH
Port 0 Pull-up Control Register
PUCR0
R/W
Port 0
00000000
1DH
Port 1 Pull-up Control Register
PUCR1
R/W
Port 1
00000000
1EH
Port 2 Pull-up Control Register
PUCR2
R/W
Port 2
00000000
1FH
Port 3 Pull-up Control Register
PUCR3
R/W
Port 3
00000000
20H to 37H
38H
Reserved
PPG 4 Operation Mode Control Register
PPGC4
W, R/W
39H
PPG 5 Operation Mode Control Register
PPGC5
W, R/W
3AH
PPG 45 Clock Select Register
PPG45
R/W
3BH
Program Address Detection Control
Status Register 1
PACSR1
R/W
0X000XX1
16-bit Programable
Pulse Generator 4/5
0X000001
000000X0
Address Match
Detection 1
00000000
(Continued)
22
MB90350 Series
Address
Register
Abbreviation
Access
3CH
PPG 6 Operation Mode Control Register
PPGC6
W, R/W
3DH
PPG 7 Operation Mode Control Register
PPGC7
W, R/W
3EH
PPG 67 Clock Select Register
PPG67
R/W
3FH
40H
Resource name
Initial value
0X000XX1
16-bit Programable
Pulse Generator 6/7
0X000001
000000X0
Reserved
PPG 8 Operation Mode Control Register
PPGC8
W, R/W
0X000XX1
16-bit Programable
Pulse Generator 8/9
41H
PPG 9 Operation Mode Control Register
PPGC9
W, R/W
42H
PPG 89 Clock Select Register
PPG89
R/W
000000X0
W, R/W
0X000XX1
Reserved
43H
44H
PPG A operation mode control register
PPGCA
45H
PPG B operation mode control register
PPGCB
46H
PPG AB clock select register
PPGAB
47H
48H
16-bit Programable
W, R/W
Pulse Generator A/B
R/W
000000X0
W,R/W
0X000XX1
PPG C Operation Mode Control Register
PPGCC
PPG D Operation Mode Control Register
PPGCD
W,R/W
4AH
PPG CD Clock Select Register
PPGCD
R/W
4BH
PPG E Operation Mode Control Register
PPGCE
0X000001
000000X0
W,R/W
PPG F Operation Mode Control Register
PPGCF
W,R/W
4EH
PPG EF Clock Select Register
PPGEF
R/W
4FH
0X000XX1
16-bit Programable
Pulse Generator E/F
0X000001
000000X0
Reserved
50H
Input Capture Control Status
Register 0/1
ICS01
R/W
51H
Input Capture Edge Register 0/1
ICE01
R/W, R
52H, 53H
Input Capture 0/1
00000000
XXX0X0XX
Reserved
54H
Input Capture Control Status
Register 4/5
ICS45
R/W
55H
Input Capture Edge Register 4/5
ICE45
R
56H
Input Capture Control Status
Register 6/7
ICS67
R/W
57H
Input Capture Edge Register 6/7
ICE67
R/W, R
58H to 5BH
5DH
16-bit Programable
Pulse Generator C/D
Reserved
4DH
5CH
0X000001
Reserved
49H
4CH
0X000001
Input Capture 4/5
00000000
XXXXXXXX
Input Capture 6/7
00000000
XXX000XX
Reserved
Output Compare Control Status
Register 4
OCS4
Output Compare Control Status
Register 5
OCS5
R/W
0000XX00
Output Compare 4/5
R/W
0XX00000
(Continued)
23
MB90350 Series
Abbreviation
Access
Output Compare Control Status
Register 6
OCS6
R/W
5FH
Output Compare Control Status
Register 7
OCS7
R/W
60H
Timer Control Status Register 0
TMCSR0
R/W
61H
Timer Control Status Register 0
TMCSR0
R/W
62H
Timer Control Status Register 1
TMCSR1
R/W
63H
Timer Control Status Register 1
TMCSR1
R/W
64H
Timer Control Status Register 2
TMCSR2
R/W
65H
Timer Control Status Register 2
TMCSR2
R/W
66H
Timer Control Status Register 3
TMCSR3
R/W
67H
Timer Control Status Register 3
TMCSR3
R/W
68H
A/D Control Status Register 0
ADCS0
R/W
000XXXX0
69H
A/D Control Status Register 1
ADCS1
R/W
0000000X
6AH
Data Register 0
ADCR0
R
6BH
Data Register 1
ADCR1
R
6CH
A/D Setting Register 0
ADSR0
R/W
00000000
6DH
A/D Setting Register 1
ADSR1
R/W
00000000
Address
5EH
Register
6EH
6FH
Resource name
Initial value
0000XX00
Output Compare 6/7
0XX00000
16-bit Reload Timer
0
16-bit Reload Timer
1
16-bit Reload Timer
2
16-bit Reload Timer
3
A/D Converter
00000000
XXXX0000
00000000
XXXX0000
00000000
XXXX0000
00000000
XXXX0000
00000000
XXXXXX00
Reserved
ROM Mirroring Register
70H to 7FH
ROMM
W
ROM Mirror
XXXXXXX1
Reserved
80H to 8FH Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
90H to 9AH
Reserved
9BH
DMA Descriptor Channel Specification
Register
DCSR
R/W
9CH
DMA Status Register L
DSRL
R/W
9DH
DMA Status Register H
DSRH
R/W
9EH
Program Address Detection Control
Status Register 0
PACSR0
R/W
Address Match
Detection 0
00000000
9FH
Delayed Interrupt/Release
DIRR
R/W
Delayed Interrupt
00000000
A0H
Low-power Mode Control Register
LPMCR
W,R/W
Low Power Control
Circuit
00011000
A1H
Clock Selection Register
CKSCR
R,R/W
Low Power Control
Circuit
11111100
R/W
DMA
00000000
A2H, A3H
A4H
00000000
DMA
00000000
00000000
Reserved
DMA Stop Status Register
DSSR
(Continued)
24
MB90350 Series
Abbreviation
Access
Automatic Ready Function Selection
Register
ARSR
W
A6H
External Address Output Control Register
HACR
W
A7H
Bus Control Signal Selection Register
ECSR
W
A8H
Watchdog Timer Control Register
WDTC
R,W
Watchdog Timer
XXXXX111
A9H
Timebase Timer Control Register
TBTC
W,R/W
Time base timer
1XX00100
AAH
Watch Timer Control Register
WTC
R,R/W
Watch timer
1X001000
Address
A5H
Register
ABH
Resource name
Initial value
0011XX00
External Memory
Access
00000000
0000000X
Reserved
ACH
DMA Enable Register L
DERL
R/W
ADH
DMA Enable Register H
DERH
R/W
AEH
Flash Control Status Register
(Flash Devices only. Otherwise
reserved)
FMCS
R,R/W
AFH
DMA
Flash Memory
00000000
00000000
000X0000
Reserved
B0H
Interrupt Control Register 00
ICR00
W,R/W
00000111
B1H
Interrupt Control Register 01
ICR01
W,R/W
00000111
B2H
Interrupt Control Register 02
ICR02
W,R/W
00000111
B3H
Interrupt Control Register 03
ICR03
W,R/W
00000111
B4H
Interrupt Control Register 04
ICR04
W,R/W
00000111
B5H
Interrupt Control Register 05
ICR05
W,R/W
00000111
B6H
Interrupt Control Register 06
ICR06
W,R/W
00000111
B7H
Interrupt Control Register 07
ICR07
W,R/W
B8H
Interrupt Control Register 08
ICR08
W,R/W
B9H
Interrupt Control Register 09
ICR09
W,R/W
00000111
BAH
Interrupt Control Register 10
ICR10
W,R/W
00000111
BBH
Interrupt Control Register 11
ICR11
W,R/W
00000111
BCH
Interrupt Control Register 12
ICR12
W,R/W
00000111
BDH
Interrupt Control Register 13
ICR13
W,R/W
00000111
BEH
Interrupt Control Register 14
ICR14
W,R/W
00000111
BFH
Interrupt Control Register 15
ICR15
W,R/W
00000111
C0H to C9H
Interrupt Control
00000111
00000111
Reserved
(Continued)
25
MB90350 Series
Address
Register
Abbreviation
Access
Resource name
Initial value
CAH
External Interrupt Request Enable
Register 1
ENIR1
R/W
00000000
CBH
External Interrupt Request Register 1
EIRR1
R/W
XXXXXXXX
CCH
External Interrupt Level Register 1
ELVR1
R/W
CDH
External Interrupt Level Register 1
ELVR1
R/W
00000000
CEH
External Interrupt Source Select
Register
EISSR
R/W
00000000
CFH
PLL/Subclock Control register
PSCCR
W
D0H
DMA Buffer Address Pointer L
BAPL
R/W
XXXXXXXX
D1H
DMA Buffer Address Pointer M
BAPM
R/W
XXXXXXXX
D2H
DMA Buffer Address Pointer H
BAPH
R/W
XXXXXXXX
D3H
DMA Control Register
DMACS
R/W
D4H
I/O Register Address Pointer L
IOAL
R/W
D5H
I/O Register Address Pointer H
IOAH
R/W
XXXXXXXX
D6H
Data Counter L
DCTL
R/W
XXXXXXXX
D7H
Data Counter H
DCTH
R/W
XXXXXXXX
D8H
Serial Mode Register 2
SMR2
W,R/W
00000000
D9H
Serial Control Register 2
SCR2
W,R/W
00000000
DAH
Reception/Transmission Data Register
2
RDR2/
TDR2
R/W
00000000
DBH
Serial Status Register 2
SSR2
R,R/W
DCH
Extended Communication Control
Register 2
ECCR2
R,W,
R/W
DDH
Extended Status/Control Register 2
ESCR2
R/W
00000100
DEH
Baud Rate Reload Register 20
BGR20
R/W
00000000
DFH
Baud Rate Reload Register 21
BGR21
R/W
00000000
E0H to EFH
Reserved
F0H to FFH
External
7900H to
7907H
Reserved
External Interrupt 1
PLL
DMA
UART2
00000000
XXXX0000
XXXXXXXX
XXXXXXXX
00001000
000000XX
(Continued)
26
MB90350 Series
Address
Register
Abbreviation
Access
Resource name
Initial value
7908H
Reload Register L4
PRLL4
R/W
7909H
Reload Register H4
PRLH4
R/W
790AH
Reload Register L5
PRLL5
R/W
790BH
Reload Register H5
PRLH5
R/W
XXXXXXXX
790CH
Reload Register L6
PRLL6
R/W
XXXXXXXX
790DH
Reload Register H6
PRLH6
R/W
790EH
Reload Register L7
PRLL7
R/W
790FH
Reload Register H7
PRLH7
R/W
XXXXXXXX
7910H
Reload Register L8
PRLL8
R/W
XXXXXXXX
7911H
Reload Register H8
PRLH8
R/W
7912H
Reload Register L9
PRLL9
R/W
7913H
Reload Register H9
PRLH9
R/W
XXXXXXXX
7914H
Reload Register LA
PRLLA
R/W
XXXXXXXX
7915H
Reload Register HA
PRLHA
R/W
7916H
Reload Register LB
PRLLB
R/W
7917H
Reload Register HB
PRLHB
R/W
XXXXXXXX
7918H
Reload Register LC
PRLLC
R/W
XXXXXXXX
7919H
Reload Register HC
PRLHC
R/W
791AH
Reload Register LD
PRLLD
R/W
791BH
Reload Register HD
PRLHD
R/W
XXXXXXXX
791CH
Reload Register LE
PRLLE
R/W
XXXXXXXX
791DH
Reload Register HE
PRLHE
R/W
791EH
Reload Register LF
PRLLF
R/W
791FH
Reload Register HF
PRLHF
R/W
XXXXXXXX
7920H
Input Capture Data Register 0
IPCP0
R
XXXXXXXX
7921H
Input Capture Data Register 0
IPCP0
R
7922H
Input Capture Data Register 1
IPCP1
R
7923H
Input Capture Data Register 1
IPCP1
R
XXXXXXXX
XXXXXXXX
7924H to
7927H
XXXXXXXX
16-bit Programable
Pulse
Generator 4/5
16-bit Programable
Pulse
Generator 6/7
16-bit Programable
Pulse
Generator 8/9
16-bit Programable
Pulse
Generator A/B
16-bit Programable
Pulse
Generator C/D
16-bit Programable
Pulse
Generator E/F
Input Capture 0/1
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Reserved
7928H
Input Capture Data Register 4
IPCP4
R
7929H
Input Capture Data Register 4
IPCP4
R
792AH
Input Capture Data Register 5
IPCP5
R
792BH
Input Capture Data Register 5
IPCP5
R
Input Capture 4/5
XXXXXXXX
XXXXXXXX
XXXXXXXX
(Continued)
27
MB90350 Series
Address
Register
Abbreviation
Access
Resource name
Initial value
792CH
Input Capture Data Register 6
IPCP6
R
792DH
Input Capture Data Register 6
IPCP6
R
792EH
Input Capture Data Register 7
IPCP7
R
792FH
Input Capture Data Register 7
IPCP7
R
XXXXXXXX
XXXXXXXX
7930H to
7937H
XXXXXXXX
Input Capture 6/7
XXXXXXXX
XXXXXXXX
Reserved
7938H
Output Compare Register 4
OCCP4
R/W
7939H
Output Compare Register 4
OCCP4
R/W
793AH
Output Compare Register 5
OCCP5
R/W
793BH
Output Compare Register 5
OCCP5
R/W
XXXXXXXX
793CH
Output Compare Register 6
OCCP6
R/W
XXXXXXXX
793DH
Output Compare Register 6
OCCP6
R/W
793EH
Output Compare Register 7
OCCP7
R/W
793FH
Output Compare Register 7
OCCP7
R/W
XXXXXXXX
7940H
Data Register 0
TCDT0
R/W
00000000
7941H
Data Register 0
TCDT0
R/W
7942H
Control status Register 0
TCCSL0
R/W
7943H
Control status Register 0
TCCSH0
R/W
0XXXXXXX
7944H
Data Register 1
TCDT1
R/W
00000000
7945H
Data Register 1
TCDT1
R/W
7946H
Control status Register 1
TCCSL1
R/W
7947H
Control status Register 1
TCCSH1
R/W
Timer Register 0/Reload Register 0
TMR0/
TMRLR0
R/W
Timer Register 1/Reload Register 1
TMR1/
TMRLR1
R/W
Timer Register 2/Reload Register 2
TMR2/
TMRLR2
R/W
Timer Register 3/Reload Register 3
TMR3/
TMRLR3
R/W
7948H
7949H
794AH
794BH
794CH
794DH
794EH
794FH
R/W
R/W
R/W
R/W
Output Compare 4/5
Output Compare 6/7
I/O Timer 0
I/O Timer 1
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
00000000
00000000
00000000
00000000
0XXXXXXX
16-bit Reload
Timer 0
XXXXXXXX
16-bit Reload
Timer 1
XXXXXXXX
16-bit Reload
Timer 2
XXXXXXXX
16-bit Reload
Timer 3
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
(Continued)
28
MB90350 Series
Address
Register
Abbreviation
Access
Resource name
Initial value
7950H
Serial Mode Register 3
SMR3
W, R/W
00000000
7951H
Serial Control Register 3
SCR3
W, R/W
00000000
7952H
Reception/Transmission Data Register
3
RDR3/
TDR3
R/W
00000000
7953H
Serial Status Register 3
SSR3
R,R/W
7954H
Extended Communication Control Register 3
ECCR3
R,W,
R/W
7955H
Extended Status/Control Register 3
ESCR3
R/W
00000100
7956H
Baud Rate Reload Register 30
BGR30
R/W
00000000
7957H
Baud Rate Reload Register 31
BGR31
R/W
00000000
7958H to
796DH
796EH
UART3
00001000
000000XX
Reserved
CAN Direct Mode Register
CDMR
R/W
CAN clock sync
XXXXXXX0
Reserved
796FH
7970H
I2C Bus Status Register 0
IBSR0
R
00000000
7971H
I2C Bus Control Register 0
IBCR0
W,R/W
00000000
ITBAL0
R/W
00000000
ITBAH0
R/W
7972H
7973H
7974H
7975H
7976H
I2C 10 bit Slave Address Register 0
I2C 10 bit Slave Address Mask Register
0
ITMKL0
R/W
00000000
2
I C Interface 0
11111111
ITMKH0
R/W
00111111
2
ISBA0
R/W
00000000
2
I C 7 bit Slave Address Register 0
7977H
I C 7 bit Slave Address Mask Register 0
ISMK0
R/W
01111111
7978H
I2C data register 0
IDAR0
R/W
00000000
7979H,
797AH
797BH
Reserved
I2C Clock Control Register 0
797CH to
79C1H
79C2H
79C3H to
79DFH
ICCR0
R/W
I2C Interface 0
00011111
R,R/W
Clock Modulator
0001X000
Reserved
Clock Modulator Control Register
CMCR
Reserved
(Continued)
29
MB90350 Series
(Continued)
Address
Register
Abbreviation
Access
79E0H
Program Address Detection Register 0
PADR0
R/W
XXXXXXXX
79E1H
Program Address Detection Register 0
PADR0
R/W
XXXXXXXX
79E2H
Program Address Detection Register 0
PADR0
R/W
XXXXXXXX
79E3H
Program Address Detection Register 1
PADR1
R/W
Resource name
Initial value
XXXXXXXX
Address Match
Detection 0
79E4H
Program Address Detection Register 1
PADR1
R/W
79E5H
Program Address Detection Register 1
PADR1
R/W
XXXXXXXX
79E6H
Program Address Detection Register 2
PADR2
R/W
XXXXXXXX
79E7H
Program Address Detection Register 2
PADR2
R/W
XXXXXXXX
79E8H
Program Address Detection Register 2
PADR2
R/W
XXXXXXXX
79E9H to
79EFH
XXXXXXXX
Reserved
79F0H
Program Address Detection Register 3
PADR3
R/W
XXXXXXXX
79F1H
Program Address Detection Register 3
PADR3
R/W
XXXXXXXX
79F2H
Program Address Detection Register 3
PADR3
R/W
XXXXXXXX
79F3H
Program Address Detection Register 4
PADR4
R/W
XXXXXXXX
Address Match
Detection 1
79F4H
Program Address Detection Register 4
PADR4
R/W
79F5H
Program Address Detection Register 4
PADR4
R/W
XXXXXXXX
79F6H
Program Address Detection Register 5
PADR5
R/W
XXXXXXXX
79F7H
Program Address Detection Register 5
PADR5
R/W
XXXXXXXX
79F8H
Program Address Detection Register 5
PADR5
R/W
XXXXXXXX
79F9H to
7BFFH
Reserved
7C00H to
7CFFH
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
7D00H to
7DFFH
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
7E00H to
7FFFH
Reserved
XXXXXXXX
Notes : • Initial value of “X” represents unknown value.
• Addresses in the range 0000H to 00BFH, which are not listed in the table, are reserved for the primary
functions of the MCU. A read access to these reserved addresses results reading “X” and any write
access should not be performed.
30
MB90350 Series
■ CAN CONTROLLERS
The CAN controller has the following features :
• Conforms to CAN Specification Version 2.0 Part A and B
• Supports transmission/reception in standard frame and extended frame formats
• Supports transmitting of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
• 29-bit ID and 8-byte data
• Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask
• Two acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 Kbits/s to 2 Mbits/s (when input clock is at 16 MHz)
List of Control Registers (1)
Address
CAN1
000080H
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
Register
Abbreviation
Access
Initial Value
Message buffer enable register
BVALR
R/W
00000000
00000000
Transmit request register
TREQR
R/W
00000000
00000000
Transmit cancel register
TCANR
W
00000000
00000000
Transmission complete register
TCR
R/W
00000000
00000000
Receive complete register
RCR
R/W
00000000
00000000
Remote request receiving register
RRTRR
R/W
00000000
00000000
Receive overrun register
ROVRR
R/W
00000000
00000000
Reception interrupt
enable register
RIER
R/W
00000000
00000000
31
MB90350 Series
List of Control Registers (2)
Address
CAN1
007D00H
007D01H
007D02H
007D03H
007D04H
007D05H
007D06H
007D07H
007D08H
007D09H
007D0AH
007D0BH
007D0CH
007D0DH
007D0EH
007D0FH
Register
Abbreviation
Access
Initial Value
Control status register
CSR
R/W, W
R/W, R
0XXXX0X1
00XXX000
Last event indicator register
LEIR
R/W
000X0000
XXXXXXXX
Receive/transmit error counter
RTEC
R
00000000
00000000
Bit timing register
BTR
R/W
11111111
X1111111
IDE register
IDER
R/W
XXXXXXXX
XXXXXXXX
Transmit RTR register
TRTRR
R/W
00000000
00000000
Remote frame receive waiting
register
RFWTR
R/W
XXXXXXXX
XXXXXXXX
Transmit interrupt
enable register
TIER
R/W
00000000
00000000
007D10H
007D11H
007D12H
Acceptance mask
select register
XXXXXXXX
XXXXXXXX
AMSR
R/W
XXXXXXXX
XXXXXXXX
007D13H
007D14H
007D15H
007D16H
XXXXXXXX
XXXXXXXX
Acceptance mask register 0
AMR0
R/W
XXXXXXXX
XXXXXXXX
007D17H
007D18H
007D19H
007D1AH
007D1BH
32
XXXXXXXX
XXXXXXXX
Acceptance mask register 1
AMR1
R/W
XXXXXXXX
XXXXXXXX
MB90350 Series
List of Message Buffers (ID Registers) (1)
Address
CAN1
007C00H
to
007C1FH
Register
Abbreviation
Access
Initial Value
General-purpose RAM
R/W
XXXXXXXX
to
XXXXXXXX
007C20H
007C21H
007C22H
XXXXXXXX
XXXXXXXX
ID register 0
IDR0
R/W
XXXXXXXX
XXXXXXXX
007C23H
007C24H
007C25H
007C26H
XXXXXXXX
XXXXXXXX
ID register 1
IDR1
R/W
XXXXXXXX
XXXXXXXX
007C27H
007C28H
007C29H
007C2AH
XXXXXXXX
XXXXXXXX
ID register 2
IDR2
R/W
XXXXXXXX
XXXXXXXX
007C2BH
007C2CH
007C2DH
007C2EH
XXXXXXXX
XXXXXXXX
ID register 3
IDR3
R/W
XXXXXXXX
XXXXXXXX
007C2FH
007C30H
007C31H
007C32H
XXXXXXXX
XXXXXXXX
ID register 4
IDR4
R/W
XXXXXXXX
XXXXXXXX
007C33H
007C34H
007C35H
007C36H
XXXXXXXX
XXXXXXXX
ID register 5
IDR5
R/W
XXXXXXXX
XXXXXXXX
007C37H
007C38H
007C39H
007C3AH
XXXXXXXX
XXXXXXXX
ID register 6
IDR6
R/W
XXXXXXXX
XXXXXXXX
007C3BH
007C3CH
007C3DH
007C3EH
007C3FH
XXXXXXXX
XXXXXXXX
ID register 7
IDR7
R/W
XXXXXXXX
XXXXXXXX
33
MB90350 Series
List of Message Buffers (ID Registers) (2)
Address
CAN1
Register
Abbreviation
Access
007C40H
007C41H
007C42H
XXXXXXXX
XXXXXXXX
ID register 8
IDR8
R/W
XXXXXXXX
XXXXXXXX
007C43H
007C44H
007C45H
007C46H
XXXXXXXX
XXXXXXXX
ID register 9
IDR9
R/W
XXXXXXXX
XXXXXXXX
007C47H
007C48H
007C49H
007C4AH
XXXXXXXX
XXXXXXXX
ID register 10
IDR10
R/W
XXXXXXXX
XXXXXXXX
007C4BH
007C4CH
007C4DH
007C4EH
XXXXXXXX
XXXXXXXX
ID register 11
IDR11
R/W
XXXXXXXX
XXXXXXXX
007C4FH
007C50H
007C51H
007C52H
XXXXXXXX
XXXXXXXX
ID register 12
IDR12
R/W
XXXXXXXX
XXXXXXXX
007C53H
007C54H
007C55H
007C56H
XXXXXXXX
XXXXXXXX
ID register 13
IDR13
R/W
XXXXXXXX
XXXXXXXX
007C57H
007C58H
007C59H
007C5AH
XXXXXXXX
XXXXXXXX
ID register 14
IDR14
R/W
XXXXXXXX
XXXXXXXX
007C5BH
007C5CH
007C5DH
007C5EH
007C5FH
34
Initial Value
XXXXXXXX
XXXXXXXX
ID register 15
IDR15
R/W
XXXXXXXX
XXXXXXXX
MB90350 Series
List of Message Buffers (DLC Registers and Data Registers) (1)
Address
CAN1
007C60H
007C61H
007C62H
007C63H
007C64H
007C65H
007C66H
007C67H
007C68H
007C69H
007C6AH
007C6BH
007C6CH
007C6DH
007C6EH
007C6FH
007C70H
007C71H
007C72H
007C73H
007C74H
007C75H
007C76H
007C77H
007C78H
007C79H
007C7AH
007C7BH
007C7CH
007C7DH
007C7EH
007C7FH
Register
Abbreviation
Access
Initial Value
DLC register 0
DLCR0
R/W
XXXXXXXX
DLC register 1
DLCR1
R/W
XXXXXXXX
DLC register 2
DLCR2
R/W
XXXXXXXX
DLC register 3
DLCR3
R/W
XXXXXXXX
DLC register 4
DLCR4
R/W
XXXXXXXX
DLC register 5
DLCR5
R/W
XXXXXXXX
DLC register 6
DLCR6
R/W
XXXXXXXX
DLC register 7
DLCR7
R/W
XXXXXXXX
DLC register 8
DLCR8
R/W
XXXXXXXX
DLC register 9
DLCR9
R/W
XXXXXXXX
DLC register 10
DLCR10
R/W
XXXXXXXX
DLC register 11
DLCR11
R/W
XXXXXXXX
DLC register 12
DLCR12
R/W
XXXXXXXX
DLC register 13
DLCR13
R/W
XXXXXXXX
DLC register 14
DLCR14
R/W
XXXXXXXX
DLC register 15
DLCR15
R/W
XXXXXXXX
35
MB90350 Series
List of Message Buffers (DLC Registers and Data Registers) (2)
Address
Register
Abbreviation
Access
Initial Value
007C80H
to
007C87H
Data register 0
(8 bytes)
DTR0
R/W
XXXXXXXX
to
XXXXXXXX
007C88H
to
007C8FH
Data register 1
(8 bytes)
DTR1
R/W
XXXXXXXX
to
XXXXXXXX
007C90H
to
007C97H
Data register 2
(8 bytes)
DTR2
R/W
XXXXXXXX
to
XXXXXXXX
007C98H
to
007C9FH
Data register 3
(8 bytes)
DTR3
R/W
XXXXXXXX
to
XXXXXXXX
007CA0H
to
007CA7H
Data register 4
(8 bytes)
DTR4
R/W
XXXXXXXX
to
XXXXXXXX
007CA8H
to
007CAFH
Data register 5
(8 bytes)
DTR5
R/W
XXXXXXXX
to
XXXXXXXX
007CB0H
to
007CB7H
Data register 6
(8 bytes)
DTR6
R/W
XXXXXXXX
to
XXXXXXXX
007CB8H
to
007CBFH
Data register 7
(8 bytes)
DTR7
R/W
XXXXXXXX
to
XXXXXXXX
007CC0H
to
007CC7H
Data register 8
(8 bytes)
DTR8
R/W
XXXXXXXX
to
XXXXXXXX
007CC8H
to
007CCFH
Data register 9
(8 bytes)
DTR9
R/W
XXXXXXXX
to
XXXXXXXX
007CD0H
to
007CD7H
Data register 10
(8 bytes)
DTR10
R/W
XXXXXXXX
to
XXXXXXXX
007CD8H
to
007CDFH
Data register 11
(8 bytes)
DTR11
R/W
XXXXXXXX
to
XXXXXXXX
007CE0H
to
007CE7H
Data register 12
(8 bytes)
DTR12
R/W
XXXXXXXX
to
XXXXXXXX
007CE8H
to
007CEFH
Data register 13
(8 bytes)
DTR13
R/W
XXXXXXXX
to
XXXXXXXX
CAN1
36
MB90350 Series
List of Message Buffers (DLC Registers and Data Registers) (3)
Address
Register
Abbreviation
Access
Initial Value
007CF0H
to
007CF7H
Data register 14
(8 bytes)
DTR14
R/W
XXXXXXXX
to
XXXXXXXX
007CF8H
to
007CFFH
Data register 15
(8 bytes)
DTR15
R/W
XXXXXXXX
to
XXXXXXXX
CAN1
37
MB90350 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
EI2OS
clear
DMA ch
number
Reset
N
INT9 instruction
Interrupt cause
Interrupt vector
Interrupt control
register
Number
Address
Number
Address
#08
FFFFDCH
N
#09
FFFFD8H
Exception
N
#10
FFFFD4H
Reserved
N
#11
FFFFD0H
Reserved
N
#12
FFFFCCH
ICR00
0000B0H
CAN 1 RX / Input Capture 6
Y1
#13
FFFFC8H
CAN 1 TX/NS / Input Capture 7
Y1
#14
FFFFC4H
ICR01
0000B1H
I2C
N
#15
FFFFC0H
Reserved
N
#16
FFFFBCH
ICR02
0000B2H
16-bit Reload Timer 0
Y1
0
#17
FFFFB8H
16-bit Reload Timer 1
Y1
1
#18
FFFFB4H
ICR03
0000B3H
16-bit Reload Timer 2
Y1
2
#19
FFFFB0H
16-bit Reload Timer 3
Y1
#20
FFFFACH
ICR04
0000B4H
PPG 4/5
N
#21
FFFFA8H
PPG 6/7
N
#22
FFFFA4H
ICR05
0000B5H
PPG 8/9/C/D
N
#23
FFFFA0H
PPG A/B/E/F
N
#24
FFFF9CH
ICR06
0000B6H
Time Base Timer
N
#25
FFFF98H
External Interrupt 8 to 11
Y1
3
#26
FFFF94H
ICR07
0000B7H
Watch Timer
N
#27
FFFF90H
External Interrupt 12 to 15
Y1
4
#28
FFFF8CH
ICR08
0000B8H
A/D Converter
Y1
5
#29
FFFF88H
I/O Timer 0 / I/O Timer 1
N
#30
FFFF84H
ICR09
0000B9H
Input Capture 4/5
Y1
6
#31
FFFF80H
Output Compare 4/5
Y1
7
#32
FFFF7CH
ICR10
0000BAH
Input Capture 0/1
Y1
8
#33
FFFF78H
Output Compare 6/7
Y1
9
#34
FFFF74H
ICR11
0000BBH
Reserved
N
10
#35
FFFF70H
Reserved
N
11
#36
FFFF6CH
ICR12
0000BCH
UART 3 RX
Y2
12
#37
FFFF68H
UART 3 TX
Y1
13
#38
FFFF64H
ICR13
0000BDH
(Continued)
38
MB90350 Series
(Continued)
EI2OS
clear
DMA ch
number
UART 2 RX
Y2
UART 2 TX
Interrupt cause
Interrupt vector
Number
Address
14
#39
FFFF60H
Y1
15
#40
FFFF5CH
Flash Memory
N
#41
FFFF58H
Delayed interrupt
N
#42
FFFF54H
Interrupt control
register
Number
Address
ICR14
0000BEH
ICR15
0000BFH
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Notes : • The peripheral resources sharing the ICR register have the same interrupt level.
• When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service
at a time.
• When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O
Service, the other one cannot use interrupts.
39
MB90350 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
(VSS = AVSS = 0 V)
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 6.0
V
AVCC
VSS − 0.3
VSS + 6.0
V
VCC = AVCC*1
AVRH
VSS − 0.3
VSS + 6.0
V
AVCC ≥ AVRH*1
Input voltage
VI
VSS − 0.3
VSS + 6.0
V
*2
Output voltage
VO
VSS − 0.3
VSS + 6.0
V
*2
ICLAMP
−4.0
+4.0
mA
*4
Σ|ICLAMP|
40
mA
*4
IOL
15
mA
*3
“L” level average output current
IOLAV
4
mA
*3
“L” level maximum overall output current
ΣIOL
100
mA
*3
“L” level average overall output current
ΣIOLAV
50
mA
*3
IOH
−15
mA
*3
“H” level average output current
IOHAV
−4
mA
*3
“H” level maximum overall output current
ΣIOH
−100
mA
*3
“H” level average overall output current
ΣIOHAV
−50
mA
*3
240
+105 °C < TA ≤ +125 °C,
mW Normal operation : maximum
frequency 16 MHz
320
−40 °C < TA ≤ +105 °C,
mW Normal operation : maximum
frequency 24 MHz
−40
+105
°C
−40
+125
°C
−55
+150
°C
Power supply voltage
Maximum Clamp Current
Total Maximum Clamp Current
“L” level maximum output current
“H” level maximum output current
Power consumption
Operating temperature
Storage temperature
PD
TA
TSTG
*5
(Continued)
40
MB90350 Series
(Continued)
*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*2: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun
current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the VI
rating.
*3: Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45, P50 to P56, P60 to P67
*4: • Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45,
P50 to P56 (for evaluation : P50 to P55) , P60 to P67
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0 V to 16 V)
N-ch
R
*5 : If used exceeding TA = +105 °C, be sure to contact Fujitsu for reliability limitations.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
41
MB90350 Series
2. Recommended Conditions
Parameter
Power supply voltage
Symbol
VCC,
AVCC
Smooth capacitor
CS
Operating temperature
TA
(VSS = AVSS = 0 V)
Value
Unit
Remarks
Min
Typ
Max
4.0
5.0
5.5
V
Under normal operation
3.5
5.0
5.5
V
Under normal operation, when not using the
A/D converter and not Flash programming.
4.5
5.0
5.5
V
When External bus is used.
3.0
5.5
V
Maintains RAM data in stop mode
0.1
1.0
µF
Use a ceramic capacitor or capacitor of better AC characteristics. Capacitor at the VCC
should be greater than this capacitor.
−40
+105
°C
−40
+125
°C *
* : If used exceeding TA = +105 °C, be sure to contact Fujitsu for reliability limitations.
C
CS
C Pin Connection Diagram
Operation guaranteed range
Internal clock fCP (MHz)
24
16
− 40
105
125
Operation temperature TA (°C)
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
42
MB90350 Series
3. DC Characteristics
Parameter
Input H
voltage
(At VCC =
5 V ± 10%)
Input L
voltage
(At VCC =
5 V ± 10%)
Output H
voltage
Output H
voltage
Output L
voltage
Output L
voltage
Symbol
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)
Pin
Condition
Min
Value
Typ
Max
Unit
VIHS
0.8 VCC
VCC + 0.3
V
VIHA
0.8 VCC
VCC + 0.3
V
VIHT
2.0
VCC + 0.3
V
VIHS
0.7 VCC
VCC + 0.3
V
VIHI
0.7 VCC
VCC + 0.3
V
VIHR
0.8 VCC
VCC + 0.3
V
VIHM
VCC − 0.3
VCC + 0.3
V
VILS
VSS − 0.3
0.2 VCC
V
VILA
VSS − 0.3
0.5 VCC
V
VILT
VSS − 0.3
0.8
V
VILS
VSS − 0.3
0.3 VCC
V
VILI
VSS − 0.3
0.3 VCC
V
VILR
VSS − 0.3
0.2 VCC
V
VILM
Normal
outputs
I2C current
outputs
Normal
outputs
I2C current
outputs
VSS − 0.3
VCC = 4.5 V,
VCC − 0.5
IOH = −4.0 mA
VCC = 4.5 V,
VCC − 0.5
IOH = −3.0 mA
VCC = 4.5 V,
IOL = 4.0 mA
VCC = 4.5 V,
IOL = 3.0 mA
VSS + 0.3
V
V
V
0.4
V
0.4
V
VOH
VOHI
VOL
VOLI
Remarks
Port inputs if CMOS
hysteresis input levels
are selected (except
P12, P15, P44, P45,
P50)
Port inputs if
AUTOMOTIVE input
levels are selected
Port inputs if TTL input
levels are selected
P12, P15, P50 inputs if
CMOS input levels are
selected
P44, P45 inputs if
CMOS hysteresis input
levels are selected
RST input pin (CMOS
hysteresis)
MD input pin
Port inputs if CMOS
hysteresis input levels
are selected (except
P12, P15, P44, P45,
P50)
Port inputs if
AUTOMOTIVE input
levels are selected
Port inputs if TTL
input levels are selected
P12, P15, P50 inputs if
CMOS input levels are
selected
P44, P45 inputs if
CMOS hysteresis input
levels are selected
RST input pin (CMOS
hysteresis)
MD input pin
(Continued)
43
MB90350 Series
(Continued)
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)
Symbol
Pin
IIL
Pull-up
resistance
RUP
P00 to P07,
P10 to P17,
P20 to P25,
P30 to P37,
RST
Pull-down
resistance
RDOWN
MD2
Parameter
Input leak current
Input capacity
Typ
Max
−1
1
µA
25
50
100
kΩ
25
50
100
Except
kΩ Flash
devices
VCC = 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
50
65
mA MB90F352
VCC = 5.0 V,
Internal frequency : 24 MHz,
At writing FLASH memory.
65
80
mA MB90F352
VCC = 5.0 V,
Internal frequency : 24 MHz,
At erasing FLASH memory.
70
85
mA MB90F352
ICCS
VCC = 5.0 V,
Internal frequency : 24 MHz,
At Sleep mode.
25
35
mA MB90F352
ICTS
VCC = 5.0 V,
Internal frequency : 2 MHz,
At Main Timer mode
0.3
0.8
mA MB90F352
ICTSPLL6
VCC = 5.0 V,
Internal frequency : 24 MHz,
At PLL Timer mode,
external frequency = 4 MHz
4
7
mA MB90F352
ICCL
VCC = 5.0 V,
Internal frequency: 8 kHz,
At sub operation
TA = +25°C
170
360
µA MB90F352
ICCLS
VCC = 5.0 V,
Internal frequency: 8 kHz,
At sub sleep
TA = +25°C
20
50
µA MB90F352
ICCT
VCC = 5.0 V,
Internal frequency: 8 kHz,
At watch mode
TA = +25°C
10
35
µA MB90F352
ICCH
VCC = 5.0 V,
At Stop mode,
TA = +25°C
7
25
µA MB90F352
5
15
pF
CIN
VCC
VCC = 5.5 V, VSS < VI < VCC
Other than C, AVCC, AVSS,
AVRH, VCC, VSS,
* : The power supply current is measured with an external clock.
44
Unit Remarks
Min
ICC
Power supply
current*
Value
Condition
MB90350 Series
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)
Parameter
Symbol
Unit
Remarks
16
MHz
When using an oscillation circuit
32.768
24
100
333
MHz
kHz
ns
When using an external clock*
41.67
333
ns
X0A, X1A
10
30.5
—
µs
PWH, PWL
X0
10
ns
PWHL, PWLL
X0A
5
15.2
µs
Duty ratio is about 30% to 70%.
tCR, tCF
X0
5
ns
When using external clock
Typ
Max
X0, X1
3
X0
X0A, X1A
X0, X1
3
—
62.5
X0
tCYLL
fCL
tCYL
Clock cycle time
Input clock pulse width
Input clock rise and fall
time
Value
Min
fC
Clock frequency
Pin
24
Internal operating
clock frequency
(machine clock)
fCP
1.5
MHz
16
fCPL
8.192
50
kHz
41.67
Internal operating
clock cycle time
(machine clock)
tCP
666
ns
122.1
µs
62.5
tCPL
20
When using an oscillation circuit
When using an external clock
When using main clock at
TA ≤ +105 °C
When using main clock at
TA ≤ +125 °C
When using sub clock
When using main clock at
TA ≤ +105 °C
When using main clock at
TA ≤ +125 °C
When using sub clock
* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as
mentioned in “Relation among external clock frequency and machine clock frequency”.
tCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCF
tCR
tCYLL
0.8 VCC
X0A
0.2 VCC
PWHL
PWLL
tCF
tCR
Clock Timing
45
MB90350 Series
Guaranteed operation range
Power supply voltage
VCC (V)
5.5
Guaranteed A/D Converter
operation range
4.0
3.5
Guaranteed PLL operation range
1.5
24
4
Machine clock fCP (MHz)
Guaranteed operation range of MB90350 series
Guaranteed oscillation frequency range
x6
24
Internal clock
fCP (MHz)
x4
x3
x2
x1
16
x 1/2
(PLL off)
12
8
4.0
1.5
3
4
8
12
16
External clock fC (MHz) *
* : When using the oscillation circuit, the maximum oscillation clock frequency is 16 MHz
External clock frequency and Machine clock frequency
46
24
MB90350 Series
(2) Reset Standby Input
Parameter
Reset input
time
Symbol
tRSTL
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)
Pin
RST
Value
Unit
Remarks
Min
Max
500
ns
Under normal operation
Oscillation time of oscillator*
+ 100 µs
µs
In Stop mode, Sub Clock
mode, Sub Sleep mode
and Watch mode
100
µs
In Main timer mode and
PLL timer mode
* : Oscillation time of oscillator is the time that the amplitude reaches 90%.
In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR / ceramic oscillators,
the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms.
Under normal operation:
tRSTL
RST
0.2 VCC
0.2 VCC
In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:
tRSTL
RST
0.2 VCC
X0
0.2 VCC
90% of
amplitude
Internal operation
clock
100 µs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
47
MB90350 Series
(3) Power On Reset
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)
Parameter
Symbol
Pin
Power on rise time
tR
VCC
tOFF
VCC
Power off time
Value
Condition
Unit
Min
Max
0.05
30
ms
1
ms
Remarks
Due to repetitive operation
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
If you change the power supply voltage too rapidly, a power on reset may occur.
We recommend that you startup smoothly by restraining voltages when changing
the power supply voltage during operation, as shown in the figure below. Perform
while not using the PLL clock. However, if voltage drops are within 1 V/s, you can
operate while using the PLL clock.
VCC
We recommend a rise of
50 mV/ms maximum.
3V
Holds RAM data
VSS
(4) Clock Output Timing
Parameter
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Symbol
Pin
Condition
Cycle time
tCYC
CLK
CLK ↑ → CLK ↓
tCHCL
CLK
Value
Unit
Max
62.5
ns
fCP = 16 MHz
41.76
ns
fCP = 24 MHz
20
ns
fCP = 16 MHz
13
ns
fCP = 24 MHz
tCYC
tCHCL
CLK
2.4 V
2.4 V
0.8 V
48
Remarks
Min
MB90350 Series
(5) Bus Timing (Read)
Parameter
(TA = –40°C to +105°C, VCC = 5.0 V±10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Pin
Condition
Unit Remarks
Min
Max
Symbol
ALE pulse width
tLHLL
ALE
tCP/2 − 10
ns
Valid address ⇒ ALE ↓ time
tAVLL
ALE, A21 to
A16, AD15
to AD00
tCP/2 − 20
ns
ALE ↓ ⇒ Address valid time
tLLAX
ALE, AD15
to AD00
tCP/2 − 15
ns
Valid address ⇒ RD ↓ time
tAVRL
A21 toA16,
AD15 to
AD00, RD
tCP − 15
ns
Valid address ⇒ Valid data
input
tAVDV
A21 to A16,
AD15 to
AD00
5 tCP/2 − 60
ns
RD pulse width
tRLRH
RD
3 tCP/2 − 20
ns
RD ↓ ⇒ Valid data input
tRLDV
RD, AD15 to
AD00
3 tCP/2 − 50
ns
RD ↑ ⇒ Data hold time
tRHDX
RD, AD15 to
AD00
0
ns
RD ↓ ⇒ ALE ↑ time
tRHLH
RD, ALE
tCP/2 − 15
ns
RD ↑ ⇒ Address valid time
tRHAX
RD, A21 to
A16
tCP/2 − 10
ns
Valid address ⇒ CLK ↑ time
tAVCH
A21 to A16,
AD15 to
AD00, CLK
tCP/2 − 16
ns
RD ↓ ⇒ CLK ↑ time
tRLCH
RD, CLK
tCP/2 − 15
ns
ALE ↓ ⇒ RD ↓ time
tLLRL
ALE, RD
tCP/2 − 15
ns
49
MB90350 Series
tRLCH
tAVCH
2.4 V
CLK
2.4 V
tLLAX
tAVLL
ALE
2.4 V
tRHLH
2.4 V
2.4 V
0.8 V
tLHLL
tAVRL
tRLRH
2.4 V
RD
0.8 V
tLLRL
tRHAX
A21 to A16
2.4 V
2.4 V
0.8 V
0.8 V
tRLDV
tRHDX
tAVDV
AD15 to AD00
2.4 V
0.8 V
50
2.4 V
Address
0.8 V
VIH
VIL
VIH
Read data
VIL
MB90350 Series
(6) Bus Timing (Write)
(TA = –40°C to +105°C, VCC = 5.0 V±10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Pin
Condition
Unit Remarks
Min
Max
Parameter
Symbol
Valid address ⇒ WR ↓ time
tAVWL
A21 to A16,
AD15 to AD00,
WR
WR pulse width
tWLWH
Valid data output ⇒ WR ↑
time
tCP−15
ns
WR
3 tCP/2 − 20
ns
tDVWH
AD15 to AD00,
WR
3 tCP/2 − 20
ns
WR ↑ ⇒ Data hold time
tWHDX
AD15 to AD00,
WR
15
ns
WR ↑ ⇒ Address valid time
tWHAX
A21 to A16,
WR
tCP/2 − 10
ns
WR ↑ ⇒ ALE ↑ time
tWHLH
WR, ALE
tCP/2 − 15
ns
WR ↓ ⇒ CLK ↑ time
tWLCH
WR, CLK
tCP/2 − 15
ns
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
2.4 V
WR (WRL, WRH)
0.8 V
tWHAX
A21 to A16
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
AD15 to AD00
2.4 V
0.8 V
2.4 V
2.4 V
Address
0.8 V
tWHDX
Write data
0.8 V
51
MB90350 Series
(7) Ready Input Timing
Symbol
(TA = –40°C to +105°C, VCC = 5.0 V±10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
Rated Value
Test
Pin
Units
Remarks
Condition
Min
Max
RDY setup time
tRYHS
RDY
RDY hold time
tRYHH
RDY
Parameter
45
ns
fCP = 16 MHz
32
ns
fCP = 24 MHz
0
ns
Note : If the RDY setup time is insufficient, use the auto-ready function.
2.4 V
CLK
ALE
RD/WR
RDY
When WAIT is not used.
RDY
When WAIT is used.
52
tRYHS
tRYHH
VIH
VIH
VIL
MB90350 Series
(8) Hold Timing
Parameter
Symbol
Pin floating ⇒ HAK ↓
time
tXHAL
HAK ↑ time ⇒ Pin valid
time
tHAHV
(TA = –40°C to +105°C, VCC = 5.0 V±10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Pin
Condition
Units
Remarks
Min
Max
HAK
30
tCP
ns
tCP
2 tCP
ns
HAK
Note : There is more than 1 cycle from when HRQ reads in until the HAK is changed.
2.4V
HAK
0.8V
tHAHV
tXHAL
Each pin
2.4V
0.8V
High-Z
2.4V
0.8V
53
MB90350 Series
(9) UART 2/3
Parameter
Symbol
(TA = –40°C to +105°C, VCC = 5.0 V±10 %, fCP ≤ 24 MHz, VSS = 0.0 V)
(TA = –40°C to +125°C, VCC = 5.0 V±10 %, fCP ≤ 16 MHz, VSS = 0.0 V)
Value
Pin
Condition
Unit Remarks
Min
Max
8 tCP*
ns
−80
+80
ns
100
ns
SCK2, SCK3,
SIN2, SIN3
60
ns
tSHSL
SCK2, SCK3
4 tCP*
ns
Serial clock “L” pulse width
tSLSH
SCK2, SCK3
4 tCP*
ns
SCK ↓ → SOT delay time
tSLOV
SCK2, SCK3,
SOT2, SOT3
150
ns
Valid SIN → SCK ↑
tIVSH
SCK2, SCK3,
SIN2, SIN3
60
ns
SCK ↑ → Valid SIN hold time
tSHIX
SCK2, SCK3,
SIN2, SIN3
60
ns
Serial clock cycle time
tSCYC
SCK2, SCK3
SCK ↓ → SOT delay time
tSLOV
SCK2, SCK3,
SOT2, SOT3
Valid SIN → SCK ↑
tIVSH
SCK2, SCK3,
SIN0 to SIN4
SCK ↑ → Valid SIN hold time
tSHIX
Serial clock “H” pulse width
Internal clock
operation output
pins are
CL = 80 pF + 1 TTL
External clock
operation output
pins are
CL = 80 pF + 1 TTL
* : Refer to “ (1) Clock timing” rating for tCP (internal operating clock cycle time).
Notes : • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is the machine cycle (Unit : ns)
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
SOT
2.4 V
0.8 V
tIVSH
SIN
VIH
VIH
VIL
VIL
Internal Shift Clock Mode
54
tSHIX
MB90350 Series
tSLSH
tSHSL
VIH
VIH
SCK
VIL
VIL
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
tSHIX
VIH
VIH
VIL
VIL
External Shift Clock Mode
(10) Trigger Input Timing
Parameter
Input pulse width
Symbol
tTRGH
tTRGL
(TA = –40°C to +105°C, VCC = 5.0 V±10 %, fCP ≤ 24 MHz, VSS = 0.0 V)
(TA = –40°C to +125°C, VCC = 5.0 V±10 %, fCP ≤ 16 MHz, VSS = 0.0 V)
Value
Pin
Condition
Unit
Remarks
Min
Max
INT8 to INT15,
INT9R to INT11R,
ADTG
5 tCP
ns
VIH
VIH
INT8 to INT15,
INT9R to INT11R,
ADTG
VIL
VIL
tTRGH
tTRGL
55
MB90350 Series
(11) Timer Related Resource Input Timing
(TA = –40°C to +105°C, VCC = 5.0 V±10 %, fCP ≤ 24 MHz, VSS = 0.0 V)
(TA = –40°C to +125°C, VCC = 5.0 V±10 %, fCP ≤ 16 MHz, VSS = 0.0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
tTIWH
Input pulse width
tTIWL
TIN1, TIN3,
IN0, IN1,
IN4 to IN7
ns
VIH
VIH
TIN1, TIN3,
IN0, IN1,
IN4 to IN7
4 tCP
VIL
VIL
tTIWH
tTIWL
(12) Timer Related Resource Output Timing
(TA = –40°C to +105°C, VCC = 5.0 V±10 %, fCP ≤ 24 MHz, VSS = 0.0 V)
(TA = –40°C to +125°C, VCC = 5.0 V±10 %, fCP ≤ 16 MHz, VSS = 0.0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
CLK ↑ ⇒ TOUT change time
CLK
tTO
TOT1, TOT3,
PPG4, PPG6,
PPG8 to PPGF
2.4 V
2.4 V
TOT1, TOT3,
PPG4, PPG6
PPG8 to PPGF
0.8 V
tTO
56
30
ns
MB90350 Series
(13) I2C Timing
(TA = –40°C to +105°C, VCC = AVCC = 5.0 V±10 %, fCP ≤ 24 MHz, VSS = AVSS = 0.0 V)
(TA = –40°C to +125°C, VCC = AVCC = 5.0 V±10 %, fCP ≤ 16 MHz, VSS = AVSS = 0.0 V)
Standard-mode Fast-mode*4
Unit
Parameter
Symbol
Condition
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
tHDSTA
4.0
0.6
µs
“L” width of the SCL clock
tLOW
4.7
1.3
µs
“H” width of the SCL clock
tHIGH
4.0
0.6
µs
Set-up time for a repeated START condition
SCL↑→SDA↓
tSUSTA
4.7
0.6
µs
Data hold time
SCL↓→SDA↓↑
tHDDAT
0
3.45*2
0
0.9*3
µs
Data set-up time
SDA↓↑→SCL↑
tSUDAT
250
100
ns
Set-up time for STOP condition
SCL↑→SDA↑
tSUSTO
4.0
0.6
µs
tBUS
4.7
1.3
µs
Hold time (repeated) START condition
SDA↓→SCL↓
Bus free time between a STOP and START
condition
R = 1.7 kΩ,
C = 50 pF*1
*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C -bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
SDA
tSUDAT
tLOW
tBUS
tHDSTA
SCL
tHDSTA
tHDDAT
tHIGH
tSUSTA
tSUSTO
57
MB90350 Series
5. A/D Converter
(TA = −40 °C to +105 °C, 3.0 V ≤ AVRH, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
(TA = −40 °C to +125 °C, 3.0 V ≤ AVRH, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)
Parameter
Symbol
Pin
Resolution
Total error
Value
Unit
Min
Typ
Max
10
bit
±3.0
LSB
Nonlinearity error
±2.5
LSB
Differential
nonlinearity error
±1.9
LSB
Zero reading
voltage
VOT
AN0 to AN14
AVSS − 1.5
AVSS + 0.5
AVSS + 2.5
LSB
Full scale reading
voltage
VFST
AN0 to AN14 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB
Compare time
Sampling time
Analog port input
current
IAIN
AN0 to AN14
Analog input
voltage range
VAIN
Reference
voltage range
Power supply
current
Reference
voltage current
Offset between
input channels
1.0
16,500
µs
∞
µs
−0.3
+0.3
µA
AN0 to AN14
AVSS
AVRH
V
AVRH
AVSS + 2.7
AVCC
V
IA
AVCC
3.5
7.5
mA
IAH
AVCC
5
µA
IR
AVRH
600
900
µA
IRH
AVRH
5
µA
AN0 to AN14
4
LSB
2.0
0.5
1.2
Remarks
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
*
*
* : IF A/D convertor is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVRH = 5.0 V) .
Note : The accuracy gets worse as |AVRH − AVSS| becomes smaller.
58
MB90350 Series
6. Definition of A/D Converter Terms
Differential
linearity error
Total error
Zero reading
voltage
Full scale
reading voltage
: Analog variation that is recognized by an A/D converter.
: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )
and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion
characteristics.
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
value.
: Difference between an actual value and an ideal value. A total error includes zero transition
error, full-scale transition error, and linear error.
: Input voltage which results in the minimum conversion value.
: Input voltage which results in the maximum conversion value.
Total error
3FF
3FE
Actual conversion
characteristics
1.5 LSB
3FD
Digital output
Resolution
Non linearity
error
{1 LSB × (N − 1) + 0.5 LSB}
004
VNT
(Actually-measured value)
003
002
Actual conversion
characteristics
Ideal characteristics
001
0.5 LSB
AVSS
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVRH − AVSS
1 LSB = (Ideal value)
[V]
1024
VOT (Ideal value) = AVSS + 0.5 LSB [V]
Total error of digital output “N” =
[LSB]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
(Continued)
59
MB90350 Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FF
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
Digital output
3FD
N+1
VFST (actual
measurement
value)
VNT (actual
measurement value)
004
Actual conversion
characteristics
003
Digital output
3FE
Actual conversion
characteristics
N
V (N + 1) T
(actual measurement
value)
VNT
(actual measurement value)
N−1
002
Ideal characteristics
Actual conversion
characteristics
N−2
001
VOT (actual measurement value)
AVSS
AVRH
AVSS
AVRH
Analog input
Analog input
Non linearity error of digital output N =
Differential linearity error of digital output N =
1 LSB =
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
V (N+1) T − VNT
1 LSB
VFST − VOT
1022
−1 LSB [LSB]
[V]
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
60
[LSB]
MB90350 Series
7. Notes on A/D Converter Section
Use the device with external circuits of the following output impedance for analog inputs :
Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AVCC ≤ 5.5 V,
sampling period ≤ 0.5 µs)
If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors
and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high
as internal capacitor.
If output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient.
• Analog input circuit model
Analog input
R
Comparator
C
4.5 V ≤ AVCC ≤ 5.5 V : R =: 2.52 kΩ, C =: 10.7 pF
4.0 V ≤ AVCC < 4.5 V : R =: 13.6 kΩ, C =: 10.7 pF
Note : Use the values in the figure only as a guideline.
8. Flash Memory Program/Erase Characteristics
Parameter
Conditions
Sector erase time
Chip erase time
TA = +25 °C
VCC = 5.0 V
Word (16 bit width)
programming time
Value
Unit
Remarks
Min
Typ
Max
1
15
s
Excludes programming
prior to erasure
9
s
Excludes programming
prior to erasure
16
3,600
µs
Except for the overhead
time of the system
Program/Erase cycle
10,000
cycle
Flash Data Retention
Time
Average
TA = +85 °C
20
Years
*
* : This value comes from the technology qualification.
(Using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C)
61
MB90350 Series
■ ORDERING INFORMATION
Part number
MB90F352PFM
MB90F352SPFM
MB90352PFM
MB90352SPFM
MB90V340A-101
MB90V340A-102
62
Package
Remarks
64-pin Plastic LQFP
(FPT-64P-M09)
64-pin Plastic LQFP
(FPT-64P-M09)
299-pin Ceramic PGA
(PGA-299C-A01)
For evaluation
MB90350 Series
■ PACKAGE DIMENSIONS
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness including plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
64-pin Plastic LQFP
(FPT-64P-M09)
14.00±0.20(.551±.008)SQ
* 12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.0057±.0022)
33
49
32
0.10(.004)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
(Mounting height)
0.25(.010)
INDEX
0~8˚
64
17
1
0.65(.026)
C
"A"
16
0.32±0.05
(.013±.002)
0.13(.005)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
M
2003 FUJITSU LIMITED F64018S-c-3-5
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
63
MB90350 Series
FUJITSU LIMITED
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FUJITSU LIMITED Printed in Japan