FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13703-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90540/545 Series
MB90F543/F549/V540
■ DESCRIPTION
The MB90540/545 series with FULL-CAN*1 and FLASH ROM is specially designed for automotive and industrial applications. Its main features are two on board CAN Interfaces (one for MB90V545 series), which conform to V2.0
Part A and Part B, supporting very flexible message buffer scheme and so offering more functions than a normal
full CAN approach. The instruction set by F2MC-16LX CPU core inherits an AT architecture of the F2MC*2 family with
additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions.The micro controller has a 32-bit accumulator for processing
long word data.The MB90540/545 series has peripheral resources of 8/10-bit A/D converters, UART(SCI), extended
I/O serial interfaces, 8/16-bit timer, I/O timer (input capture(ICU), output compare (OCU)).
*1:Controller Area Network (CAN) - License of Robert Bosch GmbH.
*2:F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from: divided-by-2 of oscillation or one to four times the oscillation
Minimum instruction execution time: 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock,
VCC of 5.0V)
Subsystem Clock: 32 kHz
(Continued)
■ PACKAGE
100-pin Plastic QFP
(FPT-100P-M06)
MB90540/545 Series
(Continued)
• Instruction set to optimize controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C language) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed: 4-byte Instruction queue
• Enhanced interrupt function: 8 levels, 34 factors
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS)
• Embedded ROM size and types
Flash ROM: 128 Kbytes / 256 Kbytes
Embedded RAM size: 6 Kbytes / 8 Kbytes (evaluation chip)
• Flash ROM
Supports automatic programming, Embedded Algorithm TM*
Write / Erase / Erase-Suspend / Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory
Erase can be performed on each block
Block protection with external programming voltage
• Low-power consumption (stand-by) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Clock mode
Hardware stand-by mode
• Process
0.5 µm CMOS technology
• I/O port
General-purpose I/O ports: 81 ports
• Timer
Watchdog timer: 1 channel
8/16-bit PPG timer: 8/16-bit × 4 channels
16-bit re-load timer: 2 channels
• 16-bit I/O timer
16-bit free-run timer: 1 channel
Input capture: 8 channels
Output compare: 4 channels
• Extended I/O serial interface: 1 channel
• UART 0
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.
(Continued)
2
MB90540/545 Series
(Continued)
• UART 1
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized serial (extended I/O serial) can be used.
• External interrupt circuit (8 channels)
A module for starting an extended intelligent I/O service (EI2OS) and generating an external interrupt which
is triggered by an external input.
• Delayed interrupt generation module
Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
8/10-bit resolution can be selectively used.
Starting by an external trigger input.
Conversion time: 26.3 µs
• FULL-CAN interfaces
MB90540 series: 2 channel
MB90545 series: 1 channel
Conforming to Version 2.0 Part A and Part B
Flexible message buffering (mailbox and FIFO buffering can be mixed)
• External bus interface: Maximum address space 16 Mbytes
*: Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
3
MB90540/545 Series
■ PRODUCT LINEUP
The following table provides a quick outlook of the MB90540/545 Series
Features
MB90F543
MB90F549
Classification
ROM size
ROM size
Flash ROM product
128 Kbytes
Boot Block
256 Kbytes
Boot Block
6K
MB90V540
Evaluation product
None
8K
CPU functions
The number of instructions: 351
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1bit, 8 bits, 16 bits
Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz)
Interrupt processing time: 1.5 µs (at machine clock frequency of 16 MHz, minimum value)
UART 0
Clock synchronized transmission (500 K / 1M / 2 Mbps)
Clock asynchronized transmission (4808 / 5208 / 9615 / 10417 / 19230 / 38460 / 62500
/500000 bps at machine clock frequency of 16 MHz)
Transmission can be performed by bi-directional serial transmission or by master/slave
connection.
UART 1 (SCI)
Clock synchronized transmission (62.5 K/ 12 K/ 250 K/ 500 K/ 1 Mbps)
Clock asynchronized transmission (1202/ 2404/ 4808/ 9615/ 31250 bps)
Transmission can be performed by bi-directional serial
Transmission or by master / slave connection.
Conversion precision: 8/10-bit can be selectively used.
Number of inputs: 8
One-shot conversion mode (converts selected channel once only)
8/10-bit A/D converter Scan conversion mode (converts two or mode successive channels and can program up
to 8 channels)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
8/16-bit PPG timers
Number of channels: 8/16 bit × 4 channels
PPG operation of 8-bit or 16 bit
A pulse wave of given intervals and given duty ratios can be output.
Pulse interval: fsys, fsys/21, fsys/22, fsys/23, fsys/24, 128 µs
(at oscillation of 4 MHz, fsys = machine clock frequency of 16 MHz, fosc = oscillation clock
frequency)
16-bit Reload timer
Number of channels:2
Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)
Supports External Event Count function
16-bit
I/O
timer
16-bit
Number of channels: 4
Output comPin input factor: A match signal of compare register
pares
Input captures
Number of channels: 8
Rewriting a register value upon a pin input (rising, falling, or both edges)
(Continued)
4
MB90540/545 Series
(Continued)
Features
MB90F543
MB90F549
MB90V540
CAN Interface
Number of channels: 2(MB90540 series), 1(MB90545 series)
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering:
Full bit compare / Full bit mask / Two partial bit masks
Supports up to 1 Mbps
External interrupt circuit
Number of inputs: 8
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
Extended I/O serial
interface
Clock synchronized transmission (31.25 K / 62.5 K /125 K / 500 K / 1 Mbps at machine
clock frequency of 16 MHz)
LSB first / MSB first
Watchdog timer
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Flash Memory
Supports automatic programming, Embedded Algorithm TM and
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Writer from Minato Electronics Inc.
Low-power consumpSleep/ stop/ CPU intermittent operation/ clock timer/ hardware stand-by
tion (stand-by) mode
Process
CMOS
Power supply voltage
for operation
Package
5 V ± 10 %
QFP-100
PGA-256
*: Varies with conditions such as operating frequency. (See section “ ■ Electrical Characteristics”.)
5
MB90540/545 Series
■ PIN ASSIGNMENT
P00/AD00
Vcc
X1
X0
Vss
84
83
82
81
P01/AD01
85
P06/AD06
91
P02/AD02
P07/AD07
92
86
P10/AD08
93
P03/AD03
P11/AD09
94
87
P12/AD10
95
88
P13/AD11
96
P05/AD05
P14/AD12
97
P04/AD04
P15/AD13
98
89
P16/AD14
99
90
P17/AD15
100
(Top view)
P20/A16
1
80
X0A
P21/A17
2
79
X1A
P22/A18
3
78
PA0
P23/A19
4
77
P24/A20
5
76
RST
P97/RX1
P25/A21
P26/A22
6
75
7
74
P96/TX1
P95/RX0
P76/OUT2/IN6
Vcc
23
58
P75/IN5
P45/SOT1
24
57
P74/IN4
P46/SOT2
25
56
P73/IN3
P47/SCK2
26
55
P72/IN2
C
27
54
P71/IN1
P50/SIN2
28
53
P70/IN0
P51/INT4
29
52
HST
P52/INT5
30
51
MD2
50
59
MD1
22
49
P77/OUT3/IN7
P44/SCK1
48
60
MD0
21
P57/TOT0
P80/PPG0
P43/SIN1
47
61
P56/TIN0
20
46
P81/PPG1
P42/SIN0
P67/AN7
62
45
19
P66/AN6
P82/PPG2
P41/SCK0
44
63
43
18
P65/AN5
P83/PPG3
P40/SOT0
P64/AN4
17
64
42
P84/OUT0
P37/CLK
Vss
65
41
16
P63/AN3
P85/OUT1
P36/RDY
40
66
P62/AN2
P86/TIN1
15
39
67
P61/AN1
14
38
P87/TOT1
P34/HRQ
P35/HAK
P60/AN0
68
37
13
AVss
P90/INT0
P33/WRH
36
69
AVRL
12
35
P91/INT1
P32/WRL/WR
AVRH
11
70
34
P92/INT2
Vss
AVcc
71
33
10
P55/ADTG
P93/INT3
P31/RD
32
P94/TX0
72
31
73
9
P54/INT7
8
P53/INT6
P27/A23
P30/ALE
(FPT-100P-M06)
(Continued)
6
MB90540/545 Series
■ PIN DESCRIPTION
No.
Pin name
Circuit type
82
83
X0
X1
A
(Oscillation)
High speed oscillator input pins
80
79
X0A
X1A
A
(Oscillation)
Low speed oscillator input pins
77
RST
B
External reset request input
52
HST
C
Hardware standby input
P00 to P07
85 to 92
I
Function
General I/O port with programmable pullup. This function is enabled
in the single-chip mode.
AD00 to AD07
I/O pins for 8 lower bits of the external address/data bus. This function is enabled when the external bus is enabled.
P10 to P17
General I/O port with programmable pullup. This function is enabled
in the single-chip mode.
93 to 100
I
AD08 to AD15
I/O pins for 8 higher bits of the external address/data bus. This function is enabled when the external bus is enabled.
P20 to P27
General I/O port with programmable pullup. This function is enabled
in the single-chip mode.
1 to 8
H
A16 to A23
8-bit I/O pins for A16 to A23 at the external address bus. This function is enabled when the external bus is enabled.
P30
General I/O port with programmable pullup. This function is enabled
in the single-chip mode.
9
I
ALE
Address latch enable output pin. This function is enabled when the
external bus is enabled.
P31
General I/O port with programmable pullup. This function is enabled
in the single-chip mode.
10
I
RD
Read strobe output pin for the data bus. This function is enabled
when the external bus is enabled.
P32
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when the WR/WRL pin output is disabled.
WRL
12
I
WR
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or external bus 8-bit mode or when WRH pin
output is disabled.
P33
13
I
WRH
Write strobe output pin for the data bus. This function is enabled
when both the external bus and the WR/WRL pin output are enabled. WRL is write-strobe output pin for the lower 8 bits of the data
bus in 16-bit access. WR is write-strobe output pin for the 8 bits of
the data bus in 8-bit access.
Write strobe output pin for the 8 higher bits of the data bus. This
function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH output pin is
enabled.
(Continued)
7
MB90540/545 Series
No.
Pin name
Circuit type
P34
14
I
Hold request input pin. This function is enabled when both the external bus and the hold functions are enabled.
P35
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when the hold function is disabled.
I
HAK
Hold acknowledge output pin. This function is enabled when both
the external bus and the hold functions are enabled.
P36
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when the external ready function is disabled.
16
I
RDY
Ready input pin. This function is enabled when both the external bus
and the external ready functions are enabled.
P37
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when the clock output is disabled.
17
H
CLK
CLK output pin. This function is enabled when both the external bus
and CLK outputs are enabled.
P40
General I/O port. This function is enabled when UART0 disables the
serial data output.
18
G
SOT0
Serial data output pin for UART0. This function is enabled when
UART0 enables the serial data output.
P41
General I/O port. This function is enabled when UART0 disables
clock output.
19
G
SCK0
P42
SIN0
SIN1
G
G
G
SCK1
P45
24
G
SOT1
Serial data input pin for UART0. While UART0 is operating for input,
the input of the pin is used as required. Except when the function is
intentionally used, output from the other functions must be stopped.
General I/O port. This function is always enabled.
P44
22
Clock I/O pin for UART0. This function is enabled when UART0 enables the clock output.
General I/O port. This function is always enabled.
P43
21
General I/O port with programmable pullup. This function is enabled
in the single-chip mode or when the hold function is disabled.
HRQ
15
20
Function
Serial data input pin for UART1. While UART1 is operating for input,
the input of the pin is used as required. Except when the function is
intentionally used, output from the other functions must be stopped.
General I/O port. This function is enabled when UART1 disables the
clock output.
Clock pulse input/output pin for UART1. This function is enabled
when UART1 enables the clock output.
General I/O port. This function is enabled when UART1 disables the
serial data output.
Serial data output pin for UART1. This function is enabled when
UART1 enables the serial data output.
(Continued)
8
MB90540/545 Series
No.
Pin name
Circuit type
P46
25
G
SOT2
P47
26
G
SCK2
P50
28
SIN2
INT4 to INT7
D
ADTG
D
D
E
Clock pulse input/output pin for the Serial IO. This function is enabled when the Serial IO enables the clock output.
Serial data input pin for the Serial IO. While the Serial IO is operating
for input, the input of the pin is used as required. Except when the
function is intentionally used, output from the other functions must
be stopped.
External interrupt request input pins for INT4 to INT7. While external
interrupt is allowed, the input of the pin is used as required. Except
when the function is intentionally used, output from the other functions must be stopped.
Trigger input pin for the A/D converter. While the A/D converter is
operating for input, the input of the pin is used as required. Except
when the function is intentionally used, output from the other functions must be stopped.
General I/O port. This function is enabled when the analog input enable register specifies a port.
AN0 to AN3
Analog input pins for the 8/10-bit A/D converter. This function is enabled when the analog input enable register specifies AD.
P64 to P67
General I/O port. The function is enabled when the analog input enable register specifies a port.
43 to 46
E
AN4 to AN7
P56
47
General I/O port. This function is enabled when the Serial IO disables the clock output.
General I/O port. This function is always enabled.
P60 to P63
38 to 41
Serial data output pin for the Serial IO. This function is enabled when
the Serial IO enables the serial data output.
General I/O port. This function is always enabled.
P55
33
General I/O port. This function is enabled when the Serial IO disables the serial data output.
General I/O port. This function is always enabled.
P51 to P54
29 to 32
Function
TIN0
General I/O port. This function is always enabled.
D
P57
48
D
TOT0
Analog input pins for the 8/10-bit A/D converter. This function is enabled when the analog input enable register specifies AD.
Event input pin for the 16-bit reload timers 0. While the 16-bit reload
timer is operating for input, the input of the pin is used as required.
Except when the function is intentionally used, output from the other
functions must be stopped.
General I/O port. This function is enabled when the 16-bit reload
timers 0 disables the output.
Output pin for the 16-bit reload timers 0. This function is enabled
when the 16-bit reload timers 0 enables the output.
(Continued)
9
MB90540/545 Series
No.
Pin name
Circuit type
P70 to P75
53 to 58
IN0 to IN5
General I/O ports. This function is always enabled.
D
General I/O ports. This function is enabled when the OCU disables
the waveform output.
OUT2 to OUT3
Waveform output pins for output compares OCU2 and OCU3. This
function is enabled when the OCU enables the waveform output.
D
IN6 to IN7
Data sample input pin for input captures ICU6 and ICU7. While the
ICU is for input, the input of the pin is used as required. Except when
the function is intentionally used, output from the other functions
must be stopped.
P80 to P83
General I/O ports. This function is enabled when 8/16-bit PPG disables the waveform output.
61 to 64
D
PPG0 to PPG3
Output pins for 8/16-bit PPGs. This function is enabled when 8/16bit PPG enables the waveform output.
P84 to P85
General I/O ports. This function is enabled when the OCU disables
the waveform output.
65 to 66
D
OUT0 to OUT1
P86
TIN1
68
D
D
TOT1
P90 to P93
INT0 to INT3
74
Event input pin for the 16-bit reload timers 1. While the 16-bit reload
timer is operating as an input, the input of the pin is used as required. Except when the function is intentionally used, output from
the other functions must be stopped.
General I/O port. This function is enabled when the 16-bit reload
timers 0 disables the output.
Output pin for the 16-bit reload timers 1 This function is enabled
when the 16-bit reload timers 1 enables the output.
General I/O port. This function is always enabled.
D
P94
73
Waveform output pins for output compares OCU0 and OCU1. This
function is enabled when the OCU enables the waveform output.
General I/O port. This function is always enabled.
P87
69 to 72
Data sample input pins for input captures ICU0 to ICU5. While the
ICU is for input, the input of the pin is used as required. Except when
the function is intentionally used, output from the other functions
must be stopped.
P76 to P77
59 to 60
67
Function
D
External interrupt request input pins for INT0 to INT3. While external
interrupt is allowed, the input of the pin is used as required. Except
when the function is intentionally used, output from the other functions must be stopped.
General I/O port. This function is enabled when CAN0 disables the
output.
TX0
TX Output pin for CAN0. This function is enabled when CAN0 enables the output.
P95
General I/O port. This function is always enabled.
RX0
D
RX input pin for CAN0 Interface. When the CAN function is used,
output from the other functions must be stopped.
(Continued)
10
MB90540/545 Series
(Continued)
No.
Pin name
Circuit type
P96
75
76
D
Function
General I/O port. This function is enabled when CAN1 disables the
output.
TX1
TX Output pin for CAN1. This function is enabled when CAN1 enables the output (only MB90540 series).
P97
General I/O port. This function is always enabled.
RX1
D
RX input pin for CAN1 Interface. When the CAN function is used,
output from the other functions must be stopped (only MB90540 series).
D
General I/O port. This function is always enabled.
78
PA0
34
AVCC
Power supply for the A/D Converter. This power supply must be
Power supply turned on or off while a voltage higher than or equal to AVcc is applied to Vcc.
37
AVSS
Power supply Power supply for the A/D Converter.
35
AVRH
External reference voltage input for the A/D Converter. This power
Power supply supply must be turned on or off while a voltage higher than or equal
to AVRH is applied to AVcc.
36
AVRL
Power supply External reference voltage input for the A/D Converter.
49
50
MD0
MD1
C
Input pins for specifying the operating mode. The pins must be directly connected to Vcc or Vss.
51
MD2
F
Input pin for specifying the operating mode. The pin must be directly
connected to Vcc or Vss.
27
C
23, 84
VCC
Power supply Input pin for power supply (5.0 V) .
11, 42, 81
VSS
Power supply Input pin for power supply (0.0 V) .
This is the power supply stabilization capacitor pin. It should be connected externally to an 0.1 µF ceramic capacitor.
11
MB90540/545 Series
■ I/O CIRCUIT TYPE
Circuit type
Diagram
Remarks
• Oscillation feedback resistor:
1 MΩ approx.
X1
X0
A
Standby control signal
• Hysteresis input with pull-up
Resistor: 50 kΩ approx.
B
R
R
HYS
• Hysteresis input
C
R
HYS
• CMOS level output
• Hysteresis input
VCC
P-ch
N-ch
D
R
12
HYS
MB90540/545 Series
Circuit type
Diagram
Remarks
• CMOS level output
• Hysteresis input
• Analog input
VCC
P-ch
N-ch
E
Analog input
HYS
R
R
F
HYS
• Hysteresis input
• Pull-down Resistor: 50 kΩ approx.
(except FLASH devices)
R
• CMOS level output
• Hysteresis input
• TTL input (FLASH devices only)
VCC
P-ch
N-ch
G
R
HYS
R
TTL
T
13
MB90540/545 Series
Circuit type
Diagram
Remarks
VCC
CNTL
VCC
P-ch
P-ch
H
N-ch
HYS
R
VCC
CNTL
VCC
P-ch
P-ch
N-ch
I
R
HYS
R
TTL
T
14
• CMOS level output
• Hysteresis input
• Programmable pullup resistor:
50 kΩ approx.
•
•
•
•
CMOS level output
Hysteresis input
TTL level input (FLASH devices only)
Programmable pullup resistor:
50 kΩ approx.
MB90540/545 Series
■ HANDLING DEVICES
(1) Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than Vcc or lower than Vss is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between Vcc and Vss.
• The AVcc power supply is applied before the Vcc voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, care must also be taken in not allowing the analog power-supply voltage (AVcc, AVRH,
DVcc) to exceed the digital power-supply voltage.
(2) Handling unused input pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefor they must be pulled up or pulled down through resistors. In this case those resistors should be
more than 2 kΩ.
Unused bi-directional pins should be set to the output state and can be left open, or the input state with the
above described connection.
(3) Using external clock
To use external clock, drive X0 pin only and leave X1 pin unconnected.
Below is a diagram of how to use external clock.
MB90540/545 Series
X0
Open
X1
(4) Not using subclock mode
Oscillations must be connected to the X0A and X1A, even when a subclock is not used.
(5) Power supply pins (Vcc/Vss)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to
avoid abnormal operations including latch-up. However you must connect the pins to an external power and a
ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused
by the rise in the ground level, and to conform to the total current rating.
Make sure to connect VCC and VSS pins via the lowest impedance to power lines.
It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pins near the device.
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90540/545
Vcc
Series
Vss
Vss
Vcc
15
MB90540/545 Series
(6) Pull-up/down resistors
The MB90540/545 Series does not support internal pull-up/down resistors (except Port0 - Port3:pull-up resistors). Use external components where needed.
(7) Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via the shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines,
and make sure, to the utmost effort, that lines of oscillation circuits do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a grand
area for stabilizing the operation.
(8) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after
turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
(9) Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.
(10) N.C. Pin
The N.C. (internally connected) pin must be opened for use.
(11) Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 µs or more (0.2 V to 2.7 V).
(12) Indeterminate outputs from ports 0 and 1
The outputs from 0 and 1 become indeterminate during a power-on reset after the power is turned on.
Pay attention to the port output timing shown as follows.
• Timming chart of indeterminate outputs from ports o and 1
Oscillation setting time∗2
Step-down circuit
setting time ∗1
Vcc(power-supply pin)
PONR(power-on reset) signal
RST(external asynchronous reset) signal
RST(internal reset) signal
Oscillation clock signal
KA(internal operation clock A) signal
KB(internal operation clock B) signal
PORT(port output)signal
Indereterminate period
* : 1:Step-down circuit setting time : 217/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms)
* : 2:Oscillation setting time: 218/oscillation clock frequency (oscillation cllock frequency of 16 MHz: 16.38 ms)
16
MB90540/545 Series
(13) Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers,
please turn on the power again.
(14) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions
In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”), the value of the corresponding bank register (DTB, ADB, USB, SSB) is set in “00h”.
If the values of the corresponding bank registers (DTB,ADB,USB,SSB) are set to other than “00h”, the remainder
by the execution result of the instruction is not stored in the register of the instruction operand.
(15) Using REALOS
Extended intelligent I/O service (EI2OS) can not be used, while REALOS is used.
17
MB90540/545 Series
■ BLOCK DIAGRAM
X0,X1
X0A,X1A
RST
Clock
Controller
F2MC 16LX
CPU
HST
16-bit I/O
Timer
RAM 6 KB
16-bit Input
Capture
8 ch.
ROM 128 KB
/256 KB
IN0 to IN5
IN6/OUT2,
IN7/OUT3
16-bit
Output
Compare
4 ch.
OUT0, OUT1
8/16-bit
PPG
4 ch.
PPG[3:0]
Prescaler
SOT0
SCK0
SIN0
UART0
CAN
Controller
Prescaler
SOT1
SCK1
SIN1
UART1
(SCI)
RX[1:0]
TX[1:0]
16-bit Reload
TIN0, TIN1
Timer 2 ch.
TOT0, TOT1
SOT2
SCK2
SIN2
AVCC
AVSS
AN0 to AN7
AVRH
AVRL
ADTG
SIO 1ch
FMC-16 Bus
Prescaler
AD00 to AD15
A16 to A23
ALE
RD
External
Bus
Interface
WRH
HRQ
10-bit ADC
8 ch.
HAK
RDY
CLK
External
Interrupt
8 ch.
18
WRL
INT0 to INT7
MB90540/545 Series
■ MEMORY SPACE
The memory space of the MB90540/545 Series is shown below.
MB90V540
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
ROM
(FF bank)
ROM
(FE bank)
MB90F543
FFFFFFH
FF0000H
FEFFFFH
FE0000H
ROM
(FF bank)
ROM
(FE bank)
ROM
(FD bank)
External
ROM
(FC bank)
MB90F549
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
External
00FFFFH
004000H
003FFFH
ROM
(Image of FF
bank)
00FFFFH
004000H
003FFFH
0020FFH
001FF5H
001FF0H
ROM
(Image of FF
bank)
ROM correction
00FFFFH
004000H
003FFFH
Peripheral
003900H
External
ROM
(FE bank)
ROM
(FD bank)
ROM
(FC bank)
External
Peripheral
003900H
ROM
(FF bank)
002000H
ROM
(Image of FF
bank)
Peripheral
003900H
External
0018FFH
002000H
External
0018FFH
RAM 6K
RAM 6K
RAM 8K
000100H
000100H
External
0000BFH
000000H
Peripheral
000100H
External
0000BFH
000000H
Peripheral
External
0000BFH
000000H
Peripheral
The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler
effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without using the “far” specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.The ROM area in bank FF
exceeds 48 Kbytes, and its entire image cannot be shown in bank 00.The image between FF4000H and FFFFFFH
is visible in bank 00, while the image between FF0000H and FF3FFFH is visible only in bank FF.
19
MB90540/545 Series
■ I/O MAP
Address
Register
Peripheral
Initial value
00H
Port 0 data register
PDR0
R/W
Port 0
XXXXXXXXB
01H
Port 1 data register
PDR1
R/W
Port 1
XXXXXXXXB
02H
Port 2 data register
PDR2
R/W
Port 2
XXXXXXXXB
03H
Port 3 data register
PDR3
R/W
Port 3
XXXXXXXXB
04H
Port 4 data register
PDR4
R/W
Port 4
XXXXXXXXB
05H
Port 5 data register
PDR5
R/W
Port 5
XXXXXXXXB
06H
Port 6 data register
PDR6
R/W
Port 6
XXXXXXXXB
07H
Port 7 data register
PDR7
R/W
Port 7
XXXXXXXXB
08H
Port 8 data register
PDR8
R/W
Port 8
XXXXXXXXB
09H
Port 9 data register
PDR9
R/W
Port 9
XXXXXXXXB
0AH
Port A data register
PDRA
R/W
Port A
_ _ _ _ _ _ _XB
0BH to 0FH
Abbreviation Access
Reserved
10H
Port 0 direction register
DDR0
R/W
Port 0
0 0 0 0 0 0 0 0B
11H
Port 1 direction register
DDR1
R/W
Port 1
0 0 0 0 0 0 0 0B
12H
Port 2 direction register
DDR2
R/W
Port 2
0 0 0 0 0 0 0 0B
13H
Port 3 direction register
DDR3
R/W
Port 3
0 0 0 0 0 0 0 0B
14H
Port 4 direction register
DDR4
R/W
Port 4
0 0 0 0 0 0 0 0B
15H
Port 5 direction register
DDR5
R/W
Port 5
0 0 0 0 0 0 0 0B
16H
Port 6 direction register
DDR6
R/W
Port 6
0 0 0 0 0 0 0 0B
17H
Port 7 direction register
DDR7
R/W
Port 7
0 0 0 0 0 0 0 0B
18H
Port 8 direction register
DDR8
R/W
Port 8
0 0 0 0 0 0 0 0B
19H
Port 9 direction register
DDR9
R/W
Port 9
0 0 0 0 0 0 0 0B
1AH
Port A direction register
DDRA
R/W
Port A
_ _ _ _ _ _ _0B
1BH
Analog Input Enable
ADER
R/W
Port 6, A/D
1 1 1 1 1 1 1 1B
1CH
Port 0 Pullup control register
PUCR0
R/W
Port 0
0 0 0 0 0 0 0 0B
1DH
Port 1 Pullup control register
PUCR1
R/W
Port 1
0 0 0 0 0 0 0 0B
1EH
Port 2 Pullup control register
PUCR2
R/W
Port 2
0 0 0 0 0 0 0 0B
1FH
Port 3 Pullup control register
PUCR3
R/W
Port 3
0 0 0 0 0 0 0 0B
20H
Serial Mode Control Register 0
UMC0
R/W
21H
Serial Status Register 0
USR0
R/W
22H
Serial Input/Output data register 0
UIDR0/
UODR0
R/W
23H
Rate and data register 0
URD0
R/W
0 0 0 0 0 1 0 0B
0 0 0 1 0 0 0 0B
UART0
XXXXXXXXB
0 0 0 0 0 0 0XB
(Continued)
20
MB90540/545 Series
Address
Register
24H
Serial mode register 1
SMR1
R/W
0 0 0 0 0 0 0 0B
25H
Serial control register 1
SCR1
R/W
0 0 0 0 0 1 0 0B
26H
Serial input/output data register 1
SIDR1/
SODR1
R/W
27H
Serial status register 1
SSR1
R/W
0 0 0 0 1_0 0B
28H
UART1 prescaler control register
U1CDCR
R/W
0_ _ _1 1 1 1B
29H
Edge selector
SES1
R/W
_ _ _ _ _ _ _0B
2AH
Abbreviation Access
Peripheral
UART1
Initial value
XXXXXXXXB
Reserved
2BH
Serial IO prescaler
SCDCR
R/W
0_ _ _1 1 1 1B
2CH
Serial mode control register
SMCS
R/W
_ _ _ _0 0 0 0B
2DH
Serial mode control register
SMCS
R/W
2EH
Serial data register
SDR
R/W
XXXXXXXXB
2FH
Edge selector
SES2
R/W
_ _ _ _ _ _ _0B
30H
External interrupt enable register
ENIR
R/W
0 0 0 0 0 0 0 0B
31H
External interrupt request register
EIRR
R/W
32H
External interrupt level register
ELVR
R/W
33H
External interrupt level register
ELVR
R/W
0 0 0 0 0 0 0 0B
34H
A/D control status register 0
ADCS0
R/W
0 0 0 0 0 0 0 0B
35H
A/D control status register 1
ADCS1
R/W
36H
A/D data register 0
ADCR0
R
37H
A/D data register 1
ADCR1
R/W
38H
PPG0 operation mode control register
PPGC0
R/W
39H
PPG1 operation mode control register
PPGC1
R/W
3AH
PPG0 and PPG1 clock select register
PPG01
R/W
3BH
External Interrupt
A/D Converter
0 0 0 0 0 0 1 0B
XXXXXXXXB
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XXXXXXXXB
0 0 0 0 1 _ XXB
0 _ 0 0 0 _ _ 1B
16-bit Programmable
Pulse
0 _ 0 0 0 0 0 1B
Generator 0/1
0 0 0 0 0 0 _ _B
Reserved
3CH
PPG2 operation mode control register
PPGC2
R/W
3DH
PPG3 operation mode control register
PPGC3
R/W
3EH
PPG2 and PPG3 Clock Select Register
PPG23
R/W
3FH
0 _ 0 0 0 _ _1B
16-bit Programmable
Pulse
0 _ 0 0 0 0 0 1B
Generator 2/3
0 0 0 0 0 0 _ _B
Reserved
40H
PPG4 operation mode control register
PPGC4
R/W
41H
PPG5 operation mode control register
PPGC5
R/W
42H
PPG4 and PPG5 clock select register
PPG45
R/W
43H
44H
Serial IO
0 _ 0 0 0 _ _ 1B
16-bit Programmable
Pulse
0 _ 0 0 0 0 0 1B
Generator 4/5
0 0 0 0 0 0 _ _B
Reserved
PPG6 operation mode control register
PPGC6
R/W
0 _ 0 0 0 _ _ 1B
16-bit Programmable
0 _ 0 0 0 0 0 1B
Pulse
Generator 6/7
45H
PPG7 operation mode control register
PPGC7
R/W
46H
PPG6 and PPG7 output pin control
register
PPG67
R/W
0 0 0 0 0 0 _ _B
(Continued)
21
MB90540/545 Series
Address
Register
47H to 4BH
Abbreviation Access
Peripheral
Initial value
Reserved
4CH
Input capture control status register 0/1
ICS01
R/W
Input Capture 0/1 0 0 0 0 0 0 0 0B
4DH
Input capture control status register 2/3
ICS23
R/W
Input Capture 2/3 0 0 0 0 0 0 0 0B
4EH
Input capture control status register 4/5
ICS45
R/W
Input Capture 4/5 0 0 0 0 0 0 0 0B
4FH
Input capture control status register 6/7
ICS67
R/W
Input Capture 6/7 0 0 0 0 0 0 0 0B
50H
Timer control status register 0
TMCSR0
R/W
0 0 0 0 0 0 0 0B
51H
Timer control status register 0
TMCSR0
R/W
_ _ _ _ 0 0 0 0B
16-bit Reload
Timer 0
52H
Timer register 0/reload register 0
TMR0/
TMRLR0
R/W
53H
Timer register 0/reload register 0
TMR0/
TMRLR0
R/W
XXXXXXXXB
54H
Timer control status register 1
TMCSR1
R/W
0 0 0 0 0 0 0 0B
55H
Timer control status register 1
TMCSR1
R/W
XXXXXXXXB
_ _ _ _ 0 0 0 0B
16-bit Reload
Timer 1
56H
Timer register 1/reload register 1
TMR1/
TMRLR1
R/W
57H
Timer register 1/reload register 1
TMR1/
TMRLR1
R/W
58H
Output compare control status register 0
OCS0
R/W
59H
Output compare control status register 1
OCS1
R/W
5AH
Output compare control status register 2
OCS2
R/W
5BH
Output compare control status register 3
OCS3
R/W
Output Compare 0 0 0 0 _ _ 0 0B
2/3
_ _ _ 0 0 0 0 0B
0 0 0 0 0 0 0 0B
5CH to 6BH
XXXXXXXXB
XXXXXXXXB
Output Compare 0 0 0 0 _ _ 0 0B
0/1
_ _ _0 0 0 0 0B
Reserved
6CH
Timer Data register
TCDT
R/W
6DH
Timer Data register
TCDT
R/W
6EH
Timer Control register
TCCS
R/W
6FH
ROM mirror register
ROMM
R/W
I/O Timer
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
ROM Mirror
_ _ _ _ _ _ _ 1B
70H to 7FH
Reserved for CAN 0 Interface. Refer to “CAN Controller Hardware Manual”
80H to 8F H
Reserved for CAN 1 Interface. Refer to “CAN Controller Hardware Manual”
90H to 9D H
Reserved
9EH
ROM correction control status register
PACSR
R/W
ROM Correction 0 0 0 0 0 0 0 0B
9FH
Delayed interrupt/release register
DIRR
R/W
Delayed Interrupt _ _ _ _ _ _ _ 0B
A0H
Low-power mode register
LPMCR
R/W
Low Power
Controller
0 0 0 1 1 0 0 0B
A1H
Clock selector register
CKSCR
R/W
Low Power
Controller
1 1 1 1 1 1 0 0B
A2H to A4H
Reserved
(Continued)
22
MB90540/545 Series
(Continued)
Address
Register
A5H
Automatic ready function select register
ARSR
W
A6H
External address output control register
HACR
W
A7H
Bus control signal select register
ECSR
W
A8H
Watchdog control register
WDTC
R/W
Watchdog Timer
A9H
Time Base Timer Control
TBTC
R/W
Time Base Timer 1 - - 0 0 1 0 0B
AAH
Watch timer control register
WTC
R/W
Watch Timer
1 X 0 0 0 0 0 0B
R/W
Flash Memory
0 0 0 X 0 _ _ 0B
ABH to ADH
AEH
Abbreviation Access
Peripheral
Initial value
0 0 1 1 _ _ 0 0B
External Memory
0 0 0 0 0 0 0 0B
Access
0 0 0 0 0 0 0 _B
XXXXX 1 1 1B
Reserved
Flash control status register
(Flash only, otherwise reserved)
AFH
FMCS
Reserved
B0H
Interrupt control register 00
ICR00
R/W
0 0 0 0 0 1 1 1B
B1H
Interrupt control register 01
ICR01
R/W
0 0 0 0 0 1 1 1B
B2H
Interrupt control register 02
ICR02
R/W
0 0 0 0 0 1 1 1B
B3H
Interrupt control register 03
ICR03
R/W
0 0 0 0 0 1 1 1B
B4H
Interrupt control register 04
ICR04
R/W
0 0 0 0 0 1 1 1B
B5H
Interrupt control register 05
ICR05
R/W
0 0 0 0 0 1 1 1B
B6H
Interrupt control register 06
ICR06
R/W
0 0 0 0 0 1 1 1B
B7H
Interrupt control register 07
ICR07
R/W
B8H
Interrupt control register 08
ICR08
R/W
B9H
Interrupt control register 09
ICR09
R/W
0 0 0 0 0 1 1 1B
BAH
Interrupt control register 10
ICR10
R/W
0 0 0 0 0 1 1 1B
BBH
Interrupt control register 11
ICR11
R/W
0 0 0 0 0 1 1 1B
BCH
Interrupt control register 12
ICR12
R/W
0 0 0 0 0 1 1 1B
BDH
Interrupt control register 13
ICR13
R/W
0 0 0 0 0 1 1 1B
BEH
Interrupt control register 14
ICR14
R/W
0 0 0 0 0 1 1 1B
BFH
Interrupt control register 15
ICR15
R/W
0 0 0 0 0 1 1 1B
COH to FF H
Interrupt
controller
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
External
Address
Register
Abbreviation Access
Peripheral
1FF0H
ROM Correction Address 0
PADR0
R/W
XXXXXXXXB
1FF1H
ROM Correction Address 1
PADR0
R/W
XXXXXXXXB
1FF2H
ROM Correction Address 2
PADR0
R/W
1FF3H
ROM Correction Address 3
PADR1
R/W
1FF4H
ROM Correction Address 4
PADR1
R/W
XXXXXXXXB
1FF5H
ROM Correction Address 5
PADR1
R/W
XXXXXXXXB
ROM correction
Initial value
XXXXXXXXB
XXXXXXXXB
23
MB90540/545 Series
Address
Register
Abbreviation Access
3900H
Reload L
PRLL0
R/W
3901H
Reload H
PRLH0
R/W
3902H
Reload L
PRLL1
R/W
3903H
Reload H
PRLH1
R/W
XXXXXXXXB
3904H
Reload L
PRLL2
R/W
XXXXXXXXB
3905H
Reload H
PRLH2
R/W
3906H
Reload L
PRLL3
R/W
3907H
Reload H
PRLH3
R/W
XXXXXXXXB
3908H
Reload L
PRLL4
R/W
XXXXXXXXB
3909H
Reload H
PRLH4
R/W
390AH
Reload L
PRLL5
R/W
390BH
Reload H
PRLH5
R/W
XXXXXXXXB
390CH
Reload L
PRLL6
R/W
XXXXXXXXB
390DH
Reload H
PRLH6
R/W
390EH
Reload L
PRLL7
R/W
390FH
Reload H
PRLH7
R/W
3910H to
3917H
Peripheral
Initial value
XXXXXXXXB
16-bit Programmable Pulse
Generator 0/1
16-bit Programmable Pulse
Generator 2/3
16-bit Programmable Pulse
Generator 4/5
16-bit Programmable Pulse
Generator 6/7
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reserved
3918H
Input Capture 0
IPCP0
R
3919H
Input Capture 0
IPCP0
R
391AH
Input Capture 1
IPCP1
R
391BH
Input Capture 1
IPCP1
R
XXXXXXXXB
391CH
Input Capture 2
IPCP2
R
XXXXXXXXB
391DH
Input Capture 2
IPCP2
R
391EH
Input Capture 3
IPCP3
R
391FH
Input Capture 3
IPCP3
R
XXXXXXXXB
3920H
Input Capture 4
IPCP4
R
XXXXXXXXB
3921H
Input Capture 4
IPCP4
R
3922H
Input Capture 5
IPCP5
R
3923H
Input Capture 5
IPCP5
R
XXXXXXXXB
3924H
Input Capture 6
IPCP6
R
XXXXXXXXB
3925H
Input Capture 6
IPCP6
R
3926H
Input Capture 7
IPCP7
R
3927H
Input Capture 7
IPCP7
R
XXXXXXXXB
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
Input Capture 6/7
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
24
MB90540/545 Series
(Continued)
Address
Register
Abbreviation Access
Peripheral
Initial value
3928H
Output Compare 0
OCCP0
R/W
3929H
Output Compare 0
OCCP0
R/W
392AH
Output Compare 1
OCCP1
R/W
392BH
Output Compare 1
OCCP1
R/W
XXXXXXXXB
392CH
Output Compare 2
OCCP2
R/W
XXXXXXXXB
392DH
Output Compare 2
OCCP2
R/W
392EH
Output Compare 3
OCCP3
R/W
392FH
Output Compare 3
OCCP3
R/W
XXXXXXXXB
Output Compare 0/1
Output Compare 2/3
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
3930H to
39FFH
Reserved
3A00H to
3AFFH
Reserved for CAN 0 Interface. Refer to “CAN Controller Hardware Manual”
3B00H to
3BFFH
Reserved for CAN 0 Interface. Refer to “CAN Controller Hardware Manual”
3C00H to
3CFFH
Reserved for CAN 1 Interface. Refer to “CAN Controller Hardware Manual”
3D00H to
3DFFH
Reserved for CAN 1 Interface. Refer to “CAN Controller Hardware Manual”
3E00H to
3FFFH
Reserved
Note
Initial value of “_” represents unused bit, “X” represents unknown value.
Addresses in the range 0000H to 00FFH, which are not listed in the table, are reserved for the primary functions
of the MCU. A read access to these reserved addresses results in an “X” reading and any write access
should not be performed.
25
MB90540/545 Series
■ CAN CONTROLLER
The MB90540 series contains two CAN controllers (CAN0 and CAN1), the MB90545 series contains only one
(CAN0). The Evaluation Chip MB90V540 also has two CAN controllers.
The CAN controller has the following features:
• Conforms to CAN Specification Version 2.0 Part A and B
- Supports transmission/reception in standard frame and extended frame formats
• Supports transmission of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
- 29-bit ID and 8-byte data
- Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as 1D acceptance mask
- Two acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 Kbit/s to 1 Mbit/s (when input clock is at 16 MHz)
List of Control Registers
Address
26
CAN0
CAN1
000070H
000080H
000071H
000081H
000072H
000082H
000073H
000083H
000074H
000084H
000075H
000085H
000076H
000086H
000077H
000087H
000078H
000088H
000079H
000089H
00007AH
00008AH
00007BH
00008BH
00007CH
00008CH
00007DH
00008DH
00007EH
00008EH
00007FH
00008FH
Register
Abbreviation
Access
Initial Value
Message buffer valid register
BVALR
R/W
00000000 00000000B
Transmit request register
TREQR
R/W
00000000 00000000B
Transmit cancel register
TCANR
W
00000000 00000000B
Transmit complete register
TCR
R/W
00000000 00000000B
Receive complete register
RCR
R/W
00000000 00000000B
Remote request receiving register
RRTRR
R/W
00000000 00000000B
Receive overrun register
ROVRR
R/W
00000000 00000000B
RIER
R/W
00000000 00000000B
Receive interrupt enable register
MB90540/545 Series
List of Control Registers
Address
CAN0
CAN1
003B00H
003D00H
003B01H
003D01H
003B02H
003D02H
003B03H
003D03H
003B04H
003D04H
003B05H
003D05H
003B06H
003D06H
003B07H
003D07H
003B08H
003D08H
003B09H
003D09H
003B0AH
003D0AH
003B0BH
003D0BH
003B0CH
003D0CH
003B0DH
003D0DH
003B0EH
003D0EH
003B0FH
003D0FH
003B10H
003D10H
003B11H
003D11H
003B12H
003D12H
003B13H
003D13H
003B14H
003D14H
003B15H
003D15H
003B16H
003D16H
003B17H
003D17H
003B18H
003D18H
003B19H
003D19H
003B1AH
003D1AH
003B1BH
003D1BH
Register
Abbreviation Access
Initial Value
Control status register
CSR
R/W, R
00---000 0----0-1B
Last event indicator register
LEIR
R/W
-------- 000-0000B
Receive/transmit error counter
RTEC
R
00000000 00000000B
Bit timing register
BTR
R/W
-1111111 11111111B
IDE register
IDER
R/W
XXXXXXXX XXXXXXXXB
Transmit RTR register
TRTRR
R/W
00000000 00000000B
Remote frame receive waiting
register
RFWTR
R/W
XXXXXXXX XXXXXXXXB
Transmit interrupt enable register
TIER
R/W
00000000 00000000B
XXXXXXXX XXXXXXXXB
Acceptance mask select register
AMSR
R/W
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
Acceptance mask register 0
AMR0
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
Acceptance mask register 1
AMR1
R/W
XXXXX--- XXXXXXXXB
27
MB90540/545 Series
List of Message Buffers (ID Registers) (1)
Address
28
CAN0
CAN1
003A00H
to
003A1FH
003C00H
to
003C1FH
003A20H
003C20H
003A21H
003C21H
003A22H
003C22H
003A23H
003C23H
003A24H
003C24H
003A25H
003C25H
003A26H
003C26H
003A27H
003C27H
003A28H
003C28H
003A29H
003C29H
003A2AH
003C2AH
003A2BH
003C2BH
003A2CH
003C2CH
003A2DH
003C2DH
003A2EH
003C2EH
003A2FH
003C2FH
003A30H
003C30H
003A31H
003C31H
003A32H
003C32H
003A33H
003C33H
003A34H
003C34H
003A35H
003C35H
003A36H
003C36H
003A37H
003C37H
003A38H
003C38H
003A39H
003C39H
003A3AH
003C3AH
003A3BH
003C3BH
Register
General-purpose RAM
Abbreviation Access
R/W
Initial Value
XXXXXXXXB
to
XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 0
IDR0
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 1
IDR1
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 2
IDR2
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 3
IDR3
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 4
IDR4
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 5
IDR5
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 6
IDR6
R/W
XXXXX--- XXXXXXXXB
MB90540/545 Series
List of Message Buffers (ID Registers) (2)
Address
CAN0
CAN1
003A3CH
003C3CH
003A3DH
003C3DH
003A3EH
003C3EH
003A3FH
003C3FH
003A40H
003C40H
003A41H
003C41H
003A42H
003C42H
003A43H
003C43H
003A44H
003C44H
003A45H
003C45H
003A46H
003C46H
003A47H
003C47H
003A48H
003C48H
003A49H
003C49H
003A4AH
003C4AH
003A4BH
003C4BH
003A4CH
003C4CH
003A4DH
003C4DH
003A4EH
003C4EH
003A4FH
003C4FH
003A50H
003C50H
003A51H
003C51H
003A52H
003C52H
003A53H
003C53H
003A54H
003C54H
003A55H
003C55H
003A56H
003C56H
003A57H
003C57H
003A58H
003C58H
003A59H
003C59H
003A5AH
003C5AH
003A5BH
003C5BH
003A5CH
003C5CH
003A5DH
003C5DH
003A5EH
003C5EH
003A5FH
003C5FH
Register
Abbreviation Access
Initial Value
XXXXXXXX XXXXXXXXB
ID register 7
IDR7
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 8
IDR8
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 9
IDR9
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 10
IDR10
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 11
IDR11
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 12
IDR12
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 13
IDR13
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 14
IDR14
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 15
IDR15
R/W
XXXXX--- XXXXXXXXB
29
MB90540/545 Series
List of Message Buffers (DLC Registers and Data Registers) (1)
Address
30
CAN0
CAN1
003A60H
003C60H
003A61H
003C61H
003A62H
003C62H
003A63H
003C63H
003A64H
003C64H
003A65H
003C65H
003A66H
003C66H
003A67H
003C67H
003A68H
003C68H
003A69H
003C69H
003A6AH
003C6AH
003A6BH
003C6BH
003A6CH
003C6CH
003A6DH
003C6DH
003A6EH
003C6EH
003A6FH
003C6FH
Register
Abbreviation Access
Initial Value
DLC register 0
DLCR0
R/W
----XXXXB
DLC register 1
DLCR1
R/W
----XXXXB
DLC register 2
DLCR2
R/W
----XXXXB
DLC register 3
DLCR3
R/W
----XXXXB
DLC register 4
DLCR4
R/W
----XXXXB
DLC register 5
DLCR5
R/W
----XXXXB
DLC register 6
DLCR6
R/W
----XXXXB
DLC register 7
DLCR7
R/W
----XXXXB
MB90540/545 Series
List of Message Buffers (DLC Registers and Data Registers) (2)
Address
CAN0
CAN1
003A70H
003C70H
003A71H
003C71H
003A72H
003C72H
003A73H
003C73H
003A74H
003C74H
003A75H
003C75H
003A76H
003C76H
003A77H
003C77H
003A78H
003C78H
003A79H
003C79H
003A7AH
003C7AH
003A7BH
003C7BH
003A7CH
003C7CH
003A7DH
003C7DH
003A7EH
003C7EH
003A7FH
003C7FH
003A80H
to
003A87H
003C80H
to
003C87H
003A88H
to
003A8FH
Register
Abbreviation Access
Initial Value
DLC register 8
DLCR8
R/W
----XXXX
DLC register 9
DLCR9
R/W
----XXXXB
DLC register 10
DLCR10
R/W
----XXXXB
DLC register 11
DLCR11
R/W
----XXXXB
DLC register 12
DLCR12
R/W
----XXXXB
DLC register 13
DLCR13
R/W
----XXXXB
DLC register 14
DLCR14
R/W
----XXXXB
DLC register 15
DLCR15
R/W
----XXXXB
Data register 0 (8 bytes)
DTR0
R/W
XXXXXXXXB
to
XXXXXXXXB
003C88H
to
003C8FH
Data register 1 (8 bytes)
DTR1
R/W
XXXXXXXXB
to
XXXXXXXXB
003A90H
to
003A97H
003C90H
to
003C97H
Data register 2 (8 bytes)
DTR2
R/W
XXXXXXXXB
to
XXXXXXXXB
003A98H
to
003A9FH
003C98H
to
003C9FH
Data register 3 (8 bytes)
DTR3
R/W
XXXXXXXXB
to
XXXXXXXXB
003AA0H
to
003AA7H
003CA0H
to
003CA7H
Data register 4 (8 bytes)
DTR4
R/W
XXXXXXXXB
to
XXXXXXXXB
003AA8H
to
003AAFH
003CA8H
to
003CAFH
Data register 5 (8 bytes)
DTR5
R/W
XXXXXXXXB
to
XXXXXXXXB
003AB0H
to
003AB7H
003CB0H
to
003CB7H
Data register 6 (8 bytes)
DTR6
R/W
XXXXXXXXB
to
XXXXXXXXB
31
MB90540/545 Series
List of Message Buffers (DLC Registers and Data Registers) (3)
Address
32
Register
Abbreviation Access
Initial Value
CAN0
CAN1
003AB8H
to
003ABFH
003CB8H
to
003CBFH
Data register 7 (8 bytes)
DTR7
R/W
XXXXXXXXB
to
XXXXXXXXB
003AC0H
to
003AC7H
003CC0H
to
003CC7H
Data register 8 (8 bytes)
DTR8
R/W
XXXXXXXXB
to
XXXXXXXXB
003AC8H
to
003ACFH
003CC8H
to
003CCFH
Data register 9 (8 bytes)
DTR9
R/W
XXXXXXXXB
to
XXXXXXXXB
003AD0H
to
003AD7H
003CD0H
to
003CD7H
Data register 10 (8 bytes)
DTR10
R/W
XXXXXXXXB
to
XXXXXXXXB
003AD8H
to
003ADFH
003CD8H
to
003CDFH
Data register 11 (8 bytes)
DTR11
R/W
XXXXXXXXB
to
XXXXXXXXB
003AE0H
to
003AE7H
003CE0H
to
003CE7H
Data register 12 (8 bytes)
DTR12
R/W
XXXXXXXXB
to
XXXXXXXXB
003AE8H
to
003AEFH
003CE8H
to
003CEFH
Data register 13 (8 bytes)
DTR13
R/W
XXXXXXXXB
to
XXXXXXXXB
003AF0H
to
003AF7H
003CF0H
to
003CF7H
Data register 14 (8 bytes)
DTR14
R/W
XXXXXXXXB
to
XXXXXXXXB
003AF8H
to
003AFFH
003CF8H
to
003CFFH
Data register 15 (8 bytes)
DTR15
R/W
XXXXXXXXB
to
XXXXXXXXB
MB90540/545 Series
■ INTERRUPT MAP
Interrupt vector
Interrupt control register
EI2OS
clear
Number
Address
Number
Address
Reset
N/A
#08
FFFFDCH
INT9 instruction
N/A
#09
FFFFD8H
Exception
N/A
#10
FFFFD4H
CAN 0 RX
N/A
#11
FFFFD0H
CAN 0 TX/NS
N/A
#12
FFFFCCH
ICR00
0000B0H
CAN 1 RX
N/A
#13
FFFFC8H
CAN 1 TX/NS
N/A
#14
FFFFC4H
ICR01
0000B1H
*1
#15
FFFFC0H
N/A
#16
FFFFBCH
ICR02
0000B2H
16-bit Reload Timer 0
*1
#17
FFFFB8H
8/10-bit A/D Converter
*1
#18
FFFFB4H
ICR03
0000B3H
N/A
#19
FFFFB0H
External Interrupt INT2/INT3
*1
#20
FFFFACH
ICR04
0000B4H
Serial I/O
*1
#21
FFFFA8H
8/16-bit PPG 0/1
N/A
#22
FFFFA4H
ICR05
0000B5H
Input Capture 0
*1
#23
FFFFA0H
External Interrupt INT4/INT5
*1
#24
FFFF9CH
ICR06
0000B6H
Input Capture 1
*1
#25
FFFF98H
8/16-bit PPG 2/3
N/A
#26
FFFF94H
ICR07
0000B7H
*1
#27
FFFF90H
Watch Timer
N/A
#28
FFFF8CH
ICR08
0000B8H
8/16-bit PPG 4/5
N/A
#29
FFFF88H
Input Capture 2/3
*1
#30
FFFF84H
ICR09
0000B9H
8/16-bit PPG 6/7
N/A
#31
FFFF80H
Output Compare 0
*1
#32
FFFF7CH
ICR10
0000BAH
Output Compare 1
*1
#33
FFFF78H
Input Capture 4/5
*1
#34
FFFF74H
ICR11
0000BBH
Output Compare 2/3 - Input Capture 6/7
*1
#35
FFFF70H
16-bit Reload Timer 1
*1
#36
FFFF6CH
ICR12
0000BCH
UART 0 RX
*2
#37
FFFF68H
UART 0 TX
*1
#38
FFFF64H
ICR13
0000BDH
UART 1 RX
*2
#39
FFFF60H
UART 1 TX
*1
#40
FFFF5CH
ICR14
0000BEH
Flash Memory
N/A
#41
FFFF58H
Delayed interrupt
N/A
#42
FFFF54H
ICR15
0000BFH
Interrupt cause
External Interrupt INT0/INT1
Time Base Timer
I/O Timer
External Interrupt INT6/INT7
33
MB90540/545 Series
*1: The interrupt request flag is cleared by the EI2OS interrupt clear signal.
*2: The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available.
N/A:The interrupt request flag is not cleared by the EI2OS interrupt clear signal.
Note:• For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags
are cleared by the EI2OS interrupt clear signal.
•At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same
interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by a
hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the
first event. So it is recommended not to use the EI2OS for this interrupt number.
• If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control
register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor which
should be unique for each interrupt source. For this reason, when one interrupt source uses the EI2OS, the
other interrupt should be disabled.
34
MB90540/545 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
(VSS = AVSS = 0V)
Symbol
Value
Units
Remarks
Min.
Max.
VCC
VSS − 0.3
VSS + 6.0
V
AVCC
VSS − 0.3
VSS + 6.0
V
VCC = AVCC
*1
AVRH,
AVRL
VSS − 0.3
VSS + 6.0
V
AVCC ≥ AVRH/AVRL,
AVRH ≥ AVRL
*1
Input voltage
VI
VSS − 0.3
VSS + 6.0
V
*2
Output voltage
VO
VSS − 0.3
VSS + 6.0
V
*2
Clamp Current
ICLAMP
− 2.0
2.0
mA
"L" level max. output current
IOL
15
mA
*3
"L" level avg. output current
IOLAV
4
mA
*4
"L" level max. overall output current
∑IOL
100
mA
"L" level avg. overall output current
∑IOLAV
50
mA
*5
"H" level max. output current
IOH
−15
mA
*3
"H" level avg. output current
IOHAV
−4
mA
*4
"H" level max. overall output current
∑IOH
−100
mA
"H" level avg. overall output current
∑IOHAV
−50
mA
Power consumption
PD
500
mW
Operating temperature
TA
−40
+85
°C
TSTG
−55
+150
°C
Power supply voltage
Storage temperature
*5
MB90F543/F549
*1: AVCC, AVRL and AVRL should not exceed VCC, and AVRL should not exceed AVRH.
*2: VI and VO should not exceed VCC + 0.3V. VI should not exceed the specified ratings. However if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the VI
rating.
*3: The maximum output current is a peak value for a corresponding pin.
*4: Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*5: Total average current is an average current value observed for a 100 ms period for all corresponding pins.
Note: Average output current = operating current × operating efficiency
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
35
MB90540/545 Series
2. Recommended Conditions
Parameter
Symbol
(VSS = AVSS = 0V)
Value
Min.
Typ.
Max.
Units
Power supply voltage
VCC
4.5
5.0
5.5
V
Smooth capacitor
CS
0.022
0.1
1.0
µF
Operating temperature
TA
−40
+85
°C
Remarks
*
*: Use a ceramic capacitor or a capacitor of better AC characteristics. The VCC Capacitor should be greater than
this capacitor.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
• C Pin Connection Diagram
C
CS
36
MB90540/545 Series
3. DC Characteristics
Parame- Sym
ter
bol
Input H
voltage
Input L
voltage
Pin
(VCC = 5.0 V±10%, VSS = AVSS = 0V, TA = −40 °C to +85 °C)
Value
Condition
Units
Remarks
Min.
Typ.
Max.
CMOS hysVIHS teresis input
pin
0.8 VCC
VCC +
0.3
V
VIHM MD input pin
VCC −
0.3
VCC +
0.3
V
CMOS hysVILS teresis input
pin
VCC −
0.3
0.2
VCC
V
VILM MD input pin
VCC −
0.3
VCC +
0.3
V
VCC –
0.5
—
—
V
Output H
voltage
VOH
All output
pins
VCC = 4.5V,
IOH = −4.0mA
Output L
voltage
VOL
All output
pins
VCC = 4.5V,
IOL = 4.0mA
—
—
0.4
V
Input leak
current
IIL
VCC = 5.5V,
VSS < VI < VCC
–5
—
5
µA
ICC
VCC = 5.0 V±10%,
Internal frequency: 16 MHz,
At normal operation
—
45
60
mA
MB90F543/F549
ICCS
VCC = 5.0V±10%,
Internal frequency: 16 MHz,
At sleep
—
13
22
mA
MB90F543/F549
ICCL
VCC = 5.0V,
Internal frequency: 8 kHz,
At sub operation
—
0.2
1
mA
MB90F543/F549
VCC = 5.0V,
Internal frequency: 8 kHz,
At sub sleep
—
10
50
µA
MB90F543/F549
ICCT
VCC = 5.0V,
Internal frequency: 8 kHz,
At watch mode
—
10
50
µA
MB90F543/F549
ICCH1
VCC = 5.0 V±10%,
At stop, TA = 25°C
—
5
20
µA
MB90F543/F549
ICCH2
VCC = 5.0 V±10%,
At hardware standby mode,
TA = 25°C
—
50
100
µA
MB90F543/F549
—
—
10
80
pF
Power
supply
current*
Input
capacity
ICCLS
CIN
VCC
Other than
AVCC, AVSS,
AVRH, AVRL,
C, VCC, VSS
*: Current values are tentative. They are subject to change without notice according to improvements in the
characteristics. The power supply current testing conditions are when using the external clock.
37
MB90540/545 Series
4. AC Characteristics
(1) Clock Timing
Parameter
Oscillation frequency
Oscillation cycle time
Frequency deviation with
PLL *
Input clock pulse width
Input clock rise and fall
time
Machine clock frequency
Machine clock cycle time
(VCC = 5.0 V±10%, VSS = AVSS = 0 V, TA = −40 °C to +85 °C)
Value
Units
Remarks
Min.
Typ.
Max.
Symbol
Pin
fC
X0, X1
3
—
16
MHz
fCL
X0A, X1A
—
32.768
—
kHz
tCYL
X0, X1
62.5
—
333
ns
tLCYL
X0A, X1A
—
30.5
—
µs
∆f
—
—
—
5
%
PWH, PWL
X0
10
—
—
ns
PWLH,PWLL
X0A
—
15.2
—
µs
tCR, tCF
X0
—
—
5
ns
fCP
—
1.5
—
16
MHz When using main clock
fLCP
—
—
8.192
—
kHz
When using sub-clock
tCP
—
62.5
—
666
ns
When using main clock
tLCP
—
—
122.1
—
µs
When using sub-clock
Duty ratio is about 30 to 70%.
When using external clock
* : Frequency deviation indicates the maximum frequency difference from the target frequency when using a
multiplied clock.
α
∆f = ------ × 100%
fo
+α
Central frequency fO
−α
• Clock Timing
tCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCF
tCR
tLCYL
0.8 VCC
X0A
0.2 VCC
PWLH
PWLL
tCF
38
tCR
MB90540/545 Series
• Guaranteed operation range
Guaranteed operation range for MB90F543/F549
5.5
Power supply voltage
VCC (V)
TB
D
4.5
3.3
3.0
Guaranteed operation
range of MB90V540
Guaranteed PLL operation range
1.5
3
8
12
Machine clock fCP (MHz)
16
• Oscillation clock frequency and Machine clock frequency
×4
16
×3
×1
×2
12
Machine clock
fCP (MHz)
9
8
×1/2
(PLL off)
4
3
4
8
Oscillation clock fC (MHz)
16
AC characteristics are set to the measured reference voltage values below.
• Input signal waveform
Hysteresis Input Pin
0.8 VCC
0.2 VCC
• Output signal waveform
Output Pin
2.4 V
0.8 V
39
MB90540/545 Series
(2) Clock Output Timing
Parameter
Symbol
Cycle time
tCYC
CLK ↑ ⇒ CLK ↓
tCHCL
(VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Pin
Condition
Units
Remarks
Min. Max.
CLK
VCC = 5 V±10%
62.5
—
ns
20
—
ns
tCYC
tCHCL
CLK
2.4 V
2.4 V
0.8 V
(3) Reset and Hardware Standby Input
Parameter
Reset input time
Symbol
tRSTL
(VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Pin
Units
Remarks
Min.
Max.
RST
16 tCP
—
ns
Hardware standby input time
tHSTL
HST
16 tCP
—
ns
“tcp” represents one cycle time of the machine clock.
Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm.
tRSTL, tHSTL
RST
HST
40
0.2 VCC
0.2 VCC
MB90540/545 Series
(4) Power On Reset
Parameter
Symbol
Pin
Power on rise time
tR
VCC
tOFF
VCC
Power off time
Note
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Condition
Units
Remarks
Min. Max.
—
0.05
30
ms
50
—
ms
Due to repetitive operation
• VCC must be kept lower than 0.2 V before power-on.
• The above values are used for creating a power-on reset.
• Some registers in the device are initialized only upon a power-on reset. To initialize these register, turn on
the power supply using the above values.
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to
raise the voltage smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage with the PLL clock not used. If the voltage drop is
1 V or fewer per second, however, you can use the PLL clock.
VCC
TBD
RAM data being held
It is recommended to keep the
rising speed of the supply voltage
at 50 mV/ms or slower.
VSS
41
MB90540/545 Series
(5) Bus Timing (Read)
Parameter
Pin
tLHLL
ALE
tCP/2 − 20
Valid address ⇒ ALE ↓ time
tAVLL
ALE,
A23 to A16,
AD15 to
AD00
tCP/2 − 20
—
ns
ALE ↓ ⇒ Address valid time
tLLAX
ALE, AD15
to AD00
tCP/2 − 15
—
ns
Valid address ⇒ RD ↓ time
tAVRL
A23 toA16,
AD15 to
AD00, RD
tCP − 15
—
ns
Valid address ⇒ Valid data
input
tAVDV
A23 to A16,
AD15 to
AD00
—
5 tCP/2 − 60
ns
RD pulse width
tRLRH
RD
3 tCP/2 − 20
—
ns
RD ↓ ⇒ Valid data input
tRLDV
RD, AD15 to
AD00
—
3 tCP/2 − 60
ns
RD ↑ ⇒ Data hold time
tRHDX
RD, AD15 to
AD00
0
—
ns
RD ↓ ⇒ ALE ↑ time
tRHLH
RD, ALE
tCP/2 − 15
—
ns
RD ↑ ⇒ Address valid time
tRHAX
RD, A23 to
A16
tCP/2 − 10
—
ns
Valid address ⇒ CLK ↑ time
tAVCH
A23 to A16,
AD15 to
AD00, CLK
tCP/2 − 20
—
ns
RD ↓ ⇒ CLK ↑ time
tRLCH
RD, CLK
tCP/2 − 20
—
ns
ALE ↓ ⇒ RD ↓ time
tLLRL
ALE, RD
tCP/2 − 15
—
ns
ALE pulse width
42
Symbol
(VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = −40 °C to +85 °C)
Value
Condition
Units Remarks
Min.
Max.
—
ns
MB90540/545 Series
• Bus Timing (Read)
tRLCH
tAVCH
2.4 V
CLK
2.4 V
tLLAX
tAVLL
ALE
2.4 V
tRHLH
2.4 V
0.8 V
tLHLL
2.4 V
tAVRL
tRLRH
2.4 V
RD
0.8 V
tLLRL
tRHAX
A23 to A16
2.4 V
2.4 V
0.8 V
0.8 V
tRLDV
tAVDV
AD15 to AD00
2.4 V
0.8 V
Address
2.4 V
0.8 VCC
0.8 V
0.2 VCC
tRHDX
Read data
0.8 VCC
0.2 VCC
43
MB90540/545 Series
(6) Bus Timing (Write)
Parameter
(VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = −40 °C to +85 °C)
Value
Condition
Units Remarks
Min.
Max.
Symbol
Pin
Valid address ⇒ WR ↓ time
tAVWL
A23 to A16,
AD15 to AD00,
WR
WR pulse width
tWLWH
Valid data output ⇒ WR ↑ time
tCP – 15
—
ns
WR
3 tCP/2 – 20
—
ns
tDVWH
AD15 to AD00,
WR
3 tCP/2 – 20
—
ns
WR ↑ ⇒ Data hold time
tWHDX
AD15 to AD00,
WR
20
—
ns
WR ↑ ⇒ Address valid time
tWHAX
A23 to A16,
WR
tCP/2 – 10
—
ns
WR ↑ ⇒ ALE ↑ time
tWHLH
WR, ALE
tCP/2 – 15
—
ns
WR ↓ ⇒ CLK ↑ time
tWLCH
WR, CLK
tCP/2 – 20
—
ns
—
• Bus Timing (Write)
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
2.4 V
WR (WRL, WRH)
0.8 V
tWHAX
A23 to A16
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
AD15 to AD00
44
2.4 V
0.8 V
Address
2.4 V
0.8 V
Write data
tWHDX
2.4 V
0.8 V
MB90540/545 Series
(7) Ready Input Timing
Parameter
Symbol
Pin
RDY setup time
tRYHS
RDY
RDY hold time
tRYHH
RDY
(VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = −40 °C to +85 °C)
Value
Condition
Units
Remarks
Min.
Max.
—
45
—
ns
0
—
ns
Note: If the RDY setup time is insufficient, use the auto-ready function.
• Ready Input Timing
2.4 V
CLK
ALE
RD/WR
tRYHS
RDY
no WAIT is used.
RDY
When WAIT is used
(1 cycle).
0.8 VCC
tRYHH
0.8 VCC
0.2 VCC
45
MB90540/545 Series
(8) Hold Timing
Parameter
Symbol
Pin
Pin floating ⇒ HAK ↓ time
tXHAL
HAK
HAK ↑ time ⇒ Pin valid time
tHAHV
HAK
(VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = −40 °C to +85 °C)
Value
Condition
Units
Remarks
Min.
Max.
—
30
tCP
ns
tCP
2 tCP
ns
Note: There is more than 1 cycle from the time HRQ is read to the time the HAK is changed.
• Hold Timing
2.4 V
HAK
0.8 V
tHAHV
tXHAL
2.4 V
Each pin
0.8 V
Symbol
(VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = –40 °C to +85 °C)
Value
Pin Symbol
Condition
Units Remarks
Min. Max.
8 tCP
—
ns
–80
80
ns
100
—
ns
SCK0 to SCK2,
SIN0 to SIN2
60
—
ns
tSHSL
SCK0 to SCK2
4 tCP
—
ns
Serial clock "L" pulse width
tSLSH
SCK0 to SCK2
4 tCP
—
ns
SCK ↓ ⇒ SOT delay time
tSLOV
—
150
ns
Valid SIN ⇒ SCK ↑
tIVSH
60
—
ns
SCK ↑ ⇒ Valid SIN hold time
tSHIX
60
—
ns
Serial clock cycle time
tSCYC
SCK ↓ ⇒ SOT delay time
tSLOV
Valid SIN ⇒ SCK ↑
tIVSH
SCK ↑ ⇒ Valid SIN hold time
tSHIX
Serial clock "H" pulse width
SCK0 to SCK2
SCK0 to SCK2,
SOT0 to SOT2 Internal clock operaSCK0 to SCK2, tion output pins are
CL = 80 pF + 1 TTL.
SIN0 to SIN2
SCK0 to SCK2,
External clock operSOT0 to SOT2
ation output pins are
SCK0 to SCK2, CL = 80 pF + 1 TTL.
SIN0 to SIN2
SCK0 to SCK2,
SIN0 to SIN2
Note: 1.AC characteristic in CLK synchronized mode.
2. CL is load capacity value of pins when testing.
3. tCP is the machine cycle (Unit: ns).
46
2.4 V
0.8 V
(9) UART0/1, Serial I/O Timing
Parameter
High impedance
MB90540/545 Series
• Internal Shift Clock Mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
SOT
tIVSH
tSHIX
0.8 VCC
0.2 VCC
SIN
0.8 VCC
0.2 VCC
• External Shift Clock Mode
tSLSH
SCK
tSHSL
0.8 VCC
0.8 VCC
0.2 VCC 0.2 VCC
tSLOV
SOT
2.4 V
0.8 V
tIVSH
SIN
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.2 VCC
47
MB90540/545 Series
(10) Timer Related Resource Input Timing
Parameter
Input pulse width
(VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = −40 °C to +85 °C)
Value
Condition
Units Remarks
Min.
Max.
Symbol
Pin
tTIWH
TIN0, TIN1
tTIWL
IN0 to IN7
—
4 tCP
—
ns
• Timer Input Timing
0.8 VCC
0.8 VCC
0.2 VCC
tTIWH
tTIWL
(11) Timer Related Resource Output Timing
Parameter
Symbol
Pin
CLK ↑ ⇒ TOUT change time
tTO
TOT0 to TOT1,
PPG0 to PPG3
• Timer Output Timing
CLK
2.4 V
2.4 V
0.8 V
TOUT
tTO
48
0.2 VCC
(VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = −40 °C to +85 °C)
Value
Condition
Units
Remarks
Min.
Max.
—
30
—
ns
MB90540/545 Series
(12) Trigger Input Timing
Parameter
Input pulse width
(VCC = 4.5 to 5.5 V, VSS = 0 V, TA = –40 °C to +85 °C)
Value
Condition
Units Remarks
Min.
Max.
Symbol
Pin
tTRGH
tTRGL
INT0 to INT7,
ADTG
—
5 tCP
—
ns
• Trigger Input Timing
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tTRGH
tTRGL
49
MB90540/545 Series
5. A/D Converter
( VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0 V,3.0 V ≤ AVRH − AVRL, TA = −40 °C to +85 °C)
Rated Value
Parameter
Symbol
Pin
Units Remarks
Min.
Typ.
Max.
Resolution
—
—
—
10
bit
Conversion error
—
—
—
—
±5.0
LSB
Nonlinearity error
—
—
—
—
±2.5
LSB
Differential nonlinearity error
—
—
—
—
±1.9
LSB
Zero reading voltage
VOT
AN0 to AN7 AVRL − 3.5 AVRL + 0.5 AVRL + 4.5
mV
Full scale reading voltage
VFST
AN0 to AN7 AVRH − 6.5 AVRH − 1.5 AVRH + 1.5
mV
Conversion time
—
—
—
352tCP
—
ns
Sampling time
—
—
—
64tCP
—
ns
Analog port input current
IAIN
AN0 to AN7
−10
—
10
µA
Analog input voltage range
VAIN
AN0 to AN7
AVRL
—
AVRH
V
Reference voltage range
Power supply current
Reference voltage current
Offset between input channels
—
AVRH
AVRL + 2.7
—
AVCC
V
—
AVRL
0
—
AVRH − 2.7
V
IA
AVCC
—
5
—
mA
IAH
AVCC
—
—
5
µA
IR
AVRH
200
400
600
µA
IRH
AVRH
—
—
5
µA
—
AN0 to AN7
—
—
4
LSB
*
*
*: When not using an A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) when the CPU is stopped.
50
MB90540/545 Series
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter
Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00
0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual
conversion characteristics
Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error: The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
Total error
3FF
3FE
0.5 LSB
Actual conversion
value
Digital output
3FD
{1 LSB × (N – 1) + 0.5 LSB}
004
VNT
(measured value)
003
Actual conversion
characteristics
002
Theoretical
characteristics
001
0.5 LSB
AVRL
1 LSB = (Theoretical value)
AVRH – AVRL
1024
VOT (Theoretical value) = AVRL + 0.5 LSB[V]
Analog input
[V]
AVRH
Total error for digital output N =
VNT – {1 LSB × (N – 1) + 0.5 LSB}
[LSB]
1 LSB
VNT: Voltage at a transition of digital output from (N – 1) to N
VFST (Theoretical value) = AVRH – 1.5 LSB[V]
(Continued)
51
MB90540/545 Series
(Continued)
Linearity error
Differential linearity error
Theoretical characteristics
3FF
Actual conversion
value
{1 LSB × (N – 1)+ VOT}
3FE
N+1
Actual conversion value
VFST
(measured value)
Digital output
Digital output
3FD
VNT
004
Actual conversion
characteristics
003
N
V(N + 1)T
(measured value)
N–1
VNT (measured value)
002
Theoretical
characteristics
001
Actual conversion
value
N–2
VOT (measured value)
AVRL
Analog input
AVRH
AVRL
Analog input
AVRH
VNT – {1 LSB × (N – 1) + VOT}
Linearity error of
[LSB]
digital output N =
1 LSB
Differential linearity error
=
of digital N
1 LSB =
V(N + 1)T – VNT
– 1 LSB [LSB]
1 LSB
VFST – VOT
[V]
1022
VOT: Voltage at transition of digital output from “000H” to “001H”
VFST: Voltage at transition of digital output from “3FEH” to “3FFH”
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions, :
• Output impedance values of the external circuit of 15 kΩ or lower are recommended.
• When capacitors are connected to external pins, the capacitance of several thousand times the internal
capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor
and internal capacitor.
When the output impedance of the external circuit is too high, the sampling period for analog voltages may not
be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz).
• Equipment of analog input circuit model
C0
Comparator
Analog input
C1
Note: Listed values must be considered as standards.
• Error
The smaller the | AVRH − AVRL |, the greater the error would become relatively.
52
MB90540/545 Series
■ ORDERING INFORMATION
Part number
Package
MB90F543PF
MB90F549PF
100-pin Plastic QFP
(FPT-100P-M06)
MB90V540CR
256-pin Ceramic PGA
(PGA-256C-A01)
Remarks
For evaluation
53
MB90540/545 Series
■ PACKAGE DIMENSIONS
100-pin Plastic QFP
(FPT-100P-M06)
23.90±0.40(.941±.016)
3.35(.132)MAX
(Mounting height)
0.05(.002)MIN
(STAND OFF)
20.00±0.20(.787±.008)
80
51
81
50
14.00±0.20
(.551±.008)
17.90±0.40
(.705±.016)
12.35(.486)
REF
16.30±0.40
(.642±.016)
INDEX
31
100
"A"
LEAD No.
1
30
0.65(.0256)TYP
0.30±0.10
(.012±.004)
0.13(.005)
0.15±0.05(.006±.002)
M
Details of "A" part
0.25(.010)
Details of "B" part
"B"
0.10(.004)
18.85(.742)REF
22.30±0.40(.878±.016)
C
0.30(.012)
0.18(.007)MAX
0.53(.021)MAX
0
10°
0.80±0.20
(.031±.008)
2000 FUJITSU LIMITED F100008-3C-3
Dimensions in mm (inches)
54
MB90540/545 Series
250-pin Ceramic PGA
(PGA-256C-A01)
C0.51 (.020) TYP
(3 PLCS)
0.20 ± 0.05
(.0079 ± .002)
22.86 (.900)
REF
1.27 (.050) TYP
INDEX AREA
+ .012
1.50 +– 0.30
0.10 (.059 – .004 )
C1.02 (.040) TYP
EXTRA INDEX PIN
25.10 ± 0.30 SQ
(.988 ± .012)
6.35 (.250) MAX
C
1994 FUJITSU LIMITED R256001SC-5-3
Dimensions in mm (inches)
55
MB90540/545 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0101
FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.