FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13704-5E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90590/590G Series
MB90591/591G/F591A/F591G/594/594G/F594A/F594G
MB90V590A/V590G
■ DESCRIPTION
The MB90590/590G series with two FULL-CAN*1 interfaces and FLASH ROM is especially designed for automotive and industrial applications. Its main features are two on board CAN Interfaces, which conform to V2.0 Part A
and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal
full CAN approach.
The instruction set of F2MC-16LX CPU core inherits an AT architecture of the F2MC*2 family with additional
instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions,
and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long
word data.
The MB90590/590G series has peripheral resources of 8/10-bit A/D converters, UART (SCI), extended I/O serial
interface, 8/16-bit PPG timer, I/O timer (input capture (ICU), output compare (OCU)), stepping motor controller,
and sound generator.
*1 : Controller Area Network (CAN) - License of Robert Bosch GmbH
*2 : F2MC stands for FUJITSU Flexible Microcontroller.
■ PACKAGE
100-pin Plastic QFP
(FPT-100P-M06)
MB90590/590G Series
■ FEATURES
• Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation
(at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction execution time : 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock,
VCC of 5.0 V)
• Instruction set to optimize controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C language) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed : 4-byte instruction queue
• Enhanced interrupt function : 8 levels, 34 factors
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS) : Up to 10 channels
• Embedded ROM size and types
Mask ROM : 256 Kbytes/384 Kbytes
Flash ROM : 256 Kbytes/384 Kbytes
Embedded RAM size : 6 Kbytes/8 Kbytes
• Flash ROM
Supports automatic programming, Embedded Algorithm TM*
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory
Erase can be performed on each block
Block protection with external programming voltage
• Low-power consumption (stand-by) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Clock mode
Hardware stand-by mode
• Process
0.5µm CMOS technology
• I/O port
General-purpose I/O ports : 78 ports
• Timer
Watchdog timer : 1 channel
8/16-bit PPG timer : 8/16-bit × 6 channels
16-bit re-load timer : 2 channels
2
MB90590/590G Series
• 16-bit I/O timer
16-bit free-run timer : 1 channel
Input capture : 6 channels
Output compare : 6 channels
• Extended I/O serial interface : 1 channel
• UART (3 channels)
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.
• Stepping motor controller (4 channels)
• External interrupt circuit (8 channels)
A module for starting an extended intelligent I/O service (EI2OS) and generating an external interrupt which
is triggered by an external input.
• Delayed interrupt generation module
Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
8/10-bit resolution can be selectively used.
Starting by an external trigger input.
• FULL-CAN interfaces : 2
Conforming to Version 2.0 Part A and Part B
Flexible message buffering (mailbox and FIFO buffering can be mixed)
• Sound generator
• 18-bit Time-base counter
• Clock timer : 1 channel
• External bus interface : Maximum address space 16 Mbytes
* : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
3
MB90590/590G Series
■ PRODUCT LINEUP
MB90591/591G/594/594G
MB90F591A/F591G/
F594A/F594G
MB90V590A/V590G
Mask ROM product
Flash ROM product
Evaluation product
ROM size
384/256 Kbytes
384/256 Kbytes
Boot block
Hard-wired reset vector
None
RAM size
8/6 Kbytes
8/6 Kbytes
8 Kbytes
Features
Classification
Emulator-specific power
supply *1
None
CPU functions
The number of instructions : 340
Instruction bit length : 8 bits, 16 bits
Instruction length : 1 byte to 7 bytes
Data bit length : 1 bit, 8 bits, 16 bits
Minimum execution time : 62.5 ns (at machine clock frequency of 16 MHz)
Interrupt processing time : 1.5 µs
(at machine clock frequency of 16 MHz, minimum value)
UART (3 channels)
Clock synchronized transmission (500 Kbps / 1 Mbps / 2 Mbps)
Clock asynchronized transmission (4808/5208/9615/10417/19230/38460/62500
/500000 bps at machine clock frequency of 16 MHz)
Transmission can be performed by bi-directional serial transmission or by master/
slave connection.
8/10-bit A/D converter
Conversion precision : 8/10-bit can be selectively used.
Number of inputs : 8
One-shot conversion mode (converts selected channel once only)
Scan conversion mode (converts two or more successive channels and can program
up to 8 channels)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
8/16-bit PPG timers
(6 channels)
Number of channels : 6 (8/16-bit × 6 channels)
PPG operation of 8-bit or 16-bit
A pulse wave of given intervals and given duty ratios can be output.
Pulse interval : fsys, fsys/21, fsys/22, fsys/23, fsys/24, 128µs
(at oscillation of 4 MHz, fsys = system clock frequency of 16 MHz, fosc = oscillation
clock frequency)
16-bit Reload timer
Number of channels : 2
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)
Supports External Event Count function
16-bit
I/O
timer
16-bit
Number of channels : 6 (8/16-bit × 6 channels)
Output compares Pin input factor : A match signal of compare register
Input captures
Number of channels : 6
Rewriting a register value upon a pin input (rising, falling, or both edges)
(Continued)
4
MB90590/590G Series
(Continued)
Features
CAN Interface
MB90591/591G/594/594G
MB90F591A/F591G/
F594A/F594G
MB90V590A/V590G
Number of channels : 2
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full bit compare / Full bit mask / Two partial bit masks
Supports up to 1Mbps
CAN bit timing setting :
MB90xxx : TSEG2 ≥ RSJW+2TQ
MB90xxxG : TSEG2 ≥ RSJW
Stepping motor controller Four high current outputs for each channel
(4 channels)
Synchronized two 8-bit PWM’s for each channel
External interrupt circuit
Number of inputs : 8
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
Sound generator
8-bit PWM signal is mixed with tone frequency from 8-bit reload counter
PWM frequency : 62.5K, 31.2K, 15.6K, 7.8KHz (at System clock = 16MHz)
Tone frequency : PWM frequency / 2 / (reload value + 1)
Extended I/O serial
interface
Clock synchronized transmission (31.25K/62.5K/125K/500K/1Mbps at machine clock
frequency of 16 MHz)
LSB first/MSB first
Clock timer
Directly operates with the system clock
Read/Write accessible Second/Minute/Hour registers
Watchdog timer
Reset generation interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Flash Memory
Supports automatic programming, Embedded Algorithm TM and
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash
Memory
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Writer from Minato Electronics Inc.
Low-power consumption
(stand-by) mode
Sleep/stop/CPU intermittent operation/clock timer/hardware stand-by
Process
Power supply voltage for
operation*2
Package
CMOS
5 V±10 % (MB90V590A, MB90F594A, MB90594, MB90V590G,
MB90F594G, MB90594G)
5 V±5 % (MB90F591G, MB90591G, MB90F591A, MB90591)
QFP-100
PGA-256
*1 : It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.
Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details.
*2 : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
5
MB90590/590G Series
■ PIN ASSIGNMENT
X1
X0
Vss
81
Vcc
84
82
P00/IN0
85
65
P81/PWM1M2
P37/SIN1
17
64
P80/PWM1P2
P40/SCK1
18
63
DVSS
P41/SOT1
P42/SOT2
19
62
P77/PWM2M1
20
61
P76/PWM2P1
P43/SCK2
21
60
P75/PWM1M1
P44/SIN2
22
59
P74/PWM1P1
Vcc
23
58
DVCC
P45/SCIN3
24
57
P73/PWM2M0
P46/SCK3
25
56
P72/PWM2P0
P47/SOT3
26
55
P71/PWM1M0
C
27
54
P70/PWM1P0
P50/PPG0
28
53
DVSS
P51/PPG1
29
52
HST
P52/PPG2
30
51
MD2
50
P82/PWM2P2
16
MD1
66
49
15
MD0
P83/PWM2M2
P35/SCK0
P36/SIN0
48
67
P56/TIN
14
P57/TOT/WOT
DVCC
P34/SOT0
47
68
P67/AN7
13
46
P84/PWM1P3
P33
45
69
P66/AN6
12
44
P85/PWM1M3
P32
43
11
70
P65/AN5
P86/PWM2P3
Vss
P64/AN4
71
42
10
Vss
P87/PWM2M3
P31
41
DVSS
72
P63/AN3
73
9
40
8
P30
P62/AN2
P27/INT7
39
P91/RX0
P90/TX0
P61/AN1
74
38
75
7
P60/AN0
6
P26/INT6
37
RST
P92/INT0
36
76
AVss
5
AVRL
P24/INT4
P25/INT5
35
77
AVRH
4
34
P93/INT1
P23
AVcc
78
33
3
P55/PPG5/ADTG
P94/INT2
P22
32
P95/INT3
79
31
80
2
P54/PPG4
1
P21
P53/PPG3
P20
(FPT-100P-M06)
6
83
P01/IN1
86
87
P06/OUT0
91
88
P07/OUT1
92
P05/IN5
P10/OUT2
93
P04/IN4
P03/IN3
P02/IN2
P11/OUT3
94
89
P12/OUT4
95
90
P14/RX1
P13/OUT5
P15/TX1
98
96
P16/SGO
99
97
P17/SGA
100
(Top view)
MB90590/590G Series
■ PIN DESCRIPTION
No.
Pin name
82
X0
83
X1
77
52
85 to 90
Circuit type
A
Oscillator pin
RST
B
Reset input
HST
C
Hardware standby input
P00 to P05
IN0 to IN5
D
P06 to P07,
P10 to P13
91 to 96
D
P14
RX1
D
P15
98
TX1
SGO
D
1 to 4
5 to 8
SGA
P20 to P23
P24 to P27
INT4 to INT7
Outputs for the Output Compares.
To enable the signal outputs, the corresponding bits of the Port Direction registers should be set to “1”.
General purpose I/O
RX input for CAN Interface 1
TX output for CAN Interface 1.
To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.
General purpose I/O
D
P17
100
Inputs for the Input Captures
General purpose I/O
P16
99
General purpose I/O
General purpose I/O
OUT0 to OUT5
97
Function
SGO output for the Sound Generator.
To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.
General purpose I/O
D
SGA output for the Sound Generator.
To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.
D
General purpose I/O
D
General purpose I/O
External interrupt input for INT4 to INT7
9 to 10
P30 to P31
D
General purpose I/O
12 to 13
P32 to P33
D
General purpose I/O
P34
14
SOT0
General purpose I/O
D
P35
15
SCK0
SOT output for UART 0.
To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.
General purpose I/O
D
SCK input/output for UART 0.
To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.
(Continued)
7
MB90590/590G Series
No.
16
17
18
19
20
21
22
24
25
26
Pin name
P36
SIN0
P37
SIN1
P40
SCK1
P41
SOT1
P42
SOT2
P43
SCK2
P44
SIN2
P45
SIN3
P46
SCK3
P47
SOT3
Circuit type
D
D
D
D
D
D
D
D
D
D
P50 to P55
28 to 33
38 to 41
43 to 46
47
PPG0 to
PPG5,
ADTG
P60 to P63
AN0 to AN3
P64 to P67
AN4 to AN7
P56
TIN
TOT/WOT
General purpose I/O
SIN input for UART 0
General purpose I/O
SIN input for UART 1
General purpose I/O
SCK input/output for UART 1
General purpose I/O
SOT output for UART 1
General purpose I/O
SOT output for UART 2
General purpose I/O
SCK input/output for UART 2
General purpose I/O
SIN input for UART 2
General purpose I/O
SIN input for the Serial I/O
General purpose I/O
SCK input/output for the Serial I/O
General purpose I/O
SOT output for the Serial I/O
General purpose I/O
D
E
E
D
P57
48
Function
Outputs for the Programmable Pulse Generators.
Pin number 33 is also shared with ADTG input for the external trigger
of the A/D Converter.
General purpose I/O
Inputs for the A/D Converter
General purpose I/O
Inputs for the A/D Converter
General purpose I/O
TIN input for the 16-bit Reload Timers
General purpose I/O
D
TOT output for the 16-bit Reload Timers and WOT output for the
Watch Timer. Only one of three output enable flags in these peripheral blocks can be set at a time. Otherwise the output signal has no
meaning.
(Continued)
8
MB90590/590G Series
No.
Pin name
Circuit type
P70 to P73
54 to 57
PWM1P0,
PWM1M0,
PWM2P0,
PWM2M0
General purpose I/O
F
P74 to P77
59 to 62
PWM1P1,
PWM1M1,
PWM2P1,
PWM2M1
PWM1P2,
PWM1M2,
PWM2P2,
PWM2M2
F
74
75
76
78
79
80
PWM1P3,
PWM1M3,
PWM2P3,
PWM2M3
P90
TX0
P91
RX0
P92
INT0
P93
INT1
P94
INT2
P95
INT3
Output for Stepping Motor Controller channel 1.
General purpose I/O
F
P84 to P87
69 to 72
Output for Stepping Motor Controller channel 0.
General purpose I/O
P80 to P83
64 to 67
Function
Output for Stepping Motor Controller channel 2.
General purpose I/O
F
D
D
D
D
D
D
Output for Stepping Motor Controller channel 3.
General purpose I/O
TX output for CAN Interface 0
General purpose I/O
RX input for CAN Interface 0
General purpose I/O
External interrupt input for INT0
General purpose I/O
External interrupt input for INT1
General purpose I/O
External interrupt input for INT2
General purpose I/O
External interrupt input for INT3
58, 68
DVCC
Dedicated power supply pins for the high current output buffers
(Pin No. 54 to 72)
53, 63, 73
DVSS
Dedicated ground pins for the high current output buffers
(Pin No. 54 to 72)
34
AVCC
Power
supply
Power supply for analog circuit pin
When turning this power supply on or off, always be sure to first apply
electric potential equal to or greater than AVCC to VCC.
37
AVSS
Power
supply
Ground level for analog circuit
(Continued)
9
MB90590/590G Series
10
(Continued)
No.
Pin name
Circuit type
Function
35
AVRH
Power
supply
Reference voltage input pin for analog circuit
When turning this power supply on or off, always be sure to first apply
electric potential equal to or greater than AVRH to AVCC.
36
AVRL
Power
supply
Reference voltage input pin for analog circuit
49, 50
MD0, MD1
C
Operating mode selection input pins
Connect directly to VCC or VSS.
51
MD2
G
Operating mode selection input pin
Connect directly to VCC or VSS.
27
C
This is the power supply stabilization capacitor pin. It should be connected externally to an 0.1 µF ceramic capacitor.
23, 84
VCC
Power
supply
Power supply (5.0 V) input pin for digital circuit
11,42,81
VSS
Power
supply
Power supply (GND) input pin for digital circuit
MB90590/590G Series
■ I/O CIRCUIT TYPE
Circuit Type
Circuit
Remarks
X1
Clock
Input
• Oscillation feedback resistor :
1 MΩ approx.
X0
A
HARD,SOFT
STANDBY
CONTROL
• Hysteresis input with pull-up resistor :
50 kΩ approx.
B
R (pull-up)
R
HYS
• Hysteresis input
C
R
HYS
• CMOS output
• Hysteresis input
VCC
P-ch
N-ch
D
R
HYS
(Continued)
11
MB90590/590G Series
(Continued)
Circuit Type
Circuit
Remarks
• CMOS output
• Hysteresis input
• Analog input
Vcc
P-ch
N-ch
E
P-ch
Analog input
N-ch
HYS
R
• CMOS high current output
• Hysteresis input
P-ch
High current
N-ch
F
R
R
G
12
R (pull-down)
HYS
HYS
• Hysteresis input with pull-down resistor :
50 kΩ approx.
• Flash version does not have pull-down
resistor.
MB90590/590G Series
■ HANDLING DEVICES
(1) Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than Vcc or lower than Vss is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between Vcc and Vss.
• The AVcc power supply is applied before the Vcc voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital
power-supply voltage.
(2) Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefor they must be pulled up or pulled down through resistors. In this case those resistors should be
more than 2 kΩ.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
(3) Using external clock
To use external clock, drive X0 pin only and leave X1 pin unconnected.
Below is a diagram of how to use external clock.
MB90590/590G Series
X0
X1
Using external clock
13
MB90590/590G Series
(4)Power supply pins (Vcc/Vss)
In products with multiple VCC or VSS pins, pins with the same potential are internally connected in the device to
avoid abnormal operations including latch-up. However, you must connect the pins to an external power and a
ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused
by the rise in the ground level, and to conform to the total current rating.
Make sure to connect VCC and VSS pins via lowest impedance to power lines.
It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pin near the device.
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90590/590G
Vcc
Series
Vss
Vss
Vcc
(5) Pull-up/down resistors
The MB90590/590G Series does not support internal pull-up/down resistors. Use external components where
needed.
(6) Crystal Oscillator Circuit
Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via the
shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure
that lines of oscillation circuits do not cross the lines of other circuits.
A printed circuit board artwork surrounding the X0 and X1 pins with a ground area for stabilizing the operation
is highly recommended.
(7) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after
turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
(8) Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.
14
MB90590/590G Series
(9) N.C. Pin
The N.C. (internally connected) pin must be opened for use.
(10) Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 µs or more (0.2 V to 2.7 V).
(11) Indeterminate outputs from ports 0 and 1 (without MB90F591G/591G, MB90F594G)
During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the
outputs from ports 0 and 1 become following state.
• If RST pin is “H”, the outputs become indeterminate.
• If RST pin is “L”, the outputs become high-impedance.
Pay attention to the port output timing shown as follow.
Oscillation setting time*2
RST pin is “H”
Power-on reset*1
Vcc (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal
Period of indeterminated
*1 : Power-on reset time : Period of “clock frequency × 217” (Clock frequency of 16 MHz : 8.19 ms)
*2 : Oscillation setting time : Period of “clock frequency × 218” (Clock frequency of 16 MHz : 16.38ms)
Oscillation setting time∗2
RST pin is “L”
Power-on reset∗1
Vcc (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal
High-impedance
*1 : Power-on reset time : Period of “clock frequency × 217” (Clock frequency of 16 MHz : 8.19 ms)
*2 : Oscillation setting time : Period of “clock frequency × 218” (Clock frequency of 16 MHz : 16.38ms)
15
MB90590/590G Series
(12) Initialization
The device contains internal registers which are initialized only by a power-on reset. To initialize these registers,
please turn on the power again.
(13) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions
In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”), the value of the corresponding bank register (DTB, ADB, USB, SSB) is set in “00 H”.
If the values of the corresponding bank registers (DTB,ADB,USB,SSB) are set to other than “00 H”, the remainder
by the execution result of the instruction is not stored in the register of the instruction operand.
(14) Using REALOS
The use of EI2OS is not possible with the REALOS real time operating system.
(15) Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected in the microcontroller, it may attempt to continue the operation using the freerunning frequency of the automatic oscillating circuit in the PLL circuitry even if the oscillator is out of place or
the clock input is stopped. Performance of this operation, however, cannot be guaranteed.
16
MB90590/590G Series
■ BLOCK DIAGRAM
X0,X1
RST
HST
Clock
Controller
F2MC-16LX
CPU
16-bit
I/O Timer
RAM 6/8 K
16-bit Input
Capture
6ch
IN0 to IN5
16-bit Output
Compare
4ch
OUT0 to OUT5
8/16-bit
PPG
6ch
PPG0 to PPG5
ROM/Flash
256 K/384 K
Prescaler × 3
SOT0 to SOT2
SCK0 to SCK2
SIN0 to SIN2
UART 3ch
CAN
2ch
Prescaler
AVCC
AVSS
AN0 to AN7
AVRH
AVRL
ADTG
TIN
TOT/WOT
Serial I/O
PWM1M0 to PWM1M3
10-bit ADC
8ch
16-bit Reload
Timer 2ch
F2MC-16 Bus
SOT3
SCK3
SIN3
RX0, RX1
TX0, TX1
SMC
4ch
PWM1P0 to PWM1P3
PWM2M0 to PWM2M3
PWM2P0 to PWM2P3
DVCC
DVSS
External
Interrupt
Circuit 8ch
Sound
Generator
INT0 to INT7
SGO
SGA
Watch
Timer
17
MB90590/590G Series
■ MEMORY SPACE
The memory space of the MB90590/590G Series is shown below
MB90594/F594A/
594G/F594G
MB90V590A/V590G
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
00FFFFH
004000H
0028FFH
002100H
0020FFH
001FFFH
001900H
0018FFH
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM
(Image of FF bank)
00FFFFH
004000H
ROM
(Image of FF bank)
Peripheral
000100H
001FFFH
001900H
0018FFH
Peripheral
00FFFFH
004000H
001FFFH
001900H
0018FFH
RAM 6K
000100H
Peripheral
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
0028FFH
002100H
0020FFH
RAM 2K
RAM 6K
0000BFH
000000H
ROM (FF bank)
MB90591/F591A/
591G/F591G
0000BFH
000000H
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM
(Image of FF bank)
RAM 2K
Peripheral
RAM 6K
000100H
Peripheral
0000BFH
000000H
Peripheral
Memory space map
Note : The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C
compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same
address, enabling reference of the table on the ROM without stating “far”.
For example, if an attempt has been made to access 00C000H , the contents of the ROM at FFC000H are
accessed. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the
image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for
004000H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to
FFFFFFH.
18
MB90590/590G Series
■ I/O MAP
Address
Register
Peripheral
Initial value
00H
Port 0 Data Register
PDR0
R/W
Port 0
XXXXXXXXB
01H
Port 1 Data Register
PDR1
R/W
Port 1
XXXXXXXXB
02H
Port 2 Data Register
PDR2
R/W
Port 2
XXXXXXXXB
03H
Port 3 Data Register
PDR3
R/W
Port 3
XXXXXXXXB
04H
Port 4 Data Register
PDR4
R/W
Port 4
XXXXXXXXB
05H
Port 5 Data Register
PDR5
R/W
Port 5
XXXXXXXXB
06H
Port 6 Data Register
PDR6
R/W
Port 6
XXXXXXXXB
07H
Port 7 Data Register
PDR7
R/W
Port 7
XXXXXXXXB
08H
Port 8 Data Register
PDR8
R/W
Port 8
XXXXXXXXB
09H
Port 9 Data Register
PDR9
R/W
Port 9
_ _ XXXXXXB
0AH to 0FH
Abbreviation Access
Reserved
10H
Port 0 Direction Register
DDR0
R/W
Port 0
0 0 0 0 0 0 0 0B
11H
Port 1 Direction Register
DDR1
R/W
Port 1
0 0 0 0 0 0 0 0B
12H
Port 2 Direction Register
DDR2
R/W
Port 2
0 0 0 0 0 0 0 0B
13H
Port 3 Direction Register
DDR3
R/W
Port 3
0 0 0 0 0 0 0 0B
14H
Port 4 Direction Register
DDR4
R/W
Port 4
0 0 0 0 0 0 0 0B
15H
Port 5 Direction Register
DDR5
R/W
Port 5
0 0 0 0 0 0 0 0B
16H
Port 6 Direction Register
DDR6
R/W
Port 6
0 0 0 0 0 0 0 0B
17H
Port 7 Direction Register
DDR7
R/W
Port 7
0 0 0 0 0 0 0 0B
18H
Port 8 Direction Register
DDR8
R/W
Port 8
0 0 0 0 0 0 0 0B
19H
Port 9 Direction Register
DDR9
R/W
Port 9
_ _ 0 0 0 0 0 0B
Port 6, A/D
1 1 1 1 1 1 1 1B
1AH
1BH
Reserved
Analog Input Enable Register
1CH to 1FH
ADER
R/W
Reserved
20H
Serial Mode Control Register 0
UMC0
R/W
21H
Serial Status Register 0
USR0
R/W
0 0 0 0 0 1 0 0B
0 0 0 1 0 0 0 0B
UART0
22H
Serial Input/Output Data Register 0
UIDR0/
UODR0
R/W
23H
Rate and Data Register 0
URD0
R/W
0 0 0 0 0 0 0XB
24H
Serial Mode Control Register 1
UMC1
R/W
0 0 0 0 0 1 0 0B
25H
Serial Status Register 1
USR1
R/W
26H
Serial Input/Output Data Register 1
UIDR1/
UODR1
R/W
27H
Rate and Data Register 1
URD1
R/W
XXXXXXXXB
0 0 0 1 0 0 0 0B
UART1
XXXXXXXXB
0 0 0 0 0 0 0XB
(Continued)
19
MB90590/590G Series
Address
Register
28H
Serial Mode Control Register 2
UMC2
R/W
0 0 0 0 0 1 0 0B
29H
Serial Status Register 2
USR2
R/W
0 0 0 1 0 0 0 0B
2AH
Serial Input/Output Data
Register 2
UIDR2/
UODR2
R/W
2BH
Rate and Data Register 2
URD2
R/W
0 0 0 0 0 0 0XB
2CH
Serial Mode Control Register
(low-order)
SMCS
R/W
_ _ _ _0 0 0 0B
2DH
Serial Mode Control Register
(high-order)
SMCS
R/W
2EH
Serial Data Register
SDR
R/W
XXXXXXXXB
2FH
Edge Selector Register
SES
R/W
_ _ _ _ _ _ _0B
30H
External Interrupt Enable Register
ENIR
R/W
0 0 0 0 0 0 0 0B
31H
External Interrupt Request Register
EIRR
R/W
32H
External Interrupt Level Register
ELVR
R/W
33H
External Interrupt Level Register
ELVR
R/W
0 0 0 0 0 0 0 0B
34H
A/D Control Status Register 0
ADCS0
R/W
0 0 0 0 0 0 0 0B
35H
A/D Control Status Register 1
ADCS1
R/W
36H
A/D Data Register 0
ADCR0
R
37H
A/D Data Register 1
ADCR1
R/W
0 0 0 0 1 0 XXB
38H
PPG0 Operation Mode Control Register
PPGC0
R/W
39H
PPG1 Operation Mode Control Register
PPGC1
R/W
3AH
PPG0,1 Output Pin Control Register
PPG01
R/W
16-bit Programmable 0 _ 0 0 0 _ _ 1B
0 _ 0 0 0 0 0 1B
Pulse
Generator 0/1
0 0 0 0 0 0 0 0B
3BH
Abbreviation Access
UART2
Serial I/O
External Interrupt
A/D Converter
Initial value
XXXXXXXXB
0 0 0 0 0 0 1 0B
XXXXXXXXB
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XXXXXXXXB
Reserved
3CH
PPG2 Operation Mode Control Register
PPGC2
R/W
3DH
PPG3 Operation Mode Control Register
PPGC3
R/W
3EH
PPG2,3 Output Pin Control Register
PPG23
R/W
3FH
0 _ 0 0 0 _ _1B
16-bit Programmable
Pulse
0 _ 0 0 0 0 0 1B
Generator 2/3
0 0 0 0 0 0 0 0B
Reserved
40H
PPG4 Operation Mode Control Register
PPGC4
R/W
41H
PPG5 Operation Mode Control Register
PPGC5
R/W
42H
PPG4,5 Output Pin Control Register
PPG45
R/W
43H
0 _ 0 0 0 _ _ 1B
16-bit Programmable
Pulse
0 _ 0 0 0 0 0 1B
Generator 4/5
0 0 0 0 0 0 0 0B
Reserved
44H
PPG6 Operation Mode Control Register
PPGC6
R/W
45H
PPG7 Operation Mode Control Register
PPGC7
R/W
46H
PPG6,7 Output Pin Control Register
PPG67
R/W
47H
Peripheral
16-bit Programmable 0 _ 0 0 0 _ _ 1B
0 _ 0 0 0 0 0 1B
Pulse
Generator 6/7
0 0 0 0 0 0 0 0B
Reserved
(Continued)
20
MB90590/590G Series
Address
Register
48H
PPG8 Operation Mode Control Register
PPGC8
R/W
49H
PPG9 Operation Mode Control Register
PPGC9
R/W
4AH
PPG8,9 Output Pin Control Register
PPG89
R/W
4BH
Abbreviation Access
Peripheral
Initial value
0 _ 0 0 0 _ _ 1B
16-bit Programmable
Pulse
0 _ 0 0 0 0 0 1B
Generator 8/9
0 0 0 0 0 0 0 0B
Reserved
4CH
PPGA Operation Mode Control Register
PPGCA
R/W
4DH
PPGB Operation Mode Control Register
PPGCB
R/W
4EH
PPGA,B Output Pin Control Register
PPGAB
R/W
4FH
0 _ 0 0 0 _ _ 1B
16-bit Programmable
Pulse
0 _ 0 0 0 0 0 1B
Generator A/B
0 0 0 0 0 0 0 0B
Reserved
Timer Control Status Register 0
(low-order)
TMCSR0
51H
Timer Control Status Register 0
(high-order)
TMCSR0
R/W
52H
Timer Control Status Register 1
(low-order)
TMCSR1
R/W
53H
Timer Control Status Register 1
(high-order)
TMCSR1
R/W
54H
Input Capture Control Status
Register 0/1
ICS01
R/W
Input Capture 0/1
0 0 0 0 0 0 0 0B
55H
Input Capture Control Status
Register 2/3
ICS23
R/W
Input Capture 2/3
0 0 0 0 0 0 0 0B
56H
Input Capture Control Status
Register 4/5
ICS45
R/W
Input Capture 4/5
0 0 0 0 0 0 0 0B
50H
57H
R/W
0 0 0 0 0 0 0 0B
16-bit Reload Timer 0
_ _ _ _ 0 0 0 0B
0 0 0 0 0 0 0 0B
16-bit Reload Timer 1
_ _ _ _ 0 0 0 0B
Reserved
58H
Output Compare Control Status
Register 0
OCS0
R/W
59H
Output Compare Control Status
Register 1
OCS1
R/W
5AH
Output Compare Control Status
Register 2
OCS2
R/W
5BH
Output Compare Control Status
Register 3
OCS3
R/W
_ _ _ 0 0 0 0 0B
5CH
Output Compare Control Status
Register 4
OCS4
R/W
0 0 0 0 _ _ 0 0B
5DH
Output Compare Control Status
Register 5
OCS5
R/W
5EH
Sound Control Register (low-order)
SGCR
R/W
5FH
Sound Control Register (high-order)
SGCR
R/W
0 0 0 0 _ _ 0 0B
Output Compare 0/1
_ _ _0 0 0 0 0B
0 0 0 0 _ _ 0 0B
Output Compare 2/3
Output Compare 4/5
_ _ _ 0 0 0 0 0B
Sound Generator
0 0 0 0 0 0 0 0B
0 _ _ _ _ _ _ 0B
(Continued)
21
MB90590/590G Series
Address
Register
Abbreviation Access
60H
Watch Timer Control Register
(low-order)
WTCR
61H
Watch Timer Control Register
(high-order)
WTCR
R/W
62H
PWM Control Register 0
PWC0
R/W
PWM Control Register 1
PWC1
0 0 0 0 0 0 0 0B
Stepping Motor
Controller 0
0 0 0 0 0 _ _ 0B
R/W
Stepping Motor
Controller 1
0 0 0 0 0 _ _ 0B
Stepping Motor
Controller 2
0 0 0 0 0 _ _ 0B
Stepping Motor
Controller 3
0 0 0 0 0 _ _ 0B
Reserved
PWM Control Register 2
PWC2
67H
68H
0 0 0 _ _ 0 0 0B
Reserved
65H
66H
R/W
Initial value
Watch Timer
63H
64H
Peripheral
R/W
Reserved
PWM Control Register 3
PWC3
69H to 6CH
R/W
Reserved
6DH
Serial I/O Prescaler Register
CDCR
R/W
Prescaler (Serial I/O)
0 XXX 1 1 1 1B
6EH
Timer Control Status Register
TCCS
R/W
I/O Timer
0 0 0 0 0 0 0 0B
6FH
ROM Mirror Function Select
Register
ROMM
W
ROM Mirror
XXXXXXX1B
70H to 8FH
Reserved for CAN Interface 0/1. Refer to section about CAN Controller
90H to 9DH
Reserved
9EH
Program Address Detection
Control Status Register
PACSR
R/W
Address Match
Detection Function
0 0 0 0 0 0 0 0B
9FH
Delayed Interrupt/Release Register
DIRR
R/W
Delayed Interrupt
_ _ _ _ _ _ _ 0B
A0H
Low Power Mode Control Register
LPMCR
R/W
Low Power Controller
0 0 0 1 1 0 0 0B
A1H
Clock Selection Register
CKSCR
R/W
Low Power Controller
1 1 1 1 1 1 0 0B
A2H to A7H
Reserved
A8H
Watchdog Timer Control Register
WDTC
R/W
Watchdog Timer
XXXXX 1 1 1B
A9H
Time Base Timer Control Register
TBTC
R/W
Time Base Timer
1 - - 0 0 1 0 0B
Flash Memory
0 0 0 X 0 0 0 0B
AAH to ADH
AEH
AFH
Reserved
Flash Memory Control Status
Register
(Flash product only.
Otherwise reserved)
FMCS
R/W
Reserved
(Continued)
22
MB90590/590G Series
Address
Register
Abbreviation
Access
B0H
Interrupt Control Register 00
ICR00
R/W
0 0 0 0 0 1 1 1B
B1H
Interrupt Control Register 01
ICR01
R/W
0 0 0 0 0 1 1 1B
B2H
Interrupt Control Register 02
ICR02
R/W
0 0 0 0 0 1 1 1B
B3H
Interrupt Control Register 03
ICR03
R/W
0 0 0 0 0 1 1 1B
B4H
Interrupt Control Register 04
ICR04
R/W
0 0 0 0 0 1 1 1B
B5H
Interrupt Control Register 05
ICR05
R/W
0 0 0 0 0 1 1 1B
B6H
Interrupt Control Register 06
ICR06
R/W
0 0 0 0 0 1 1 1B
B7H
Interrupt Control Register 07
ICR07
R/W
B8H
Interrupt Control Register 08
ICR08
R/W
B9H
Interrupt Control Register 09
ICR09
R/W
0 0 0 0 0 1 1 1B
BAH
Interrupt Control Register 10
ICR10
R/W
0 0 0 0 0 1 1 1B
BBH
Interrupt Control Register 11
ICR11
R/W
0 0 0 0 0 1 1 1B
BCH
Interrupt Control Register 12
ICR12
R/W
0 0 0 0 0 1 1 1B
BDH
Interrupt Control Register 13
ICR13
R/W
0 0 0 0 0 1 1 1B
BEH
Interrupt Control Register 14
ICR14
R/W
0 0 0 0 0 1 1 1B
BFH
Interrupt Control Register 15
ICR15
R/W
0 0 0 0 0 1 1 1B
C0H to
FFH
Peripheral
Interrupt controller
Initial value
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
Reserved
1900H
Reload L Register
PRLL0
R/W
1901H
Reload H Register
PRLH0
R/W
1902H
Reload L Register
PRLL1
R/W
1903H
Reload H Register
PRLH1
R/W
XXXXXXXXB
1904H
Reload L Register
PRLL2
R/W
XXXXXXXXB
1905H
Reload H Register
PRLH2
R/W
1906H
Reload L Register
PRLL3
R/W
1907H
Reload H Register
PRLH3
R/W
XXXXXXXXB
1908H
Reload L Register
PRLL4
R/W
XXXXXXXXB
1909H
Reload H Register
PRLH4
R/W
190AH
Reload L Register
PRLL5
R/W
190BH
Reload H Register
PRLH5
R/W
XXXXXXXXB
190CH
Reload L Register
PRLL6
R/W
XXXXXXXXB
190DH
Reload H Register
PRLH6
R/W
190EH
Reload L Register
PRLL7
R/W
190FH
Reload H Register
PRLH7
R/W
XXXXXXXXB
16-bit Programmable
Pulse
Generator 0/1
16-bit Programmable
Pulse
Generator 2/3
16-bit Programmable
Pulse
Generator 4/5
16-bit Programmable
Pulse
Generator 6/7
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
23
MB90590/590G Series
Address
Register
Abbreviation Access
1910H
Reload L Register
PRLL8
R/W
1911H
Reload H Register
PRLH8
R/W
1912H
Reload L Register
PRLL9
R/W
1913H
Reload H Register
PRLH9
R/W
XXXXXXXXB
1914H
Reload L Register
PRLLA
R/W
XXXXXXXXB
1915H
Reload H Register
PRLHA
R/W
1916H
Reload L Register
PRLLB
R/W
1917H
Reload H Register
PRLHB
R/W
1918H to 191FH
Peripheral
Initial value
XXXXXXXXB
16-bit Programmable
Pulse
Generator 8/9
16-bit Programmable
Pulse
Generator A/B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reserved
1920H
Input Capture Register 0
(low-order)
IPCP0
R
XXXXXXXXB
1921H
Input Capture Register 0
(high-order)
IPCP0
R
XXXXXXXXB
1922H
Input Capture Register 1
(low-order)
IPCP1
R
XXXXXXXXB
1923H
Input Capture Register 1
(high-order)
IPCP1
R
XXXXXXXXB
1924H
Input Capture Register 2
(low-order)
IPCP2
R
XXXXXXXXB
1925H
Input Capture Register 2
(high-order)
IPCP2
R
XXXXXXXXB
1926H
Input Capture Register 3
(low-order)
IPCP3
R
XXXXXXXXB
1927H
Input Capture Register 3
(high-order)
IPCP3
R
XXXXXXXXB
1928H
Input Capture Register 4
(low-order)
IPCP4
R
XXXXXXXXB
1929H
Input Capture Register 4
(high-order)
IPCP4
R
XXXXXXXXB
192AH
Input Capture Register 5
(low-order)
IPCP5
R
XXXXXXXXB
192BH
Input Capture Register 5
(high-order)
IPCP5
R
XXXXXXXXB
192CH to 192FH
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
Reserved
(Continued)
24
MB90590/590G Series
Address
Register
Abbreviation
Access
1930H
Output Compare Register 0
(low-order)
OCCP0
R/W
1931H
Output Compare Register 0
(high-order)
OCCP0
R/W
1932H
Output Compare Register 1
(low-order)
OCCP1
R/W
1933H
Output Compare Register 1
(high-order)
OCCP1
R/W
XXXXXXXXB
1934H
Output Compare Register 2
(low-order)
OCCP2
R/W
XXXXXXXXB
1935H
Output Compare Register 2
(high-order)
OCCP2
R/W
1936H
Output Compare Register 3
(low-order)
OCCP3
R/W
1937H
Output Compare Register 3
(high-order)
OCCP3
R/W
XXXXXXXXB
1938H
Output Compare Register 4
(low-order)
OCCP4
R/W
XXXXXXXXB
1939H
Output Compare Register 4
(high-order)
OCCP4
R/W
193AH
Output Compare Register 5
(low-order)
OCCP5
R/W
193BH
Output Compare Register 5
(high-order)
OCCP5
R/W
193CH to 193FH
Peripheral
Initial value
XXXXXXXXB
Output Compare
0/1
Output Compare
2/3
Output Compare
4/5
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reserved
1940H
Timer 0/Reload Register 0
(low-order)
TMR0/
TMRLR0
R/W
1941H
Timer 0/Reload Register 0
(high-order)
TMR0/
TMRLR0
R/W
1942H
Timer 1/Reload Register 1
(low-order)
TMR1/
TMRLR1
R/W
1943H
Timer 1/Reload Register 1
(high-order)
TMR1/
TMRLR1
R/W
1944H
Timer Data Register (low-order)
TCDT
R/W
1945H
Timer Data Register (high-order)
TCDT
R/W
1946H
Frequency Data Register
SGFR
R/W
1947H
Amplitude Data Register
SGAR
R/W
1948H
Decrement Grade Register
SGDR
R/W
1949H
Tone Count Register
SGTR
R/W
16-bit Reload
Timer 0
16-bit Reload
Timer 1
I/O Timer
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
XXXXXXXXB
Sound Generator
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
25
MB90590/590G Series
Address
Register
Abbreviation
Access
Peripheral
Initial value
194AH
Sub-second Data Register
(low-order)
WTBR
R/W
194BH
Sub-second Data Register
(middle-order)
WTBR
R/W
194CH
Sub-second Data Register
(high-order)
WTBR
R/W
_ _ _ XXXXXB
194DH
Second Data Register
WTSR
R/W
__000000B
194EH
Minute Data Register
WTMR
R/W
194FH
Hour Data Register
WTHR
R/W
1950H
PWM1 Compare Register 0
PWC10
R/W
1951H
PWM2 Compare Register 0
PWC20
R/W
1952H
PWM1 Select Register 0
PWS10
R/W
1953H
PWM2 Select Register 0
PWS20
R/W
_0000000B
1954H
PWM1 Compare Register 1
PWC11
R/W
XXXXXXXXB
1955H
PWM2 Compare Register 1
PWC21
R/W
1956H
PWM1 Select Register 1
PWS11
R/W
1957H
PWM2 Select Register 1
PWS21
R/W
_0000000B
1958H
PWM1 Compare Register 2
PWC12
R/W
XXXXXXXXB
1959H
PWM2 Compare Register 2
PWC22
R/W
195AH
PWM1 Select Register 2
PWS12
R/W
195BH
PWM2 Select Register 2
PWS22
R/W
_0000000B
195CH
PWM1 Compare Register 3
PWC13
R/W
XXXXXXXXB
195DH
PWM2 Compare Register 3
PWC23
R/W
195EH
PWM1 Select Register 3
PWS13
R/W
195FH
PWM2 Select Register 3
PWS23
R/W
XXXXXXXXB
Watch Timer
Watch Timer
XXXXXXXXB
__000000B
___00000B
XXXXXXXXB
Stepping Motor
Controller 0
Stepping Motor
Controller 1
Stepping Motor
Controller 2
Stepping Motor
Controller 3
XXXXXXXXB
__000000B
XXXXXXXXB
__000000B
XXXXXXXXB
__000000B
XXXXXXXXB
__000000B
_0 0 0 0 0 0 0 B
1960H to 19FFH
Reserved
1A00H to 1AFFH
Reserved for CAN Interface 0. Refer to section about CAN Controller
1B00H to 1BFFH
Reserved for CAN Interface 1. Refer to section about CAN Controller
1C00H to 1CFFH
Reserved for CAN Interface 0. Refer to section about CAN Controller
1D00H to 1DFFH
Reserved for CAN Interface 1. Refer to section about CAN Controller
1E00H to 1EFFH
Reserved
(Continued)
26
MB90590/590G Series
(Continued)
Address
Register
Abbreviation
Access
1FF0H
Program Address Detection
Register 0 (low-order)
PADR0
R/W
XXXXXXXX B
1FF1H
Program Address Detection
Register 0 (middle-order)
PADR0
R/W
XXXXXXXX B
1FF2H
Program Address Detection
Register 0 (high-order)
PADR0
R/W
1FF3H
Program Address Detection
Register 1 (low-order)
PADR1
R/W
1FF4H
Program Address Detection
Register 1 (middle-order)
PADR1
R/W
XXXXXXXX B
1FF5H
Program Address Detection
Register 1 (high-order)
PADR1
R/W
XXXXXXXX B
1FF6H to 1FFFH
Peripheral
Address Match
Detection
Function
Initial value
XXXXXXXX B
XXXXXXXX B
Reserved
Note : Initial value of “_” represents unused bit; “X” represents unknown value.
Addresses in the rage 0000H to 00FFH, which are not listed in the table, are reserved for the primary functions
of the MCU. A read access to these reserved addresses results in reading “X”, and any write access should
not be performed.
27
MB90590/590G Series
■ CAN CONTROLLERS
The CAN controller has the following features : Conforms to CAN Specification Version 2.0 Part A and B
- Supports transmission/reception in standard frame and extended frame formats
• Supports transmission of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
- 29-bit ID and 8-byte data
- Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as 1D acceptance mask
- Two acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 Kbit/s to 2 Mbit/s (when input clock is at 16 MHz)
List of Control Registers
Address
28
CAN0
CAN1
000070H
000080H
000071H
000081H
000072H
000082H
000073H
000083H
000074H
000084H
000075H
000085H
000076H
000086H
000077H
000087H
000078H
000088H
000079H
000089H
00007AH
00008AH
00007BH
00008BH
00007CH
00008CH
00007DH
00008DH
00007EH
00008EH
00007FH
00008FH
Register
Abbreviation
Access
Initial Value
Message buffer valid register
BVALR
R/W
00000000 00000000B
Transmit request register
TREQR
R/W
00000000 00000000B
Transmit cancel register
TCANR
W
00000000 00000000B
Transmit complete register
TCR
R/W
00000000 00000000B
Receive complete register
RCR
R/W
00000000 00000000B
Remote request receiving register
RRTRR
R/W
00000000 00000000B
Receive overrun register
ROVRR
R/W
00000000 00000000B
RIER
R/W
00000000 00000000B
Receive interrupt enable register
MB90590/590G Series
List of Control Registers
Address
CAN0
CAN1
001C00H
001D00H
001C01H
001D01H
001C02H
001D02H
001C03H
001D03H
001C04H
001D04H
001C05H
001D05H
001C06H
001D06H
001C07H
001D07H
001C08H
001D08H
001C09H
001D09H
001C0AH 001D0AH
001C0BH 001D0BH
001C0CH 001D0CH
001C0DH 001D0DH
001C0EH 001D0EH
001C0FH
001D0FH
001C10H
001D10H
001C11H
001D11H
001C12H
001D12H
001C13H
001D13H
001C14H
001D14H
001C15H
001D15H
001C16H
001D16H
001C17H
001D17H
001C18H
001D18H
001C19H
001D19H
001C1AH 001D1AH
001C1BH 001D1BH
Register
Abbreviation Access
Initial Value
Control status register
CSR
R/W, R
00---000 0----0-1B
Last event indicator register
LEIR
R/W
-------- 000-0000B
Receive/transmit error counter
RTEC
R
00000000 00000000B
Bit timing register
BTR
R/W
-1111111 11111111B
IDE register
IDER
R/W
XXXXXXXX
XXXXXXXXB
Transmit RTR register
TRTRR
R/W
00000000 00000000B
Remote frame receive waiting register
RFWTR
R/W
XXXXXXXX
XXXXXXXXB
TIER
R/W
00000000 00000000B
Transmit interrupt enable register
XXXXXXXX
XXXXXXXXB
Acceptance mask select register
AMSR
R/W
XXXXXXXX
XXXXXXXXB
XXXXXXXX
XXXXXXXXB
Acceptance mask register 0
AMR0
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX
XXXXXXXXB
Acceptance mask register 1
AMR1
R/W
XXXXX--- XXXXXXXXB
29
MB90590/590G Series
List of Message Buffers (ID Registers)
Address
CAN0
CAN1
001A20H
001B20H
001A21H
001B21H
001A22H
001B22H
001A23H
001B23H
001A24H
001B24H
001A25H
001B25H
001A26H
001B26H
001A27H
001B27H
001A28H
001B28H
001A29H
001B29H
001A2AH
001B2AH
001A2BH
001B2BH
001A2CH
001B2CH
001A2DH
001B2DH
001A2EH
001B2EH
001A2FH
001B2FH
001A30H
001B30H
001A31H
001B31H
001A32H
001B32H
001A33H
001B33H
001A34H
001B34H
001A35H
001B35H
001A36H
001B36H
001A37H
001B37H
001A38H
001B38H
001A39H
001B39H
001A3AH
001B3AH
001A3BH
001B3BH
001A3CH
001B3CH
001A3DH
001B3DH
001A3EH
001B3EH
001A3FH
001B3FH
Register
Abbreviation
Access
Initial Value
XXXXXXXX XXXXXXXXB
ID register 0
IDR0
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 1
IDR1
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 2
IDR2
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 3
IDR3
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 4
IDR4
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 5
IDR5
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 6
IDR6
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 7
IDR7
R/W
XXXXX--- XXXXXXXXB
(Continued)
30
MB90590/590G Series
(Continued)
Address
CAN0
CAN1
001A40H
001B40H
001A41H
001B41H
001A42H
001B42H
001A43FH
001B43H
001A44H
001B44H
001A45H
001B45H
001A46H
001B46H
001A47H
001B47H
001A48H
001B48H
001A49H
001B49H
001A4AH
001B4AH
001A4BH
001B4BH
001A4CH
001B4CH
001A4DH
001B4DH
001A4EH
001B4EH
001A4FH
001B4FH
001A50H
001B50H
001A51H
001B51H
001A52H
001B52H
001A53H
001B53H
001A54H
001B54H
001A55H
001B55H
001A56H
001B56H
001A57H
001B57H
001A58H
001B58H
001A59H
001B59H
001A5AH
001B5AH
001A5BH
001B5BH
001A5CH
001B5CH
001A5DH
001B5DH
001A5EH
001B5EH
001A5FH
001B5FH
Register
Abbreviation
Access
Initial Value
XXXXXXXX XXXXXXXXB
ID register 8
IDR8
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 9
IDR9
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 10
IDR10
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 11
IDR11
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 12
IDR12
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 13
IDR13
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 14
IDR14
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 15
IDR15
R/W
XXXXX--- XXXXXXXXB
31
MB90590/590G Series
List of Message Buffers (DLC Registers and Data Registers)
Address
Register
Abbreviation
Access
Initial Value
DLC register 0
DLCR0
R/W
----XXXXB
DLC register 1
DLCR1
R/W
----XXXXB
DLC register 2
DLCR2
R/W
----XXXXB
DLC register 3
DLCR3
R/W
----XXXXB
DLC register 4
DLCR4
R/W
----XXXXB
DLC register 5
DLCR5
R/W
----XXXXB
DLC register 6
DLCR6
R/W
----XXXXB
DLC register 7
DLCR7
R/W
----XXXXB
DLC register 8
DLCR8
R/W
----XXXX
DLC register 9
DLCR9
R/W
----XXXXB
DLC register 10
DLCR10
R/W
----XXXXB
DLC register 11
DLCR11
R/W
----XXXXB
DLC register 12
DLCR12
R/W
----XXXXB
DLC register 13
DLCR13
R/W
----XXXXB
DLC register 14
DLCR14
R/W
----XXXXB
DLC register 15
DLCR15
R/W
----XXXXB
DTR0
R/W
XXXXXXXXB
to
XXXXXXXXB
CAN0
CAN1
001A60H
001B60H
001A61H
001B61H
001A62H
001B62H
001A63H
001B63H
001A64H
001B64H
001A65H
001B65H
001A66H
001B66H
001A67H
001B67H
001A68H
001B68H
001A69H
001B69H
001A6AH
001B6AH
001A6BH
001B6BH
001A6CH
001B6CH
001A6DH
001B6DH
001A6EH
001B6EH
001A6FH
001B6FH
001A70H
001B70H
001A71H
001B71H
001A72H
001B72H
001A73H
001B73H
001A74H
001B74H
001A75H
001B75H
001A76H
001B76H
001A77H
001B77H
001A78H
001B78H
001A79H
001B79H
001A7AH
001B7AH
001A7BH
001B7BH
001A7CH
001B7CH
001A7DH
001B7DH
001A7EH
001B7EH
001A7FH
001B7FH
001A80H
to
001A87H
001B80H
to
Data register 0 (8 bytes)
001B87H
(Continued)
32
MB90590/590G Series
(Continued)
Address
CAN0
CAN1
Register
Abbreviation
Access
Initial Value
001A88H
to
001A8FH
001B88H
to
Data register 1 (8 bytes)
001B8FH
DTR1
R/W
XXXXXXXXB
to
XXXXXXXXB
001A90H
to
001A97H
001B90H
to
Data register 2 (8 bytes)
001B97H
DTR2
R/W
XXXXXXXXB
to
XXXXXXXXB
001A98H
to
001A9FH
001B98H
to
Data register 3 (8 bytes)
001B9FH
DTR3
R/W
XXXXXXXXB
to
XXXXXXXXB
001AA0H
to
001AA7H
001BA0H
to
Data register 4 (8 bytes)
001BA7H
DTR4
R/W
XXXXXXXXB
to
XXXXXXXXB
001AA8H
to
001AAFH
001BA8H
to
Data register 5 (8 bytes)
001BAFH
DTR5
R/W
XXXXXXXXB
to
XXXXXXXXB
001AB0H
to
001AB7H
001BB0H
to
Data register 6 (8 bytes)
001BB7H
DTR6
R/W
XXXXXXXXB
to
XXXXXXXXB
001AB8H
to
001ABFH
001BB8H
to
Data register 7 (8 bytes)
001BBFH
DTR7
R/W
XXXXXXXXB
to
XXXXXXXXB
001AC0H
to
001AC7H
001BC0H
to
Data register 8 (8 bytes)
001BC7H
DTR8
R/W
XXXXXXXXB
to
XXXXXXXXB
001AC8H
to
001ACFH
001BC8H
to
Data register 9 (8 bytes)
001BCFH
DTR9
R/W
XXXXXXXXB
to
XXXXXXXXB
001AD0H
to
001AD7H
001BD0H
to
Data register 10 (8 bytes)
001BD7H
DTR10
R/W
XXXXXXXXB
to
XXXXXXXXB
001AD8H
to
001ADFH
001BD8H
to
Data register 11 (8 bytes)
001BDFH
DTR11
R/W
XXXXXXXXB
to
XXXXXXXXB
001AE0H
to
001AE7H
001BE0H
to
Data register 12 (8 bytes)
001BE7H
DTR12
R/W
XXXXXXXXB
to
XXXXXXXXB
001AE8H
to
001AEFH
001BE8H
to
Data register 13 (8 bytes)
001BEFH
DTR13
R/W
XXXXXXXXB
to
XXXXXXXXB
001AF0H
to
001AF7H
001BF0H
to
Data register 14 (8 bytes)
001BF7H
DTR14
R/W
XXXXXXXXB
to
XXXXXXXXB
001AF8H
to
001AFFH
001BF8H
to
Data register 15 (8 bytes)
001BFFH
DTR15
R/W
XXXXXXXXB
to
XXXXXXXXB
33
MB90590/590G Series
■ INTERRUPT MAP
Interrupt control register
Number
Address
Number
Address
Reset
N/A
# 08
FFFFDCH
INT9 instruction
N/A
# 09
FFFFD8H
Exception
N/A
# 10
FFFFD4H
Time Base Timer
N/A
# 11
FFFFD0H
*1
# 12
FFFFCCH
ICR00
0000B0H
CAN 0 RX
N/A
# 13
FFFFC8H
CAN 0 TX/NS
N/A
# 14
FFFFC4H
ICR01
0000B1H
CAN 1 RX
N/A
# 15
FFFFC0H
CAN 1 TX/NS
N/A
# 16
FFFFBCH
ICR02
0000B2H
8/16 bit PPG 0/1
N/A
# 17
FFFFB8H
8/16 bit PPG 2/3
N/A
# 18
FFFFB4H
ICR03
0000B3H
8/16 bit PPG 4/5
N/A
# 19
FFFFB0H
8/16 bit PPG 6/7
N/A
# 20
FFFFACH
ICR04
0000B4H
8/16 bit PPG 8/9
N/A
# 21
FFFFA8H
8/16 bit PPG A/B
N/A
# 22
FFFFA4H
ICR05
0000B5H
16-bit Reload Timer 0
*1
# 23
FFFFA0H
16-bit Reload Timer 1
*1
# 24
FFFF9CH
ICR06
0000B6H
Input Capture 0/1
*1
# 25
FFFF98H
Output compare 0/1
*1
# 26
FFFF94H
ICR07
0000B7H
Input Capture 2/3
*1
# 27
FFFF90H
Output Compare 2/3
*1
# 28
FFFF8CH
ICR08
0000B8H
Input Capture 4/5
*1
# 29
FFFF88H
Output Compare 4/5
*1
# 30
FFFF84H
ICR09
0000B9H
8/10 bit A/D Converter
*1
# 31
FFFF80H
I/O Timer/Watch Timer
N/A
# 32
FFFF7CH
ICR10
0000BAH
*1
# 33
FFFF78H
N/A
# 34
FFFF74H
ICR11
0000BBH
UART 0 RX
*2
# 35
FFFF70H
UART 0 TX
*1
# 36
FFFF6CH
ICR12
0000BCH
UART 1 RX
*2
# 37
FFFF68H
UART 1 TX
*1
# 38
FFFF64H
ICR13
0000BDH
UART 2 RX
*2
# 39
FFFF60H
UART 2 TX
*1
# 40
FFFF5CH
ICR14
0000BEH
Flash Memory
N/A
# 41
FFFF58H
Delayed interrupt
N/A
# 42
FFFF54H
ICR15
0000BFH
External Interrupt (INT0 to INT7)
Serial I/O
Sound Generator
34
Interrupt vector
I2OS
clear
Interrupt cause
MB90590/590G Series
*1 : The interrupt request flag is cleared by the I2OS interrupt clear signal.
*2 : The interrupt request flag is cleared by the I2OS interrupt clear signal. A stop request is available.
N/A : The interrupt request flag is not cleared by the I2OS interrupt clear signal.
Notes : • For a peripheral module with two interrupt for a single interrupt number, both interrupt request flags are
cleared by the I2OS interrupt clear signal.
• At the end of I2OS, the I2OS clear signal will be asserted for all the interrupt flags assigned to the same
interrupt number. If one interrupt flag starts the I2OS and in the meantime another interrupt flag is set by a
hardware event, the later event is lost because the flag is cleared by the I2OS clear signal caused by the
first event. So it is recommended not to use the I2OS for this interrupt number.
• If I2OS is enabled, I2OS is initiated when one of the two interrupt signals in the same interrupt control
register (ICR) is asserted. This means that different interrupt sources share the same I2OS Descriptor which
should be unique for each interrupt source. For this reason, when one interrupt source uses the I2OS, the
other interrupt should be disabled.
35
MB90590/590G Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V)
Parameter
Power supply voltage
Input voltage
Output voltage
Max clamp current
Total Max clamp current
“L” level Max output current
“L” level avg. output current
“L” level Max output current
“L” level avg. output current
“L” level Max overall output current
“L” level Max overall output current
Symbol
VCC
AVCC
AVRH,
AVRL
DVCC
VI
VO
ICLAMP
∑ | ICLAMP |
IOL1
IOLAV1
IOL2
IOLAV2
∑IOL1
∑IOL2
“L” level avg. overall output current
“L” level avg. overall output current
∑IOLAV1
“H” level Max output current
“H” level avg. output current
“H” level Max output current
“H” level avg. output current
“H” level Max overall output current
“H” level Max overall output current
IOH1
“H” level avg. overall output current
“H” level avg. overall output current
Power consumption
Operating temperature
Storage temperature
∑IOLAV2
IOHAV1
IOH2
IOHAV2
∑IOH1
∑IOH2
∑IOHAV1
∑IOHAV2
Rating
Unit
Min
Max
VSS − 0.3 VSS + 6.0
V
VSS − 0.3 VSS + 6.0
V
VCC = AVCC
VSS − 0.3 VSS + 6.0
V
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
−2.0
+ 2.0
—
20
—
15
—
4
—
40
—
30
—
100
330
—
50
250
—
–15
—
–4
—
–40
—
–30
—
–100
—
–330
—
–50
—
–250
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
—
500
mW
—
400
mW
–40
–55
+85
+150
°C
°C
PD
TA
TSTG
Remarks
AVCC ≥ AVRH/L, AVRH ≥ AVRL
*1
*1
VCC ≥ DVCC
Normal output
Normal output, average value
High current output
High current output, average value
Total normal output
Total high current output
Total normal output, average value
Total high current output, average value
Normal output
Normal output, average value
High current output
High current output, average value
Total normal output
Total high current output
Total normal output, average value
*2
*2
*6
*6
*3
*4
*3
*4
*5
*5
*3
*4
*3
*4
*5
*5
Total high current output, average value
MB90F594A, MB90F591A, MB90F594G,
MB90F591G
MB90594, MB90591, MB90594G,
MB90591G
*1 : AVCC, AVRH, AVRL and DVCC shall not exceed VCC. AVRH and AVRL shall not exceed AVCC.
Also, AVRL shall not exceed AVRH.
*2 : VI and VO should not exceed VCC + 0.3V. VI should not exceed the specified ratings. However if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI rating.
*3 : The maximum output current is a peak value for a corresponding pin.
*4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins.
(Continued)
36
MB90590/590G Series
*6 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 toP95
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pins does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is
provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins,
etc.) cannot accept +B signal input.
• Sample recommended circuits
• Input/Output equivalent circuits
Protective diode
VCC
P-ch
Limiting
resistance
+B input (0 V to 16 V)
N-ch
R
Note : Average output current = operating current × operating efficiency
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
37
MB90590/590G Series
2. Recommended Conditions
(VSS = AVSS = 0.0 V)
Parameter
Value
Symbol
Min
Typ
Max
4.5
5.0
5.5
Unit
Remarks
MB90V590A
Power supply voltage
VCC
AVCC
V
3.0
—
5.5
V
4.75
5.0
5.25
V
3.0
—
5.25
V
Smooth capacitor
CS
0.022
0.1
1.0
µF
Operating temperature
TA
–40
—
+85
°C
Under normal operation MB90V590G
Maintains RAM data in
stop mode
MB90F594A
MB90F594G
MB90594
MB90594G
Under normal operation MB90F591G
MB90591G
Maintains RAM data in MB90F591A
stop mode
MB90591
*
* : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be
connected to the VCC pin must have a capacitance value higher than CS.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
• C Pin Connection Diagram
C
CS
38
MB90590/590G Series
3. DC Characteristics
(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G :
VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol Pin name
Condition
Unit
Remarks
Min
Typ
Max
Input H
voltage
Input L
voltage
Output H
voltage
Output L
voltage
VIHS
CMOS hysteresis input
—
0.8 VCC
—
VCC +0.3
V
VIHM
MD input
—
VCC – 0.3
—
VCC +0.3
V
VILS
CMOS hysteresis input
—
VSS – 0.3
—
0.5VCC
V
VILM
MD input
—
VSS – 0.3
—
VSS + 0.3
V
VILR
RST, HST
—
VSS – 0.3
—
0.2VCC
V
VOH1
Normal
output
VCC – 0.5
—
—
V
VOH2
High current VCC = 4.5 V,
output
IOH2 = –30.0 mA
VCC – 0.5
—
—
V
VOL1
Normal
output
—
—
0.4
V
VOL2
High current VCC = 4.5 V,
output
IOL2 = 30.0 mA
—
—
0.5
V
VCC = 5.5 V,
VSS < VI < VCC
–5
—
5
µA
VCC = 5.5 V,
AVSS < VI < AVCC
–1
—
1
µA
—
37
60
mA
MB90594/594G
—
50
80
mA
MB90F594A/F594G
—
50
80
mA
MB90F591A/F591G
—
45
60
mA
MB90591/591G
—
13
20
mA
MB90594/594G
—
15
23
mA
MB90F594A/F594G
—
15
23
mA
MB90F591A/F591G
—
15
23
mA
MB90591/591G
—
0.3
0.6
mA
MB90594/594G
—
0.35
0.6
mA
MB90F594A/F594G
—
0.35
0.6
mA
MB90F591A/F591G
—
0.35
0.6
mA
MB90591/591G
—
5
20
µA
MB90594/594G
—
5
20
µA
MB90F594A/F594G
—
5
20
µA
MB90F591A/F591G
—
5
20
µA
MB90591/591G
Input leak
current
IIL
—
Analog input
leak current
IIAL
AN0 to AN7
VCC = 4.5 V,
IOL1 = 4.0 mA
VCC = 5.0 V±10%,
Internal frequency :
16 MHz,
At normal operation.
ICC
VCC = 5.0 V±10%,
Internal frequency :
16 MHz,
At Sleep mode.
ICCS
Power
supply
current *
VCC = 4.5 V,
IOH1 = –4.0 mA
VCC
ICTS
ICCH
VCC = 5.0 V±10%,
Internal frequency :
2 MHz,
At Timer mode
VCC = 5.0 V±10%,
At Stop mode,
TA = 25°C
* : The power supply current testing conditions are when using the external clock.
(Continued)
39
MB90590/590G Series
(Continued)
(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G :
VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Condition
Unit
Remarks
Parameter Symbol Pin name
Min
Typ
Max
Input
capacity
Pull-up
resistance
Pull-down
resistance
40
Other than C,
AVCC, AVSS,
AVRH,
AVRL, VCC,
VSS, DVCC,
DVSS,
P70 to P87
—
—
5
15
pF
P70 to P87
—
—
15
30
pF
RST
—
25
50
100
kΩ
RDOWN MD2
—
25
50
100
kΩ
CIN
RUP
MB90590/590G Series
4. AC Characteristics
(1) Clock Timing
(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G :
VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Pin
Unit
Remarks
Parameter
Symbol
name Min Typ Max
Oscillation frequency
fC
Oscillation cycle time
tCYL
Input clock pulse width
X0, X1
3
X0, X1 62.5
—
16
MHz
—
333
ns
PWH, PWL
X0
10
—
—
ns
Duty ratio is about 30 to 70%.
tCR, tCF
X0
—
—
5
ns
When using external clock
Machine clock frequency
fCP
—
1.5
—
16
MHz
Machine clock cycle time
tCP
—
62.5
—
666
ns
tCYCFL
—
—
2 tCP
—
ns
Input clock rise and fall time
Flash read cycle time
• Clock Timing
When Flash is accessed by CPU
tCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCF
tCR
Example of Oscillation circuit
X0
X1
R
C1
C2
41
MB90590/590G Series
• Guaranteed operation range
Guaranteed operation range (MB90F591G, MB90591G, MB90F591A, MB90591)
Guaranteed operation range (MB90V590A, MB90F594A, MB90594,
MB90V590G, MB90F594G, MB90594G)
5.5
5.25
4.75
4.5
Guaranteed PLL operation range
(MB90F591G, MB90591G, MB90F591A, MB90591)
Power supply voltage
VCC (V)
Guaranteed PLL operation range
(MB90V590A, MB90F594A, MB90594,
MB90V590G, MB90F594G, MB90594G)
3.0
1.5
8
Machine clock
16
fCP (MHz)
• Oscillation clock frequency and machine clock frequency
×4
16
×3
×2
×1
12
Machine clock
fCP (MHz)
9
8
×1/2
(PLL off)
4
3
4
8
Oscillation frequency fC (MHz)
42
16
MB90590/590G Series
(2) Reset and Hardware Standby Input
(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G :
VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name
Unit
Remarks
Parameter
Min
Max
16 tCP*1
—
ns
Under normal operation
Reset input time
tRSTL
RST
Oscillation time of
oscillator*2 + 16 tCP*1
—
ms
In stop mode
Hardware standby input time
tHSTL
HST
16 tCP*1
—
ns
Under normal operation
*1 : “tcp” represents one cycle time of the machine clock.
No reset can fully initialize the Flash Memory if it is performing the automatic algorithm.
*2 : Oscillation time of oscillator is time that the amplitude reached the 90%.
In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR / ceramic oscillator, the
oscillation time is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms.
Under Normal Operation
tRSTL, tHSTL
RST
HST
0.2 VCC
0.2 VCC
In Stop Mode
tRSTL
RST
0.2VCC
0.2VCC
90% of
amplitude
X0
Internal operation clock
16 tCP
Oscillation time of
oscillator
Oscillation setting time
Instruction execution
Internal reset
43
MB90590/590G Series
(3) Power On Reset
(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G :
VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol Pin name
Condition
Unit
Remarks
Min
Max
Power on rise time
Power off time
tR
VCC
tOFF
VCC
—
0.05
30
ms
50
—
ms
Due to repetitive operation
Notes : • VCC must be kept lower than 0.2 V before power-on.
• The above values are used for creating a power-on reset.
• Some registers in the device are initialized only upon a power-on reset. To initialize these register, turn on
the power supply using the above values.
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to
raise the voltage smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1
V or fewer per second, however, you can use the PLL clock.
VCC
3V
RAM data being held
VSS
44
It is recommended to keep the
rising speed of the supply voltage
at 50 mV/ms or slower.
MB90590/590G Series
(4) UART0/1/2, Serial I/O
(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G :
VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol
Pin name
Condition
Unit Remarks
Min Max
8 tCP*
—
ns
–80
80
ns
100
—
ns
SCK0 to SCK3,
SIN0 to SIN3
60
—
ns
tSHSL
SCK0 to SCK3
4 tCP
—
ns
Serial clock "L" pulse width
tSLSH
SCK0 to SCK3
4 tCP
—
ns
SCK ↓ ⇒ SOT delay time
tSLOV
—
150
ns
Valid SIN ⇒ SCK ↑
tIVSH
60
—
ns
SCK ↑ ⇒ Valid SIN hold time
tSHIX
60
—
ns
Serial clock cycle time
tSCYC
SCK ↓ ⇒ SOT delay time
tSLOV
Valid SIN ⇒ SCK ↑
tIVSH
SCK ↑ ⇒ Valid SIN hold time
tSHIX
Serial clock "H" pulse width
SCK0 to SCK3
SCK0 to SCK3,
SOT0 to SOT3 Internal clock operaSCK0 to SCK3, tion output pins are
CL = 80 pF + 1 TTL.
SIN0 to SIN3
SCK0 to SCK3,
External clock operSOT0 to SOT3
ation output pins are
SCK0 to SCK3, CL = 80 pF + 1 TTL.
SIN0 to SIN3
SCK0 to SCK3,
SIN0 to SIN3
* : tCP is the machine cycle (Unit : ns)
Notes : • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• Internal Shift Clock Mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
SOT
2.4 V
0.8 V
tIVSH
SIN
0.8 VCC
0.5 VCC
tSHIX
0.8 VCC
0.5 VCC
45
MB90590/590G Series
• External Shift Clock Mode
tSLSH
tSHSL
0.8 VCC
SCK
0.8 VCC
0.5 VCC 0.5 VCC
tSLOV
2.4 V
0.8 V
SOT
tIVSH
tSHIX
0.8 VCC
0.5 VCC
SIN
0.8 VCC
0.5 VCC
(5)Timer Input Timing
(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G :
VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol Pin name
Condition
Unit
Remarks
Min
Max
Input pulse width
tTIWH
TIN0
tTIWL
IN0 to IN5
—
4 tCP
—
ns
Under normal operation
1
—
µs
In stop mode
• Timer Input Timing
0.8 VCC
0.8 VCC
0.5 VCC
tTIWH
46
0.5 VCC
tTIWL
MB90590/590G Series
(6)Trigger Input Timing
(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G :
VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol
Pin name
Condition
Unit
Remarks
Min
Max
Input pulse width
INT0 to
INT7, ADTG
tTRGH
tTRGL
—
5 tCP
—
ns
• Trigger Input Timing
0.8 VCC
0.8 VCC
0.5 VCC
0.5 VCC
tTRGH
tTRGL
(7) Slew Rate High Current Outputs
(MB90F591G, MB90591G, MB90F591A, MB90591, MB90594G and MB90F594G only)
(MB90F594G, MB90594G : VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591G, MB90591G, MB90F591A, MB90591 : VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol
Pin name
Condition
Unit
Remarks
Min
Max
Output Rise/Fall time
tR2
tF2
Port P70 to P77,
Port P80 to P87
—
15
40
ns
• Slew Rate Output Timing
VH
VH
VL
VL
tR2
VH = VOL2 + 0.1 × (VOH2 − VOL2)
VL = VOL2 + 0.9 × (VOH2 − VOL2)
tF2
47
MB90590/590G Series
5. A/D Converter
(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G :
VCC = AVCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, 3.0 V ≤ AVR+ − AVR-, TA = −40 °C to +85 °C)
(MB90F591G, MB90591G, MB90F591A, MB90591 :
VCC = AVCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, 3.0 V ≤ AVR+ − AVR-, TA = −40 °C to +85 °C)
Value
Parameter
Symbol Pin name
Unit
Remarks
Min
Typ
Max
Resolution
—
—
—
—
10
bit
Conversion error
—
—
—
—
±5.0
LSB
Nonlinearity error
—
—
—
—
±2.5
LSB
Differential linearity
error
—
—
—
—
±1.9
LSB
Zero transition voltage
VOT
AN0 to AN7
AVRL
– 3.5 LSB
AVRL
+ 0.5 LSB
AVRL
+ 4.5 LSB
mV
Full scale transition voltage
VFST
AN0 to AN7
AVRH
– 6.5 LSB
AVRH
– 1.5 LSB
AVRH
+ 1.5 LSB
mV
Compare time
—
—
352tCP
—
—
ns
Internal
frequency :
16 MHz
Sampling time
—
—
64tCP
—
—
ns
Internal
frequency :
16 MHz
Analog port input current
IAIN
AN0 to AN7
-1
—
+1
µA
Analog input voltage range
VAIN
AN0 to AN7
AVRL
—
AVRH
V
—
AVRH
AVRL + 2.7
—
AVCC
V
—
AVRL
0
—
AVRH – 2.7
V
IA
AVCC
—
5
—
mA
IAH
AVCC
—
—
5
µA
*
Reference voltage range
Power supply current
Reference voltage current
Offset between input
channels
IR
—
400
600
µA
MB90594
MB90V590A
MB90V590G
MB90F594A
MB90F594G
MB90F591A
MB90F591G
—
140
600
µA
MB90594G
MB90591
MB90591G
*
AVRH
IRH
AVRH
—
—
5
µA
—
AN0 to AN7
—
—
4
LSB
* : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) when the CPU is stopped.
48
MB90590/590G Series
6. A/D Converter Glossary
Resolution : Analog changes that are identifiable with the A/D converter
Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000
0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics
Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error : The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
Total error
3FF
3FE
0.5 LSB
Actual conversion
value
Digital output
3FD
{1 LSB × (N – 1) + 0.5 LSB}
004
VNT
(measured value)
003
Actual conversion
characteristics
002
Theoretical
characteristics
001
0.5 LSB
AVRL
1 LSB = (Theoretical value)
AVRH – AVRL
1024
VOT (Theoretical value) = AVRL + 0.5 LSB[V]
Analog input
[V]
AVRH
Total error for digital output N =
VNT – {1 LSB × (N – 1) + 0.5 LSB}
[LSB]
1 LSB
VNT : Voltage at a transition of digital output from (N – 1) to N
VFST (Theoretical value) = AVRH – 1.5 LSB[V]
(Continued)
49
MB90590/590G Series
(Continued)
Linearity error
Differential linearity error
Theoretical characteristics
3FF
Actual conversion
value
{1 LSB × (N – 1)+ VOT}
3FE
N+1
Actual conversion value
VFST
(measured value)
VNT
(measured value)
004
Actual conversion
characteristics
003
Digital output
Digital output
3FD
N
V(N + 1)T
(measured value)
N–1
VNT (measured value)
002
Theoretical
characteristics
001
Actual conversion
value
N–2
VOT (measured value)
AVRL
Analog input
AVRH
AVRL
Analog input
AVRH
VNT – {1 LSB × (N – 1) + VOT}
Linearity error of
[LSB]
digital output N =
1 LSB
Differential linearity error
=
of digital N
1 LSB =
VFST – VOT
V(N + 1)T – VNT
– 1 LSB [LSB]
1 LSB
[V]
1022
VOT : Voltage at transition of digital output from “000H” to “001H”
VFST : Voltage at transition of digital output from “3FEH” to “3FFH”
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions, :
• Output impedance values of the external circuit of 15 kΩ or lower are recommended.
• When capacitors are connected to external pins, the capacitance of several thousand times the internal
capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor
and internal capacitor.
When the output impedance of the external circuit is too high, the sampling period for analog voltages may not
be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz).
• Equipment of analog input circuit model
Analog input
Comparator
3.2 kΩ Max
30 pF Max
Note : Listed values must be considered as standards.
• Error
The smaller the | AVRH − AVRL |, the greater the error would become relatively.
50
MB90590/590G Series
8. Flash Memory
• Erase and Programming Performance
Value
Parameter
Condition
Min
Typ Max
Sector erase time
Chip erase time
TA = + 25 °C
VCC = 5.0 V
Word (16-bit)
programming time
Erase/Program
cycle
—
Unit
Remarks
—
1
15
s
Excludes 00H programming prior erasure
—
7
—
s
—
12
—
s
MB90F594A/F594G Excludes 00H programming
MB90F591A/F591G prior erasure
—
16
3,600
ns
Excludes system-level overhead
10,000
—
—
cycle
51
MB90590/590G Series
■ EXAMPLE CHARACTERISTICS
• “H” Level Output Voltage
VOH1 – IOH1
VOH2 – IOH2
(Vcc = 4.5 V, TA = +25˚C)
5
4.5
4
4
3.5
3.5
VOH2 [V]
VOH1 [V]
4.5
3
2.5
3
2.5
2
2
1.5
1.5
1
1
0.5
0.5
0
(Vcc = 4.5 V, TA = +25˚C)
5
0
0.0
-2.0
-4.0
-6.0
-8.0
-10.0
0
IOH1 [mA]
-10
-20
-30
-40
IOH2 [mA]
• “L” Level Output Voltage
VOL2 – IOL2
(Vcc = 4.5 V, TA = +25˚C)
0.8
0.7
0.7
0.6
0.6
0.5
0.5
VOL2 [V]
VOL1 [V]
0.8
VOL1 – IOL1
(Vcc = 4.5 V, TA = +25˚C)
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0.0
0
2.0
4.0
8.0
6.0
0.0
10.0
10.0
20.0
30.0
40.0
IOL2 [mA]
IOL1 [mA]
• “H” Level Input Voltage/“L Level Input Voltage
(Hysteresis Input)
VIN – VCC
(TA = +25˚C)
5
VIH
4
VIN [V]
VIL
3
2
1
0
3
4
5
6
Vcc [V]
(Continued)
52
MB90590/590G Series
(Continued)
• Power Supply Voltage
ICC – VCC
ICCS – VCC
(TA = +25˚C)
(TA = +25˚C)
60
25
fcp = 16 MHz
fcp = 16 MHz
40
30
fcp = 8 MHz
ICCS [mA]
ICC [mA]
50
20
15
fcp = 8 MHz
10
20
fcp = 4 MHz
fcp = 4 MHz
5
10
0
fcp = 2 MHz
fcp = 2 MHz
2.0
3.0
4.0
5.0
6.0
0
7.0
2.0
3.0
4.0
VCC [V]
ICTS – VCC
800
5.0
6.0
7.0
VCC [V]
ICCH – VCC
(TA = +25˚C)
18
fcp = 4 MHz
700
(TA = +25˚C)
20
16
ICTS [mA]
500
fcp = 2 MHz
400
ICCT [mA]
600
14
12
10
8
300
6
200
4
100
2
0
2.0
3.0
4.0
5.0
VCC [V]
6.0
7.0
0
2.0
3.0
4.0
5.0
6.0
7.0
VCC [V]
53
MB90590/590G Series
■ ORDERING INFORMATION
Part number
54
Package
MB90594PF
MB90591PF
MB90594GPF
MB90F594GPF
MB90F594APF
MB90F591APF
MB90F591GPF
MB90591GPF
100-pin Plastic QFP
(FPT-100P-M06)
MB90V590ACR
MB90V590GCR
256-pin Ceramic PGA
(PGA-256C-A01)
Remarks
For evaluation
MB90590/590G Series
■ PACKAGE DIMENSION
100-pin plastic QFP
(FPT-100P-M06)
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
"A"
C
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8°
31
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
2001 FUJITSU LIMITED F100008S-c-4-4
Dimensions in mm (inches)
55
MB90590/590G Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0204
FUJITSU LIMITED Printed in Japan