FUJITSU MB91101A

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16301-2E
32-bit RISC Microcontroller
CMOS
FR30 Series
MB91101/MB91101A
■ DESCRIPTION
The MB91101 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family)
core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU
processing for embedded controller applications. To support the vast memory space accessed by the 32-bit
CPU, the MB91101 normally operates in the external bus access mode and executes instructions on the internal
1 Kbyte cache memory and 2 Kbytes RAM for enhanced performance.
The MB91101 is optimized for applications requiring high-performance CPU processing such as navigation
systems, high-performance FAXs and printer controllers.
*: FR Family stands for FUJITSU RISC controller.
■ FEATURES
FR CPU
•
•
•
•
•
•
32-bit RISC, load/store architecture, 5-stage pipeline
Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)
General purpose registers: 32 bits × 16
16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle
Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications
Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems
supporting high level languages
• Register interlock functions, efficient assembly language coding
• Branch instructions with delay slots: Reduced overhead time in branch executions
(Continued)
■ PACKAGE
100-pin Plastic LQFP
100-pin Plastic QFP
(FPT-100P-M05)
(FPT-100P-M06)
MB91101/MB91101A
(Continued)
• Internal multiplier/supported at instruction level
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
• Interrupt (push PC and PS): 6 cycles, 16 priority levels
External bus interface
•
•
•
•
•
•
Clock doubler: Internal 50 MHz, external bus 25 MHz operation
25-bit address bus (32 Mbytes memory space)
8/16-bit data bus
Basic external bus cycle: 2 clock cycles
Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 6
Interface supported for various memory technologies
DRAM interface (area 4 and 5)
• Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area
• Unused data/address pins can be configured us input/output ports
• Little endian mode supported (Select 1 area from area 1 to 5)
DRAM interface
•
•
•
•
•
2 banks independent control (area 4 and 5)
Normal mode (double CAS DRAM)/high-speed page mode (single CAS DRAM)/Hyper DRAM
Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode
Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles
DRAM refresh
CBR refresh (interval time configurable by 6-bit timer)
Self-refresh mode
• Supports 8/9/10/12-bit column address width
• 2CAS/1WE, 2WE/1CAS selective
Cache memory
•
•
•
•
1-Kbyte instruction cache memory
32 block/way, 4 entry(4 word)/block
2 way set associative
Lock function: For specific program code to be resident in cashe memory
DMA controller (DMAC)
•
•
•
•
•
8 channels
Transfer incident/external pins/internal resource interrupt requests
Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer
Transfer data length: 8 bits/16 bits/32 bits selective
NMI/interrupt request enables temporary stop operation
UART
•
•
•
•
•
•
•
•
2
3 independent channels
Full-duplex double buffer
Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity)
Asynchronous (start-stop system), CLK-synchronized communication selective
Multi-processor mode
Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate
Use external clock can be used as a transfer clock
Error detection: Parity, frame, overrun
MB91101/MB91101A
(Continued)
10-bit A/D converter (successive approximation conversion type)
•
•
•
•
•
10-bit resolution, 4 channels
Successive approximation type: Conversion time of 5.6 µs at 25 MHz
Internal sample and hold circuit
Conversion mode: Single conversion/scanning conversion/repeated conversion/stop conversion selective
Start: Software/external trigger/internal timer selective
16-bit reload timer
• 3 channels
• Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective
Other interval timers
• 16-bit timer: 3 channels (U-TIMER)
• PWM timer: 4 channels
• Watchdog timer: 1 channel
Bit search module
First bit transition “1” or “0” from MSB can be detected in 1 cycle
Interrupt controller
• External interrupt input: Non-maskable interrupt (NMI), normal interrupt × 4 (INT0 to INT3)
• Internal interrupt incident: UART, DMA controller (DMAC), A/D converter, U-TIMER and delayed interrupt
module
• Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps)
Others
• Reset cause: Power-on reset/hardware standby/watchdog timer/software reset/external reset
• Low-power consumption mode: Sleep mode/stop mode
• Clock control
Gear function: Operating clocks for CPU and peripherals are independently selective
Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16)
However, operating frequency for peripherals is less than 25 MHz.
• Packages: LQFP-100 and QFP-100
• CMOS technology (0.35 µm)
• Power supply voltage
5 V: CPU power supply 5.0 V ±10% (internal regulator)
A/D power supply 2.7 V to 3.6 V
3 V: CPU power supply 2.7 V to 3.6 V (without internal regulator)
A/D power supply 2.7 V to 3.6 V
3
D17/P21
D18/P22
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27
D24
D25
D26
D27
D28
D29
D30
VSS
D31
A00
VCC5
A01
A02
A03
A04
A05
A06
A07
CS1L/PB5/DREQ2
CS1H/PB6/DACK2
DW1/PB7
VCC3
CLK/PA6
CS5/PA5
CS4/PA4
CS3/PA3/EOP1
CS2/PA2
CS1/PA1
CS0
NMI
HST
RST
VSS
MD0
MD1
MD2
RDY/P80
BGRNT/P81
BRQ/P82
RD
WR0
WR1/P85
D16/P20
4
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RAS1/PB4/EOP2
DW0/PB3
CS0H/PB2
CS0L/PB1
RAS0/PB0
INT0/PE0
INT1/PE1
VCC5
X0
X1
VSS
INT2/SC1/PE2
INT3/SC2/PE3
DREQ0/PE4
DREQ1/PE5
DACK0/PE6
DACK1/PE7
OCPA0/PF7/ATG
SO2/OCPA2/PF6
SI2/OCPA1/PF5
SO1/TRG3/PF4
SI1/TRG2/PF3
SC0/OCPA3/PF2
SO0/TRG1/PF1
SI0/TRG0/PF0
MB91101/MB91101A
■ PIN ASSIGNMENT
(Top view)
(FPT-100P-M05)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AN3
AN2
AN1
AN0
AVSS/AVRL
AVRH
AVCC
A24/EOP0
A23/P67
A22/P66
VSS
A21/P65
A20/P64
A19/P63
A18/P62
A17/P61
A16/P60
A15
A14
A13
A12
A11
A10
A09
A08
MB91101/MB91101A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CS0L/PB1
RAS0/PB0
INT0/PE0
INT1/PE1
VCC5
X0
X1
VSS
INT2/SC1/PE2
INT3/SC2/PE3
DREQ0/PE4
DREQ1/PE5
DACK0/PE6
DACK1/PE7
OCPA0/PF7/ATG
SO2/OCPA2/PF6
SI2/OCPA1/PF5
SO1/TRG3/PF4
SI1/TRG2/PF3
SC0/OCPA3/PF2
(Top view)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SO0/TRG1/PF1
SI0/TRG0/PF0
AN3
AN2
AN1
AN0
AVSS/AVRL
AVRH
AVCC
A24/EOP0
A23/P67
A22/P66
VSS
A21/P65
A20/P64
A19/P63
A18/P62
A17/P61
A16/P60
A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27
D24
D25
D26
D27
D28
D29
D30
VSS
D31
A00
VCC5
A01
A02
A03
A04
CS0H/PB2
DW0/PB3
RAS1/PB4/EOP2
CS1L/PB5/DREQ2
CS1H/PB6/DACK2
DW1/PB7
VCC3
CLK/PA6
CS5/PA5
CS4/PA4
CS3/PA3/EOP1
CS2/PA2
CS1/PA1
CS0
NMI
HST
RST
VSS
MD0
MD1
MD2
RDY/P80
BGRNT/P81
BRQ/P82
RD
WR0
WR1/P85
D16/P20
D17/P21
D18/P22
(FPT-100P-M06)
5
MB91101/MB91101A
■ PIN DESCRIPTION
Pin no.
LQFP*1
25 to 32
QFP*2
Pin name
28 to 35 D16 to D23
Circuit
type
C
P20 to P27
Function
Bit 16 to bit 23 of external data bus
Can be configured as I/O ports when external data bus width is
set to 8-bit.
33 to 39,
41
36 to 42, D24 to D30,
44
D31
C
Bit 24 to bit 31 of external data bus
42,
44 to 58
45,
A00,
47 to 61 A01 to A15
F
Bit 00 to bit 15 of external address bus
59 to 64,
66,
67
62 to 67, A16 to A21,
69,
A22,
70
A23
F
Bit 16 to bit 23 of external address bus
P60 to P65,
P66,
P67
68
71
A24
Can be configured as I/O ports when not used as address bus.
L
EOP0
19
22
RDY
Can be configured as DMAC EOP output (ch. 0) when DMAC
EOP output is enabled.
C
P80
20
23
BGRNT
24
BRQ
External ready input
Inputs “0” when bus cycle is being executed and not
completed.
Can be configured as a port when RDY is not used.
F
P81
21
Bit 24 of external address bus
External bus release acknowledge output
Outputs “L” level when external bus is released.
Can be configured as a port when BGRNT is not used.
C
P82
External bus release request input
Inputs “1” when release of external bus is required.
Can be configured as a port when BRQ is not used.
22
25
RD
L
Read strobe output pin for external bus
23
26
WR0
L
Write strobe output pin for external bus
Relation between control signals and effective byte locations is
as follows:
24
27
WR1
F
16-bit bus width
8-bit bus width
D15 to D08
WR0
WR0
D07 to D00
WR1
(I/O port enabled)
Note: WR1 is Hi-Z during resetting.
Attach an external pull-up resister when using at 16-bit
bus width.
P85
*1: FPT-100P-M05
*2: FPT-100P-M06
6
Can be configured as a port when WR1 is not used.
(Continued)
MB91101/MB91101A
Pin no.
1
2
Pin name
Circuit
type
Function
LQFP*
QFP*
11
14
CS0
L
Chip select 0 output (“L” active)
10
13
CS1
F
Chip select 1 output (“L” active)
PA1
9
12
CS2
Can be configured as a port when CS1 is not used.
F
PA2
8
7
11
10
CS3
Can be configured as a port when CS2 is not used.
F
9
Can be configured as a port when CS3 and EOP1 are not
used.
EOP1
EOP output pin for DMAC (ch. 1)
This function is available when EOP output for DMAC is
enabled.
CS4
F
CS5
8
CLK
F
99
RAS0
F
100
CS0L
F
1
CS0H
F
2
DW0
F
3
*1: FPT-100P-M05
*2: FPT-100P-M06
RAS1
CASH output for DRAM bank 0
Refer to the DRAM interface for details.
Can be configured as a port when CS0H is not used.
F
PB3
100
CASL output for DRAM bank 0
Refer to the DRAM interface for details.
Can be configured as a port when CS0L is not used.
PB2
99
RAS output for DRAM bank 0
Refer to the DRAM interface for details.
Can be configured as a port when RAS0 is not used.
PB1
98
System clock output
Outputs clock signal of external bus operating frequency.
Can be configured as a port when CLK is not used.
PB0
97
Chip select 5 output (“L” active)
Can be configured as a port when CS5 is not used.
PA6
96
Chip select 4 output (“L” active)
Can be configured as a port when CS4 is not used.
PA5
5
Chip select 3 output (“L” active)
PA3
PA4
6
Chip select 2 output (“L” active)
WE output for DRAM bank 0 (“L” active)
Refer to the DRAM interface for details.
Can be configured as a port when DW0 is not used.
F
RAS output for DRAM bank 1
Refer to the DRAM interface for details.
PB4
Can be configured as a port when RAS1 and EOP2 are not
used.
EOP2
DMAC EOP output (ch. 2)
This function is available when DMAC EOP output is enabled.
(Continued)
7
MB91101/MB91101A
Pin no.
1
LQFP*
QFP*
1
4
2
3
5
6
2
Pin name
CS1L
Circuit
type
F
Can be configured as a port when CS1L and DREQ2 are not
used.
DREQ2
External transfer request input pin for DMA
This pin is used for input when external trigger is selected to
cause DMAC operation, and it is necessary to disable output for
other functions from this pin unless such output is made
intentionally.
CS1H
F
CASH output for DRAM bank 1
Refer to the DRAM interface for details.
PB6
Can be configured as a port when CS1H and DACK2 are not
used.
DACK2
External transfer request acknowledge output pin for DMAC (ch.
2)
This function is available when transfer request output for DMAC
is enabled.
DW1
F
19 to 21 MD0 to MD2
WE output for DRAM bank 1 (“L” active)
Refer to the DRAM interface for details.
Can be configured as a port when DW1 is not used.
G
Mode pins 0 to 2
MCU basic operation mode is set by these pins.
Directly connect these pins with VCC or VSS for use.
92
95
X0
A
Clock (oscillator) input
91
94
X1
A
Clock (oscillator) output
14
17
RST
B
External reset input
13
16
HST
H
Hardware standby input (“L” active)
12
15
NMI
H
NMI (non-maskable interrupt pin) input (“L” active)
95,
94
98,
97
INT0,
INT1
F
External interrupt request input pins
These pins are used for input during corresponding interrupt is
enabled, and it is necessary to disable output for other functions
from these pins unless such output is made intentionally.
PE0,
PE1
89
92
*1: FPT-100P-M05
*2: FPT-100P-M06
8
CASL output for DRAM bank 1
Refer to the DRAM interface for details.
PB5
PB7
16 to 18
Function
INT2
Can be configured as a I/O port when INT0, INT1 are not used.
F
External interrupt request input pin
This pin is used for input during corresponding interrupt is
enabled, and it is necessary to disable output for other functions
from this pin unless such output is made intentionally.
SC1
Clock I/O pin for UART1
Clock output is available when clock output of UART1 is enabled.
PE2
Can be configured as a I/O port when INT2 and SC1 are not
used.
This function is available when UART1 clock output is disabled.
(Continued)
MB91101/MB91101A
Pin no.
LQFP*
88
87,
86
1
2
QFP*
91
90,
89
Pin name
INT3
Circuit
type
F
88
UART2 clock I/O pin
Clock output is available when UART2 clock output is enabled.
PE3
Can be configured as a I/O port when INT3 and SC2 are not used.
This function is available when UART2 clock output is disabled.
DREQ0,
DREQ1
F
DACK0
87
DACK1
F
79
*1: FPT-100P-M05
*2: FPT-100P-M06
SI0
External transfer request acknowledge output pin for DMAC (ch. 0)
This function is available when transfer request output for DMAC is
enabled.
Can be configured as a I/O port when DACK0 is not used.
This function is available when transfer request acknowledge
output for DMAC or DACK0 output is disabled.
F
PE7
76
External transfer request input pins for DMA
These pins are used for input when external trigger is selected to
cause DMAC operation, and it is necessary to disable output for
other functions from these pins unless such output is made
intentionally.
Can be configured as a I/O port when DREQ0, DREQ1 are not
used.
PE6
84
External interrupt request input pin
This pin is used for input during corresponding interrupt is enabled,
and it is necessary to disable output for other functions from this
pin unless such output is made intentionally.
SC2
PE4,
PE5
85
Function
External transfer request acknowledge output pin for DMAC (ch. 1)
This function is available when transfer request output for DMAC is
enabled.
Can be configured as a I/O port when DACK1 is not used.
This function is available when transfer request output for DMAC or
DACK1 output is disabled.
F
UART0 data input pin
This pin is used for input during UART0 is in input operation, and it
is necessary to disable output for other functions from this pin
unless such output is made intentionally.
TRG0
PWM timer external trigger input pin
This pin is used for input during PWM timer external trigger is in
input operation, and it is necessary to disable output for other
functions from this pin unless such output is made intentionally.
PF0
Can be configured as a I/O port when SI0 and TRG0 are not used.
(Continued)
9
MB91101/MB91101A
Pin no.
1
LQFP*
QFP*
77
80
78
79
80
81
2
81
82
83
84
*1: FPT-100P-M05
*2: FPT-100P-M06
10
Pin name
SO0
Circuit
type
F
Function
UART0 data output pin
This function is available when UART0 data output is enabled.
TRG1
PWM timer external trigger input pin
This function is available when serial data output of PF1, UART0
are disabled.
PF1
Can be configured as a I/O port when SO0 and TRG1 are not
used.
This function is available when serial data output of UART0 is
disabled.
SC0
F
UART0 clock I/O pin
Clock output is available when UART0 clock output is enabled.
OCPA3
PWM timer output pin
This function is available when PWM timer output is enabled.
PF2
Can be configured as a I/O port when SC0 and OCPA3 are not
used.
This function is available when UART0 clock output is disabled.
SI1
F
UART1 data input pin
This pin is used for input during UART1 is in input operation, and it
is necessary to disable output for other functions from this pin
unless such output is made intentionally.
TRG2
PWM timer external trigger input pin
This pin is used for input during PWM timer external trigger is in
input operation, and it is necessary to disable output for other
functions from this pin unless such output is made intentionally.
PF3
Can be configured as a I/O port when SI1 and TRG2 are not used.
SO1
F
UART1 data output pin
This function is available when UART1 data output is enabled.
TRG3
PWM timer external trigger input pin
This function is available when PF4, UART1 data outputs are
disabled.
PF4
Can be configured as a I/O port when SO1 and TRG3 are not
used.
This function is available when UART1 data output is disabled.
SI2
F
UART2 data input pin
This pin is used for input during UART2 is in input operation, and it
is necessary to disable output for other functions from this pin
unless such output is made intentionally.
OCPA1
PWM timer output pin
This function is available when PWM timer output is enabled.
PF5
Can be configured as a I/O port when SI2 and OCPA1 are not
used.
(Continued)
MB91101/MB91101A
(Continued)
Pin no.
1
LQFP*
QFP*
82
85
83
72 to 75
86
2
Pin name
SO2
Circuit
type
F
Function
UART2 data output pin
This function is available when UART2 data output is enabled.
OCPA2
PWM timer output pin
This function is available when PWM timer output is enabled.
PF6
Can be configured as a I/O port when SO2 and OCPA2 are not
used.
This function is available when UART2 data output is disabled.
OCPA0
F
PWM timer output pin
This function is available when PWM timer output is enabled.
PF7
Can be configured as a I/O port when OCPA0 and ATG are not
used.
This function is available when PWM timer output is disabled.
ATG
External trigger input pin for A/D converter
This pin is used for input when external trigger is selected to
cause A/D converter operation, and it is necessary to disable
output for other functions from this pin unless such output is
made intentionally.
75 to 78 AN0 to AN3
D
Analog input pins of A/D converter
This function is available when AIC register is set to specify
analog input mode.
69
72
AVCC
—
Power supply pin (VCC) for A/D converter
70
73
AVRH
—
Reference voltage input (high) for A/D converter
Make sure to turn on and off this pin with potential of AVRH or
more applied to VCC.
71
74
AVSS / AVRL
—
Power supply pin (VSS) for A/D converter and reference voltage
input pin (low)
43,
93
46,
96
VCC5
—
5 V power supply pin (VCC) for digital circuit
Always two pins must be connected to the power supply
(connect to 3 V power supply when operating at 3 V).
4
7
VCC3
—
Bypass capacitor pin for internal capacitor.
Also connect this pin to 3 V power supply when operating at
3 V.
15,
40,
65,
90
18,
43,
68,
93
VSS
—
Earth level (VSS) for digital circuit
*1: FPT-100P-M05
*2: FPT-100P-M06
Note: In most of the above pins, I/O port and resource I/O are multiplexed e.g. P82 and BRQ. In case of conflict
between output of I/O port and resource I/O, priority is always given to the output of resource I/O.
11
MB91101/MB91101A
■ DRAM CONTROL PIN
Pin name
12
Data bus 16-bit mode
2CAS/1WR mode
1CAS/2WR mode
Data bus 8-bit mode
—
RAS0
Area 4 RAS
Area 4 RAS
Area 4 RAS
RAS1
Area 5 RAS
Area 5 RAS
Area 5 RAS
CS0L
Area 4 CASL
Area 4 CAS
Area 4 CAS
CS0H
Area 4 CASH
Area 4 WEL
Area 4 CAS
CS1L
Area 5 CASL
Area 5 CAS
Area 5 CAS
CS1H
Area 5 CASH
Area 5 WEL
Area 5 CAS
CW0
Area 4 WE
Area 4 WEH
Area 4 WE
DW1
Area 5 WE
Area 5 WEH
Area 5 WE
Remarks
Correspondence of “L”
“H” to lower address 1
bit (A0) in data bus 16bit mode
“L”: “0”
“H”: “1”
CASL: CAS which A0
corresponds to
“0” area
CASH: CAS which A0
corresponds to
“1” area
WEL: WE which A0
corresponds to
“0” area
WEH: WE which A0
corresponds to
“1” area
MB91101/MB91101A
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
X1
Clock input
• Oscillation feedback resistance 1 MΩ
approx.
With standby control
X0
Standby control signal
B
• CMOS level
Hysteresis input
Without standby control
With pull-up resistance
VCC
P-ch
P-ch
R
N-ch
VSS
Digital input
C
• CMOS level I/O
With standby control
R
P-ch
Digital output
N-ch
Digital output
Digital input
Standby control signal
D
• Analog input
R
P-ch
Digital output
N-ch
Digital output
Analog input
(Continued)
13
MB91101/MB91101A
Type
Circuit
Remarks
E
• N-ch open-drain output
• CMOS level input
With standby control
P-ch
R
N-ch
Digital output
Digital input
Standby control signal
F
R
P-ch
Digital output
N-ch
Digital output
• CMOS level output
• CMOS level
Hysteresis input
With standby control
Digital input
Standby control signal
G
• CMOS level input
Without standby control
P-ch
R
N-ch
Digital input
H
• CMOS level
Hysteresis input
Without standby control
P-ch
R
N-ch
Digital input
(Continued)
14
MB91101/MB91101A
(Continued)
Type
Circuit
Remarks
I
R
P-ch
Digital output
N-ch
Digital output
• CMOS level output
• CMOS level
Hysteresis input
Without standby control
Digital input
J
R
P-ch
Digital output
N-ch
Digital output
• CMOS level output
• TTL level input
With standby control
Digital input
Standby control signal
TTL
K
R
P-ch
Digital output
N-ch
Digital output
• CMOS level input/output
With standby control
• Large current drive
Digital input
Standby control signal
L
• CMOS level output
P-ch
Digital output
N-ch
Digital output
15
MB91101/MB91101A
■ HANDLING DEVICES
1. Preventing Latchup
In CMOS ICs, applying voltage higher than VCC or lower than VSS to input/output pin or applying voltage over
rating across VCC and VSS may cause latchup.
This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the
device. Make sure to prevent the voltage from exceeding the maximum rating.
Take care that the analog power supply (AVCC , AVR) and the analog input do not exceed the digital power
supply (VCC) when the analog power supply turned on or off.
2. Treatment of Unused Pins
Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors.
3. External Reset Input
It takes at least 5 machine cycle to input “L” level to the RST pin and to ensure inner reset operation properly.
4. Remarks for External Clock Operation
When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to
X0 must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin stops
at “H” output in stop mode).
And can be used to supply only to X0 pin with 5 V power supply at 12.5 MHz and less than.
• Using an external clock
X0
X1
MB91101
Using an external clock (normal)
Note: Can not be used stop mode (oscillation stop mode).
X0
Open
X1
MB91101
Using an external clock (can be used at 12.5 MHz and less than.)
(5 V power supply only)
16
MB91101/MB91101A
5. Power Supply Pins
When there are several VCC and VSS pins, each of them is equipotentially connected to its counterpart inside
of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions,
to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and
to observe the total output current standard, connect all VCC and VSS pins to the power supply or GND.
It is preferred to connect VCC and VSS of MB91101 to power supply with minimal impedance possible.
It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 µF between VCC
and VSS at a position as close as possible to MB91101.
MB91101 has an internal regulator. When using with 5 V power supply, supply 5 V to VCC5 pin and make sure
to connect about 0.1 µF bypass capacitor to VCC3 pin for regulator. And another 3 V power supply is needed
for the A/D convertor. When using with 3 V power supply, connect both VCC5 pin and VCC3 pin to the 3 V power
supply.
• Connecting to a power supply
[Using with 3 V power supply]
[Using with 5 V power supply]
3V
5V
3V
VCC5
AVCC
AVRH
AVSS
VSS
GND
VCC3
VCC5
VCC3
AVCC
About
0.1 µF
AVRH
AVSS
GND
VSS
6. Crystal Oscillator Circuit
Noises around X0 and X1 pins may cause malfunctions of MB91101. In designing the PC board, layout X0,
X1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible.
It is strongly recommended to design PC board so that X1 and X0 pins are surrounded by grounding area for
stable operation.
7. Turning-on Sequence of A/D Converter Power Supply and Analog Input
Make sure to turn on the digital power supply (VCC) before turning on the A/D converter (AVCC, AVRH) and
applying voltage to analog input (AN0 to AN3).
Make sure to turn off digital power supply after power supply to A/D converters and analog inputs have been
switched off. (There are no such limitations in turning on power supplies. Analog and digital power supplies
may be turned on simultaneously.) Make sure that AVRH never exceeds AVCC when turning on/off power
supplies.
8. Treatment of N.C. Pins
Make sure to leave N.C. pins open.
17
MB91101/MB91101A
9. Fluctuation of Power Supply Voltage
Warranty range for normal operation against fluctuation of power supply voltage VCC is as given in rating.
However, sudden fluctuation of power supply voltage within the warranty range may cause malfunctions. It is
recommended to make every effort to stabilize the power supply voltage to IC. It is also recommended that by
controlling power supply as a reference of stabilizing, VCC ripple fluctuation (P-P value) at the commercial
frequency (50 Hz to 60 Hz) should be less than 10% of the standard VCC value and the transient regulation
should be less than 0.1 V/ms at instantaneous deviation like turning off the power supply.
10. Mode Setting Pins (MD0 to MD2)
Connect mode setting pins (MD0 to MD2) directly to VCC or VSS.
Arrange each mode setting pin and VCC or VSS patterns on the printed circuit board as close as possible and
make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises.
11. Internal DC Regulator
Internal DC regulator stops in stop mode. When the regulator stops owing to the increase of inner leakage
current (ICCH) in stop mode, malfunction caused by noise or any troubles about power supply in normal
operation, the internal 3 V power supply voltage may decrease less than the warranty range for normal operation.
So when using the internal regulator and stop mode with 5 V power supply, never fail to support externally so
that 3 V power supply voltage might not decrease. However, even in such a case, the internal regulator can be
restarted by inputting the reset procedure. (In this case, set the reset to “L” level within the oscillation stabilizing
waiting time.)
• Using STOP mode with 5 V power supply
5V
VCC5
3.6 kΩ
VCC3
VSS
0.1 µF
approx.
6.8 kΩ
12. Turning on the Power Supply
When turning on the power supply, never fail to start from setting the RST pin to “L” level. And after the power
supply voltage goes to VCC level, at least after ensuring the time for 5 machine cycle, then set to “H” level.
13. Pin Condition at Turning on the Power Supply
The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning on
the power supply and then starting oscillation and then the operation of the internal regulator becomes stable.
So it takes about 42 ms for the pin to be initialized from the oscillation starting at the source oscillation 12.5
MHz. Take care that the pin condition may be output condition at initial unstable condition.
(With the MB91101A, however, initalization can be achieved in less than about 42 ms after turning on the
internal power supply by maintaining the RST pin at "L" level.)
18
MB91101/MB91101A
14. Source Oscillation Input at Turning on the Power Supply
At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing
waiting.
15. Hardware Stand-by at Turning on the Power Supply
When turning on the power supply with the HST pin being set to “L” level, the hardware doesn’t stand by.
However the HST pin becomes available after the reset cancellation, the HST pin must once be back to “H” level.
16. Power on Reset
Make sure to make power on reset at turning on the power supply or returning on the power supply when the
power supply voltage is below the warranty range for normal operation.
19
MB91101/MB91101A
■ BLOCK DIAGRAM
I-bus (16 bits)
FR CPU
Bit search module
DREQ0 to
DREQ2
DACK0 to
DACK2
EOP0 to
EOP2
3
3
D-bus (32 bits)
RAM (2 Kbytes)
Instruction cache (1 Kbyte)
Bus converter
(Harvard↔Princeton)
DMA controller (DMAC)
(8 ch.)
3
Bus converter (32 bits↔16 bits)
16
25
X0
X1
RST
HST
Clock control unit
(Watchdog timer)
2
Bus controller
6
Interrupt control unit
C-bus (32 bits)
AN0 to AN3
AVCC
AVSS /AVRL
AVRH
ATG
4
4
10-bit A/D converter
(4 ch.)
RAS0
RAS1
CS0L
CS0H
CS1L
CS1H
DW0
DW1
DRAM controller
Reload timer (3 ch.)
R-bus (16 bits)
INT0 to INT3
NMI
D16 to D31
A00 to A24
RD
WR0, WR1
RDY
CLK
CS0 to CS5
BRQ
BGRNT
Port 0 to port B
Port
Other pins
UART (3 ch.)
(Baud rate timer)
3
3
MD0 to MD2, P20 to P27, P60 to P67,
P80 to P82, P85, PA1 to PA6,
PB0 to PB7, PE0 to PE7, PF0 to PF7,
VCC3, VCC5, VSS
PWM timer (4 ch.)
4
4
SI0 to SI2
SO0 to SO2
SC0 to SC2
OCPA0 to OCPA3
TRG0 to TRG3
Note: Pins are display for functions (Actually some pins are multiplexer).
When using REALOS, time control should be done by using external interrupt or inner timer.
20
MB91101/MB91101A
■ CPU CORE
1. Memory Space
The FR family has a logical address space of 4 Gbytes (232 bytes) and the CPU linearly accesses the memory
space.
• Memory space
Address
External ROM/external bus mode
0000 0000H
I/O area
Direct addressing area
0000 0400H
See “■ I/O MAP”
I/O area
0000 0800H
Access inhibited
0000 1000H
Embedded RAM
0000 1800H
Access inhibited
0001 0000H
External area
FFFF FFFFH
• Direct addressing area
The following areas on the memory space are assigned to direct addressing area for I/O. In these areas, an
address can be specified in a direct operand of a code.
Direct areas consists of the following areas dependent on accessible data sizes.
Byte data access: 000H to 0FFH
Half word data access: 000H to 1FFH
Word data access: 000H to 3FFH
21
MB91101/MB91101A
2. Registers
The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose
registers on memory.
• Dedicated registers
Program counter (PC):
Program status (PS):
Table base register (TBR):
32-bit length, indicates the location of the instruction to be executed.
32-bit length, register for storing register pointer or condition codes
Holds top address of vector table used in EIT (Exceptional/Interrupt/Trap)
processing.
Return pointer (RP):
Holds address to resume operation after returning from a subroutine.
System stack pointer (SSP): Indicates system stack space.
User's stack pointer (USP): Indicates user’s stack space.
Multiplication/division result register (MDH/MDL): 32-bit length, register for multiplication/division
32 bits
PC
Program counter
PS
Program status
Initial value
XXXX XXXXH
Indeterminate
Table base register
000F
Return pointer
XXXX XXXXH
SSP
System stack pointer
0000
USP
User’s stack pointer
XXXX XXXXH
Indeterminate
XXXX XXXXH
Indeterminate
XXXX XXXXH
Indeterminate
TBR
RP
MDH
Multiplication/division result register
MDL
FC00H
Indeterminate
0000H
• Program status (PS)
The PS register is for holding program status and consists of a condition code register (CCR), a system condition
code register (SCR) and a interrupt level mask register (ILM).
31 to 21 20
PS
—
19
18
16 11 to 15 10
ILM4 ILM3 ILM2 ILM1 ILM0
ILM
22
17
—
D1
9
8
7
6
5
4
3
2
1
0
D0
T
—
—
S
I
N
Z
V
C
SCR
CCR
MB91101/MB91101A
• Condition code register (CCR)
S-flag:
I-flag:
N-flag:
Z-flag:
V-flag:
Specifies a stack pointer used as R15.
Controls user interrupt request enable/disable.
Indicates sign bit when division result is assumed to be in the 2’s complement format.
Indicates whether or not the result of division was “0”.
Assumes the operand used in calculation in the 2’s complement format and indicates whether
or not overflow has occurred.
Indicates if a carry or borrow from the MSB has occurred.
C-flag:
• System condition code register (SCR)
T-flag:
Specifies whether or not to enable step trace trap.
• Interrupt level mask register (ILM)
ILM4 to ILM0: Register for holding interrupt level mask value. The value held by this register is used as a
level mask. When an interrupt request issued to the CPU is higher than the level held by ILM,
the interrupt request is accepted.
ILM4
ILM3
ILM2
ILM1
ILM0
Interrupt level
High-low
0
0
0
0
0
0
High
:
:
0
1
0
:
:
0
0
:
:
1
1
1
15
:
:
1
1
31
Low
23
MB91101/MB91101A
■ GENERAL-PURPOSE REGISTERS
R0 to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator
and a memory access pointer (field for indicating address).
• Register bank structure
32 bits
Initial value
R0
R13
AC (accumulator)
R14
FP (frame pointer)
XXXX XXXXH
:
:
:
:
:
:
:
:
:
:
:
XXXX XXXXH
R15
SP (stack pointer)
0 0 0 0 0 0 0 0H
R1
:
:
R12
Of the above 16 registers, following registers have special functions. To support the special functions, part of
the instruction set has been sophisticated to have enhanced functions.
R13: Virtual accumulator (AC)
R14: Frame pointer (FP)
R15: Stack pointer (SP)
Upon reset, values in R0 to R14 are not fixed. Value in R15 is initialized to be 0000 0000H (SSP value).
24
MB91101/MB91101A
■ SETTING MODE
1. Pin
• Mode setting pins and modes
Mode setting
pins
Mode name
Reset vector
access area
External data
bus width
MD2 MD1 MD0
Bus mode
0
0
0
External vector mode 0
External
8 bits
0
0
1
External vector mode 1
External
16 bits
0
1
0
—
—
—
0
1
1
Internal vector mode
Internal
(Mode register)
1
—
—
—
—
—
External ROM/external bus
mode
Inhibited
Single-chip mode*
Inhibited
* : MB91101 does not support single-chip mode.
2. Registers
• Mode setting registers (MODR) and modes
Address
0000 07FFH
M1
M0
*
*
*
*
*
*
Initial value
Access
XXXX XXXXB
W
Bus mode setting bit
W : Write only
X : Indeterminate
* : Always write “0” except for M1 and M0.
• Bus mode setting bits and functions
M1
M0
Functions
0
0
Single-chip mode
0
1
Internal ROM/external bus mode
1
0
External ROM/external bus mode
1
1
—
Note
Inhibited
Note: Because of without internal ROM, MB91101 allows “10B” setting value only.
25
MB91101/MB91101A
■ I/O MAP
Address
Register name
(abbreviated)
Register name
0000H
0001H
Initial value
R/W
XXXXXXXXB
R/W
XXXXXXXXB
(Vacancy)
PDR2
Port 2 data register
0002H
to
0004H
0005H
Read/write
(Vacancy)
PDR6
Port 6 data register
0006H
(Vacancy)
0007H
0008H
PDRB
Port B data register
R/W
XXXXXXXXB
0009H
PDRA
Port A data register
R/W
– XXXXXX – B
R/W
– – X – – XXXB
000AH
000BH
(Vacancy)
PDR8
Port 8 data register
000CH
to
0011H
(Vacancy)
0012H
PDRE
Port E data register
R/W
XXXXXXXXB
0013H
PDRF
Port F data register
R/W
XXXXXXXXB
0014H
to
001BH
(Vacancy)
001CH
SSR0
Serial status register 0
R/W
00001–00B
001DH
SIDR0/SODR0
Serial input register 0/serial output register 0
R/W
XXXXXXXXB
001EH
SCR0
Serial control register 0
R/W
00000100B
001FH
SMR0
Serial mode register 0
R/W
00––0–00B
0020H
SSR1
Serial status register 1
R/W
00001–00B
0021H
SIDR1/SODR1
Serial input register 1/serial output register 1
R/W
XXXXXXXXB
0022H
SCR1
Serial control register 1
R/W
00000100B
0023H
SMR2
Serial mode register 1
R/W
00––0–00B
0024H
SSR2
Serial status register 2
R/W
00001–00B
0025H
SIDR2/SODR2
Serial input register 2/serial output register 2
R/W
XXXXXXXXB
0026H
SCR2
Serial control register 2
R/W
00000100B
0027H
SMR2
Serial mode register 2
R/W
00––0–00B
(Continued)
26
MB91101/MB91101A
Address
0028H
0029H
002AH
002BH
Register name
(abbreviated)
Register name
TMRLR0
16-bit reload register ch. 0
W
TMR0
16-bit timer register ch. 0
R
002CH
002FH
0030H
0031H
0032H
0033H
TMCSR0
16-bit reload timer control status register
ch. 0
TMRLR1
16-bit reload register ch. 1
W
TMR1
16-bit timer register ch. 1
R
0034H
0037H
0038H
0039H
003AH
003BH
003CH
003DH
003EH
003FH
16-bit reload timer control status register
ch. 1
ADCR
A/D converter data register
ADCS
A/D converter control status register
TMRLR2
16-bit reload register ch. 2
W
TMR2
16-bit timer register ch. 2
R
0044H
to
0077H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
––––0000B
00000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
R
R/W
––––0000B
00000000B
– – – – – – XXB
XXXXXXXXB
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Vacancy)
0041H
0043H
R/W
TMCSR1
0040H
0042H
XXXXXXXXB
(Vacancy)
0035H
0036H
Initial value
(Vacancy)
002DH
002EH
Read/write
TMCSR2
16-bit reload timer control status register
ch. 2
R/W
––––0000B
00000000B
(Vacancy)
(Continued)
27
MB91101/MB91101A
Address
0078H
0079H
Register name
(abbreviated)
UTIM0/UTIMR0
Register name
U-TIMER register ch. 0/reload register ch. 0
007AH
007BH
007CH
007DH
0080H
0081H
UTIMC0
U-TIMER control register ch. 0
R/W
UTIM1/UTIMR1
U-TIMER register ch. 1/reload register ch. 1
R/W
00000000B
00000000B
0––00001B
00000000B
00000000B
(Vacancy)
UTIMC1
U-TIMER control register ch. 1
R/W
UTIM2/UTIMR2
U-TIMER register ch. 2/reload register ch. 0
R/W
0082H
0083H
R/W
Initial value
(Vacancy)
007EH
007FH
Read/write
0––00001B
00000000B
00000000B
(Vacancy)
UTIMC2
U-TIMER control register ch. 2
0084H
to
0093H
R/W
0––00001B
(Vacancy)
0094H
EIRR
External interrupt cause register
R/W
00000000B
0095H
ENIR
Interrupt enable register
R/W
00000000B
R/W
00000000B
0096H
to
0098H
0099H
(Vacancy)
ELVR
External interrupt request level setting
register
009AH
to
00D1H
(Vacancy)
00D2H
DDRE
Port E data direction register
W
00000000B
00D3H
DDRF
Port F data direction register
W
00000000B
00D4H
to
00DBH
00DCH
00DDH
(Vacancy)
GCN1
General control register 1
00DEH
00DFH
R/W
00110010B
00010000B
(Vacancy)
GCN2
General control register 2
R/W
00000000B
(Continued)
28
MB91101/MB91101A
Address
00E0H
Register name
(abbreviated)
Register name
Read/write
Initial value
11111111B
PTMR0
Ch. 0 timer register
R
PCSR0
Ch. 0 cycle setting register
W
PDUT0
Ch. 0 duty setting register
W
00E6H
PCNH0
Ch. 0 control status register H
R/W
0000000–B
00E7H
PCNL0
Ch. 0 control status register L
R/W
00000000B
PTMR1
Ch. 1 timer register
R
PCSR1
Ch. 1 cycle setting register
W
PDUT1
Ch. 1 duty setting register
W
00EEH
PCNH1
Ch. 1 control status register H
R/W
0000000–B
00EFH
PCNL1
Ch. 1 control status register L
R/W
00000000B
PTMR2
Ch. 2 timer register
R
PCSR2
Ch. 2 cycle setting register
W
PDUT2
Ch. 2 duty setting register
W
00F6H
PCNH2
Ch. 2 control status register H
R/W
0000000–B
00F7H
PCNL2
Ch. 2 control status register L
R/W
00000000B
PTMR3
Ch. 3 timer register
R
PCSR3
Ch. 3 cycle setting register
W
PDUT3
Ch. 3 duty setting register
W
00FEH
PCNH3
Ch. 3 control status register H
R/W
0000000–B
00FFH
PCNL3
Ch. 3 control status register L
R/W
00000000B
00E1H
00E2H
00E3H
00E4H
00E5H
00E8H
00E9H
00EAH
00EBH
00ECH
00EDH
00F0H
00F1H
00F2H
00F3H
00F4H
00F5H
00F8H
00F9H
00FAH
00FBH
00FCH
00FDH
11111111B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
11111111B
11111111B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
11111111B
11111111B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
11111111B
11111111B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
29
MB91101/MB91101A
Address
Register name
(abbreviated)
0100H
to
01FFH
Register name
Read/write
(Vacancy)
0200H
0201H
0202H
Initial value
XXXXXXXXB
DPDP
DMAC parameter descriptor pointer
R/W
XXXXXXXXB
XXXXXXXXB
0203H
X0000000B
0204H
00000000B
0205H
0206H
DACSR
DMAC control status register
R/W
00000000B
00000000B
0207H
00000000B
0208H
XXXXXXXXB
0209H
020AH
DATCR
DMAC pin control register
R/W
020BH
(Vacancy)
03E4H
03E6H
––––––––B
ICHCR
Instruction cache control register
R/W
03E7H
––––––––B
(Vacancy)
03F0H
03F2H
––––––––B
––000000B
03E8H
to
03EFH
03F1H
XXXX 0 0 0 0 B
XXXX 0 0 0 0 B
020CH
to
03E3H
03E5H
XXXX 0 0 0 0 B
XXXXXXXXB
BSD0
Bit search module 0-detection data register
W
XXXXXXXXB
XXXXXXXXB
03F3H
XXXXXXXXB
03F4H
XXXXXXXXB
03F5H
03F6H
03F7H
BSD1
Bit search module 1-detection data register
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
30
MB91101/MB91101A
Address
Register name
(abbreviated)
Register name
Read/write
03F8H
03F9H
03FAH
Initial value
XXXXXXXXB
BSDC
Bit search module transition-detection data
register
W
XXXXXXXXB
XXXXXXXXB
03FBH
XXXXXXXXB
03FCH
XXXXXXXXB
03FDH
03FEH
BSRR
Bit search module detection result register
R
03FFH
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
0400H
ICR00
Interrupt control register 0
R/W
–––11111B
0401H
ICR01
Interrupt control register 1
R/W
–––11111B
0402H
ICR02
Interrupt control register 2
R/W
–––11111B
0403H
ICR03
Interrupt control register 3
R/W
–––11111B
0404H
ICR04
Interrupt control register 4
R/W
–––11111B
0405H
ICR05
Interrupt control register 5
R/W
–––11111B
0406H
ICR06
Interrupt control register 6
R/W
–––11111B
0407H
ICR07
Interrupt control register 7
R/W
–––11111B
0408H
ICR08
Interrupt control register 8
R/W
–––11111B
0409H
ICR09
Interrupt control register 9
R/W
–––11111B
040AH
ICR10
Interrupt control register 10
R/W
–––11111B
040BH
ICR11
Interrupt control register 11
R/W
–––11111B
040CH
ICR12
Interrupt control register 12
R/W
–––11111B
040DH
ICR13
Interrupt control register 13
R/W
–––11111B
040EH
ICR14
Interrupt control register 14
R/W
–––11111B
040FH
ICR15
Interrupt control register 15
R/W
–––11111B
0410H
ICR16
Interrupt control register 16
R/W
–––11111B
0411H
ICR17
Interrupt control register 17
R/W
–––11111B
0412H
ICR18
Interrupt control register 18
R/W
–––11111B
0413H
ICR19
Interrupt control register 19
R/W
–––11111B
0414H
ICR20
Interrupt control register 20
R/W
–––11111B
0415H
ICR21
Interrupt control register 21
R/W
–––11111B
0416H
ICR22
Interrupt control register 22
R/W
–––11111B
(Continued)
31
MB91101/MB91101A
Address
Register name
(abbreviated)
Register name
Read/write
Initial value
0417H
ICR23
Interrupt control register 23
R/W
–––11111B
0418H
ICR24
Interrupt control register 24
R/W
–––11111B
0419H
ICR25
Interrupt control register 25
R/W
–––11111B
041AH
ICR26
Interrupt control register 26
R/W
–––11111B
041BH
ICR27
Interrupt control register 27
R/W
–––11111B
041CH
ICR28
Interrupt control register 28
R/W
–––11111B
041DH
ICR29
Interrupt control register 29
R/W
–––11111B
041EH
ICR30
Interrupt control register 30
R/W
–––11111B
041FH
ICR31
Interrupt control register 31
R/W
–––11111B
042FH
ICR47
Interrupt control register 47
R/W
–––11111B
0430H
DICR
Delayed interrupt control register
R/W
–––––––0B
0431H
HRCL
Hold request cancel request level setting
register
R/W
–––11111B
0432H
to
047FH
(Vacancy)
0480H
RSRR/WTCR
Reset cause register/
watchdog peripheral control register
R/W
0481H
STCR
Standby control register
R/W
000111––B
0482H
PDRR
DMA controller request squelch register
R/W
––––0000B
0483H
CTBR
Timebase timer clear register
W
XXXXXXXX B
0484H
GCR
Gear control register
R/W
110011–1B
0485H
WPR
Watchdog reset occurrence postpone
register
W
XXXXXXXXB
R/W
00––0–––B
W
00000000B
W
00000000B
0486H
PCTR
0489H
to
0600H
0601H
0606H
0607H
PLL control register
(Vacancy)
DDR2
0602H
to
0604H
0605H
B
(Vacancy)
0487H
0488H
1X X X X – 0 0
Port 2 data direction register
(Vacancy)
DDR6
Port 6 data direction register
(Vacancy)
(Continued)
32
MB91101/MB91101A
Address
Register name
(abbreviated)
Register name
Read/write
Initial value
0608H
DDRB
Port B data direction register
W
00000000B
0609H
DDRA
Port A data direction register
W
–000000–B
––0––000B
060AH
060BH
(Vacancy)
DDR8
Port 8 data direction register
W
ASR1
Area select register 1
W
AMR1
Area mask register 1
W
ASR2
Area select register 2
W
AMR2
Area mask register 2
W
ASR3
Area select register 3
W
AMR3
Area mask register 3
W
ASR4
Area select register 4
W
AMR4
Area mask register 4
W
ASR5
Area select register 5
W
AMR5
Area mask register 5
W
0620H
AMD0
Area mode register 0
R/W
–––00111B
0621H
AMD1
Area mode register 1
R/W
0––00000B
0622H
AMD32
Area mode register 32
R/W
00000000B
0623H
AMD4
Area mode register 4
R/W
0––00000B
0624H
AMD5
Area mode register 5
R/W
0––00000B
0625H
DSCR
DRAM signal control register
W
00000000B
RFCR
Refresh control register
060CH
060DH
060EH
060FH
0610H
0611H
0612H
0613H
0614H
0615H
0616H
0617H
0618H
0619H
061AH
061BH
061CH
061DH
061EH
061FH
0626H
0627H
R/W
00000000B
00000001B
00000000B
00000000B
00000000B
00000010B
00000000B
00000000B
00000000B
00000011B
00000000B
00000000B
00000000B
00000100B
00000000B
00000000B
00000000B
00000101B
00000000B
00000000B
– – XXXXXXB
00–––000B
(Continued)
33
MB91101/MB91101A
(Continued)
Address
0628H
0629H
Register name
(abbreviated)
EPCR0
Register name
External pin control register 0
062AH
062BH
062CH
062DH
062EH
062FH
W
Initial value
––––1100B
–1111111B
(Vacancy)
EPCR1
External pin control register 1
DMCR4
DRAM control register 4
R/W
DMCR5
DRAM control register 5
R/W
0630H
to
07FDH
W
11111111B
00000000B
0000000–B
00000000B
0000000–B
(Vacancy)
07FEH
LER
Little endian register
W
–––––000B
07FFH
MODR
Mode register
W
XXXXXXXXB
Note: Do not use (vacancy).
34
Read/write
MB91101/MB91101A
■ INTERRUPT CAUSES, INTERRUPT VECTORS
AND INTERRUPT CONTROL REGISTER ALLOCATIONS
Interrupt number
Interrupt level
Decimal
Hexadecimal
Register
Offset
TBR default
address
Reset
0
00
—
3FCH
000FFFFCH
Reserved for system
1
01
—
3F8H
000FFFF8H
Reserved for system
2
02
—
3F4H
000FFFF4H
Reserved for system
3
03
—
3F0H
000FFFF0H
Reserved for system
4
04
—
3ECH
000FFFECH
Reserved for system
5
05
—
3E8H
000FFFE8H
Reserved for system
6
06
—
3E4H
000FFFE4H
Reserved for system
7
07
—
3E0H
000FFFE0H
Reserved for system
8
08
—
3DCH
000FFFDCH
Reserved for system
9
09
—
3D8H
000FFFD8H
Reserved for system
10
0A
—
3D4H
000FFFD4H
Reserved for system
11
0B
—
3D0H
000FFFD0H
Reserved for system
12
0C
—
3CCH
000FFFCCH
Reserved for system
13
0D
—
3C8H
000FFFC8H
Exception for undefined instruction
14
0E
—
3C4H
000FFFC4H
NMI request
15
0F
FH fixed
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
UART0 receive complete
20
14
ICR04
3ACH
000FFFACH
UART1 receive complete
21
15
ICR05
3A8H
000FFFA8H
UART2 receive complete
22
16
ICR06
3A4H
000FFFA4H
UART0 transmit complete
23
17
ICR07
3A0H
000FFFA0H
UART1 transmit complete
24
18
ICR08
39CH
000FFF9CH
UART2 transmit complete
25
19
ICR09
398H
000FFF98H
DMAC0 (complete, error)
26
1A
ICR10
394H
000FFF94H
DMAC1 (complete, error)
27
1B
ICR11
390H
000FFF90H
DMAC2 (complete, error)
28
1C
ICR12
38CH
000FFF8CH
DMAC3 (complete, error)
29
1D
ICR13
388H
000FFF88H
DMAC4 (complete, error)
30
1E
ICR14
384H
000FFF84H
DMAC5 (complete, error)
31
1F
ICR15
380H
000FFF80H
Interrupt causes
(Continued)
35
MB91101/MB91101A
Interrupt number
Interrupt level
Decimal
Hexadecimal
Register
Offset
TBR default
address
DMAC6 (complete, error)
32
20
ICR16
37CH
000FFF7CH
DMAC7 (complete, error)
33
21
ICR17
378H
000FFF78H
A/D converter (successive
approximation conversion type)
34
22
ICR18
374H
000FFF74H
16-bit reload timer 0
35
23
ICR19
370H
000FFF70H
16-bit reload timer 1
36
24
ICR20
36CH
000FFF6CH
16-bit reload timer 2
37
25
ICR21
368H
000FFF68H
PWM 0
38
26
ICR22
364H
000FFF64H
PWM 1
39
27
ICR23
360H
000FFF60H
PWM 2
40
28
ICR24
35CH
000FFF5CH
PWM 3
41
29
ICR25
358H
000FFF58H
U-TIMER 0
42
2A
ICR26
354H
000FFF54H
U-TIMER 1
43
2B
ICR27
350H
000FFF50H
U-TIMER 2
44
2C
ICR28
34CH
000FFF4CH
Reserved for system
45
2D
ICR29
348H
000FFF48H
Reserved for system
46
2E
ICR30
344H
000FFF44H
Reserved for system
47
2F
ICR31
340H
000FFF40H
Reserved for system
48
30
ICR32
33CH
000FFF3CH
Reserved for system
49
31
ICR33
338H
000FFF38H
Reserved for system
50
32
ICR34
334H
000FFF34H
Reserved for system
51
33
ICR35
330H
000FFF30H
Reserved for system
52
34
ICR36
32CH
000FFF2CH
Reserved for system
53
35
ICR37
328H
000FFF28H
Reserved for system
54
36
ICR38
324H
000FFF24H
Reserved for system
55
37
ICR39
320H
000FFF20H
Reserved for system
56
38
ICR40
31CH
000FFF1CH
Reserved for system
57
39
ICR41
318H
000FFF18H
Reserved for system
58
3A
ICR42
314H
000FFF14H
Reserved for system
59
3B
ICR43
310H
000FFF10H
Reserved for system
60
3C
ICR44
30CH
000FFF0CH
Reserved for system
61
3D
ICR45
308H
000FFF08H
Reserved for system
62
3E
ICR46
304H
000FFF04H
Delayed interrupt cause bit
63
3F
ICR47
300H
000FFF00H
Interrupt causes
(Continued)
36
MB91101/MB91101A
(Continued)
Interrupt number
Interrupt level
Decimal
Hexadecimal
Register
Offset
TBR default
address
Reserved for system (used in
REALOS*)
64
40
—
2FCH
000FFEFCH
Reserved for system (used in
REALOS*)
65
41
—
2F8H
000FFEF8H
Used in INT instructions
66
to
255
42
to
FF
—
2F4H
to
000H
000FFEF4H
to
000FFC00H
Interrupt causes
* : When using in REALOS/FR, interrupt 0x40, 0x41 for system code.
37
MB91101/MB91101A
■ PERIPHERAL RESOURCES
1. I/O Ports
There are 2 types of I/O port register structure; port data register (PDR0 to PDRF) and data direction register
(DDR0 to DDRF), where bits PDR0 to PDRF and bits DDR0 to DDRF corresponds respectively. Each bit on
the register corresponds to an external pin. In port registers input/output register of the port configures input/
output function of the port, while corresponding bit (pin) configures input/output function in data direction
registers. Bit “0” specifies input and “1” specifies output.
• For input (DDR = “0”) setting;
PDR reading operation: reads level of corresponding external pin.
PDR writing operation: writes set value to PDR.
• For output (DDR = “1”) setting;
PDR reading operation: reads PDR value.
PDR writing operation: outputs PDR value to corresponding external pin.
• Block diagram
Resource input
0
1
Data bus
PDR read
0
PDR
(Port data register)
Resource output
1
Resource output enable
DDR
(Data direction register)
38
Pin
MB91101/MB91101A
• Port data register
Address
bit 7
bit 0
Initial value
000001H
PDR2
XXXXXXXX
B
(R/W)
000005H
PDR6
XXXXXXXX
B
(R/W)
00000BH
PDR8
- - X - - XXX
B
(R/W)
000009H
PDRA
- XXXXXX -
B
(R/W)
000008H
PDRB
XXXXXXXX
B
(R/W)
000012H
PDRE
XXXXXXXX
B
(R/W)
000013H
PDRF
XXXXXXXX
B
(R/W)
( ) : Access
R/W : Readable and writable
X : Indeterminate
• Data direction register
Address
bit 7
bit 0
Initial value
000601H
DDR2
00000000
B
(W)
000605H
DDR6
00000000
B
(W)
00060BH
DDR8
- - 0 - - 000
B
(W)
000609H
DDRA
- 000000 -
B
(W)
000608H
DDRB
00000000
B
(W)
0000D2H
DDRE
00000000
B
(W)
0000D3H
DDRF
00000000
B
(W)
( ) : Access
W : Write only
– : Unused
39
MB91101/MB91101A
2. DMA Controller (DMAC)
The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access)
transfer.
DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to
enhanced performance of the system.
•
•
•
•
•
•
•
8 channels
Mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer
Transfer all through the area
Max. 65536 of transfer cycles
Interrupt function right after the transfer
Selectable for address transfer increase/decrease by the software
External transfer request input pin, external transfer request accept output pin, external transfer complete
output pin three pins for each
• Block diagram
DREQ0 to DREQ2
3
Edge/level
detection circuit
3
3
DACK0 to DACK2
3
Sequencer
EOP0 to EOP2
8
Interrupt request
5
Inner resource
Transfer request
Data buffer
Switcher
DACSR
DATCR
Mode
BLK DEC
BLK
DMACT
INC / DEC
SADR
DADR
40
Data bus
DPDP
MB91101/MB91101A
• Registers (DMAC internal registers)
Address
00000200H
00000201H
00000202H
00000203H
Initial value
bit 31
XXXXXXXX
XXXXXXXX
XXXXXXXX
X0000000
B
0
0
0
0
B
DACSR
0
0
0
0
B
DATCR
XXXXXXXX
XXXX0 0 0 0
XXXX0 0 0 0
XXXX0 0 0 0
bit 16
bit 0
DPDP
00000204H
00000205H
00000206H
00000207H
00000208H
00000209H
0000020AH
0000020BH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B
B
(R/W)
B
B
B
(R/W)
B
B
B
(R/W)
B
( ) : Access
R/W : Readable and writable
X : Indeterminate
• Registers (DMA descriptor)
Address
DPDP + 0H
bit 31
bit 0
DMA
ch.0
Descriptor
DPDP + 0CH
DMA
ch.1
Descriptor
DPDP + 54H
DMA
ch.7
Descriptor
41
MB91101/MB91101A
3. UART
The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK
synchronous communication, and it has the following features.
The MB91101 consists of 3 channels of UART.
•
•
•
•
•
•
•
•
42
Full double double buffer
Both a synchronous (start-stop system) communication and CLK synchronous communication are available.
Supporting multi-processor mode
Perfect programmable baud rate
Any baud rate can be set by internal timer (refer to section “4. U-TIMER”).
Any baud rate can be set by external clock.
Error checking function (parity, framing and overrun)
Transfer signal: NRZ code
Enable DMA transfer/start by interrupt.
MB91101/MB91101A
• Block diagram
Control signals
Receive interrupt
(to CPU)
SC (clock)
Transmit interrupt
(to CPU)
Transmit clock
From U-TIMER
Clock select
circuit
Receive clock
From external clock
SC
SI
(receive data)
Receive control circuit
Transmit control circuit
Start bit detect
circuit
Transmit start
circuit
Receive bit counter
Transmit bit counter
Receive parity
counter
Transmit parity
counter
SO (transmit data)
Receive status
judge circuit
Receive shifter
Receive error
generate signal
for DMA
(to DMAC)
Transmit shifter
Receive
complete
Transmit
start
SODR
SIDR
R-bus
MD1
MD0
SMR
register
SCR
register
CS0
SCKE
SOE
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Control signals
43
MB91101/MB91101A
• Register configuration
Address
bit 8
bit 0
Initial value
0000001EH
SCR0
00000100
B
(R/W)
00000022H
SCR1
00000100
B
(R/W)
00000026H
SCR2
00000100
B
(R/W)
0000001FH
SMR0
00 - - 0 - 00
B
(R/W)
00000023H
SMR1
00 - - 0 - 00
B
(R/W)
00000027H
SMR2
00 - - 0 - 00
B
(R/W)
0000001CH
SSR0
00001 - 00
B
(R/W)
00000020H
SSR1
00001 - 00
B
(R/W)
00000024H
SSR2
00001 - 00
B
(R/W)
0000001DH
SIDR0/SODR0
XXXXXXXX
B
(R/W)
00000021H
SIDR1/SIDR1
XXXXXXXX
B
(R/W)
00000002H
SIDR2/SIDR2
XXXXXXXX
B
(R/W)
()
R/W
–
X
44
bit 15
:
:
:
:
Access
Readable and writable
Unused
Indeterminate
MB91101/MB91101A
4. U-TIMER (16-bit Timer for UART Baud Rate Generation)
The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and
reload value of U-TIMER allows flexible setting of baud rate.
The U-TIMER operates as an interval timer by using interrupt issued on counter underflow.
The MB91101 has 3 channel U-TIMER embedded on the chip. An interval of up to 216 × φ can be counted.
• Block diagram
bit 15
bit 0
UTIMR (reload register)
Load
bit 15
bit 0
UTIM ( U-TIMER register)
Underflow
Clock
φ
(Peripheral clock)
Control
f.f.
To UART
• Register configuration
Address
bit 15
bit 0
00000078H
00000079H
UTIM0/UTIMR0
0000007CH
0000007DH
UTIM1/UTIMR1
00000080H
00000081H
UTIM2/UTIMR2
0000007BH
0000007FH
00000083H
Initial value
(R/W)
00000000
00000000
B
00000000
00000000
B
00000000
00000000
B
UTIMC0
0 - - 00001
B
(R/W)
UTIMC1
0 - - 00001
B
(R/W)
UTIMC2
0 - - 00001
B
(R/W)
B
(R/W)
B
(R/W)
B
( ) : Access
R/W : Readable and writable
– : Unused
45
MB91101/MB91101A
5. PWM Timer
The PWM timer can output high accurate PWM waves efficiently.
MB91101 has inner 4-channel PWM timers, and has the following features.
• Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for scyde setting, a 16bit compare resister with a buffer for duty setting, and a pin controller.
• The count clock of a 16-bit down counter can be selected from the following four inner clocks.
Inner clock φ, φ/4, φ/16, φ/64
• The counter value can be initialized “FFFFH” by the resetting or the counter borrow.
• PWM output (each channel)
• Resister description
• Block diagram (general construction)
16-bit reload timer
ch.0
16-bit reload timer
ch.1
General control
register 2
General control
register 1
(cause selection)
4
4
External TRG0 to TRG3
46
TRG input
PWM timer ch.0
PWM0
TRG input
PWM timer ch.1
PWM1
TRG input
PWM timer ch.2
PWM2
TRG input
PWM timer ch.3
PWM3
MB91101/MB91101A
• Block diagram (for one channel)
PDUT
PCSR
Prescaler
1/1
1/4
1 / 16
1 / 64
cmp
ck
Load
16-bit down counter
Start
Borrow
PPG mask
S
Peripheral clock
Q
PWM output
R
Enable
TRG input
Edge detect
Interrupt
selection
Reverse bit
IRQ
Soft trigger
47
MB91101/MB91101A
• Register configuration
Address
Initial value
bit 15
bit 8
000000DCH
000000DDH
GCN1
000000DFH
GCN2
00110010
00010000
B
00000000
B
(R/W)
(R)
B
(R/W)
000000E0H
000000E1H
PTMR0
11111111
11111111
B
000000E2H
000000E3H
PCSR0
XXXXXXXX
XXXXXXXX
B
000000E4H
000000E5H
PDUT0
XXXXXXXX
XXXXXXXX
B
0000000 -
B
(R/W)
00000000
B
(R/W)
(R)
000000E6H
PCNH0
000000E7H
PCNL0
B
B
B
(W)
(W)
000000E8H
000000E9H
PTMR1
11111111
11111111
B
000000EAH
000000EBH
PCSR1
XXXXXXXX
XXXXXXXX
B
000000ECH
000000EDH
PDUT1
XXXXXXXX
XXXXXXXX
B
0000000 -
B
(R/W)
00000000
B
(R/W)
000000EEH
PCNH1
PCNL1
000000EFH
B
B
B
(W)
(W)
000000F0H
000000F1H
PTMR2
11111111
11111111
B
000000F2H
000000F3H
PCSR2
XXXXXXXX
XXXXXXXX
B
000000F4H
000000F5H
PDUT2
XXXXXXXX
XXXXXXXX
B
0000000 -
B
(R/W)
00000000
B
(R/W)
(R)
000000F6H
PCNH2
PCNL2
000000F7H
B
B
B
(R)
(W)
(W)
000000F8H
000000F9H
PTMR3
11111111
11111111
B
000000FAH
000000FBH
PCSR3
XXXXXXXX
XXXXXXXX
B
000000FCH
000000FDH
PDUT3
XXXXXXXX
XXXXXXXX
B
0000000 -
B
(R/W)
00000000
B
(R/W)
000000FEH
PCNH3
000000FFH
()
R/W
R
W
–
X
48
bit 0
:
:
:
:
:
:
Access
Readable and writable
Read only
Write only
Unused
Indeterminate
PCNL3
B
B
B
(W)
(W)
MB91101/MB91101A
6. 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating
internal count clock and control registers.
Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock).
The DMA transfer can be started by the interruption.
The MB91101 consists of 3 channels of the 16-bit reload timer.
• Block diagram
16
16-bit reload register
8
Reload
RELD
16
OUTE
16-bit down counter UF
OUTL
2
OUT
CTL.
R-bus
GATE
INTE
2
IRQ
UF
CSL1
Clock selector
CNTE
CSL0
TRG
2
Retrigger
IN CTL.
EXCK
φ φ φ
– – –
21 2 3 2 5
PWM (ch.0, ch.1)
A/D (ch.2)
3
Prescaler
clear
MOD2
MOD1
Internal clock
MOD0
3
49
MB91101/MB91101A
• Register configuration
Address
bit 15
Initial value
0000002EH
0000002FH
TMCSR0
- - - - 0000
00000000
B
00000036H
00000037H
TMCSR1
- - - - 0000
00000000
B
00000042H
00000043H
TMCSR2
- - - - 0000
00000000
B
0000002AH
0000002BH
TMR0
XXXXXXXX
XXXXXXXX
B
00000032H
00000033H
TMR1
XXXXXXXX
XXXXXXXX
B
0000003EH
0000003FH
TMR2
XXXXXXXX
XXXXXXXX
B
TMRLR0
XXXXXXXX
XXXXXXXX
B
00000030H
00000031H
TMRLR1
XXXXXXXX
XXXXXXXX
B
0000003CH
0000003DH
TMRLR2
XXXXXXXX
XXXXXXXX
B
00000028H
00000029H
()
R/W
R
W
–
X
50
bit 0
:
:
:
:
:
:
Access
Readable and writable
Read only
Write only
Unused
Indeterminate
B
B
B
(R/W)
(R/W)
(R/W)
(R)
B
(R)
B
B
B
B
B
(R)
(W)
(W)
(W)
MB91101/MB91101A
7. Bit Search Module
The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and
returns locations of the transitions.
• Block diagram
Input latch
Detection
mode
D-bus
Address
decoder
Single-detection data recovery
Bit search circuit
Search result
• Register configuration
Address
bit 31
bit 16
bit 0
Initial value
000003F0H
000003F1H
000003F2H
000003F3H
BSD0
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(W)
000003F4H
000003F5H
000003F6H
000003F7H
BSD1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(W)
000003F8H
000003F9H
000003FAH
000003FBH
BSDC
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(W)
000003FCH
000003FEH
000003FDH
000003FFH
BSRR
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(W)
()
R/W
R
W
X
:
:
:
:
:
Access
Readable and writable
Read only
Write only
Indeterminate
51
MB91101/MB91101A
8. 10-bit A/D Converter (Successive Approximation Conversion Type)
The A/D converter is the module which converts an analog input voltage to a digital value, and it has following
features.
Minimum converting time: 5.6 µs/ch. (system clock: 25 MHz)
Inner sample and hold circuit
Resolution: 10 bits
Analog input can be selected from 4 channels by program.
Single convert mode: 1 channel is selected and converted.
Scan convert mode: Converting continuous channels. Maximum 4 channels are programmable.
Continuous convert mode: Converting the specified channel repeatedly.
Stop convert mode: After converting one channel then stop and wait till next activation synchronising at
the beginning of conversion can be peformed.
• DMA transfer operation is available by interruption.
• Operating factor can be selected from the software, the external trigger (falling edge), and 16-bit reroad timer
(rising edge).
•
•
•
•
• Block diagram
AVCC
AVR
AVSS
Internal voltage generator
MPX
AN0
AN2
Successive approximation
register
Input circuit
AN1
Comparator
AN3
Decoder
R-bus
Sample & hold circuit
Data register (ADCR)
A/D control register (ADCS)
Trigger start
ATG
TIM0
(internal connection)
(16-bit reload timer ch.2)
φ
(Peripheral clock)
52
Timer start
Operating clock
Prescaler
MB91101/MB91101A
• Register configuration
Address
bit 15
bit 0
Initial value
0000003AH
0000003BH
ADCS
00000000
00000000
B
00000038H
00000039H
ADCR
- - - - - - XX
XXXXXXXX
B
()
R/W
R
–
X
:
:
:
:
:
B
B
(R/W)
(R)
Access
Readable and writable
Read only
Unused
Indeterminate
53
MB91101/MB91101A
9. Interrupt Controller
The interrupt controller processes interrupt acknowledgments and arbitration between interrupts.
• Block diagram
INT0*2
IM
Priority judgment
OR
5
NMI
5
NMI processing
4
Level judgment
ICR00
RI00
•
•
•
6
•
•
•
Vector judgment
6
HLDCAN*3
VCT5 to
VCT0*5
ICR47
RI47
(DLYIRQ)
•
•
Level
vector
generation
HLDREQ
cancel
request
LEVEL4 to
LEVEL0*4
DLYI*1
R-bus
*1: DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section “11. Delayed Interrupt
Module” for detail).
*2: INT0 is a wake-up signal to clock control block in the sleep or stop status.
*3: HLDCAN is a bus release request signal for bus masters other than CPU.
*4: LEVEL5 to LEVEL0 are interrupt level outputs.
*5: VCT5 to VCT0 are interrupt vector outputs.
54
MB91101/MB91101A
• Register configuration
Address
bit 7
bit 0
Initial value
Address
bit 7
bit 0
Initial value
00000400H
ICR00
- - - 11111 B (R/W)
00000411H
ICR17
- - - 11111 B (R/W)
00000401H
ICR01
- - - 11111 B (R/W)
00000412H
ICR18
- - - 11111 B (R/W)
00000402H
ICR02
- - - 11111 B (R/W)
00000413H
ICR19
- - - 11111 B (R/W)
00000403H
ICR03
- - - 11111 B (R/W)
00000414H
ICR20
- - - 11111 B (R/W)
00000404H
ICR04
- - - 11111 B (R/W)
00000415H
ICR21
- - - 11111 B (R/W)
00000405H
ICR05
- - - 11111 B (R/W)
00000416H
ICR22
- - - 11111 B (R/W)
00000406H
ICR06
- - - 11111 B (R/W)
00000417H
ICR23
- - - 11111 B (R/W)
00000407H
ICR07
- - - 11111 B (R/W)
00000418H
ICR24
- - - 11111 B (R/W)
00000408H
ICR08
- - - 11111 B (R/W)
00000419H
ICR25
- - - 11111 B (R/W)
00000409H
ICR09
- - - 11111 B (R/W)
0000041AH
ICR26
- - - 11111 B (R/W)
0000040AH
ICR10
- - - 11111 B (R/W)
0000041BH
ICR27
- - - 11111 B (R/W)
0000040BH
ICR11
- - - 11111 B (R/W)
0000041CH
ICR28
- - - 11111 B (R/W)
0000040CH
ICR12
- - - 11111 B (R/W)
0000041DH
ICR29
- - - 11111 B (R/W)
0000040DH
ICR13
- - - 11111 B (R/W)
0000041EH
ICR30
- - - 11111 B (R/W)
0000040EH
ICR14
- - - 11111 B (R/W)
0000041FH
ICR31
- - - 11111 B (R/W)
0000040FH
ICR15
- - - 11111 B (R/W)
0000042FH
ICR47
- - - 11111 B (R/W)
00000410H
ICR16
- - - 11111 B (R/W)
00000431H
HRCL
- - - 11111 B (R/W)
00000430H
DICR
- - - - - - - 0 B (R/W)
( ) : Access
R/W : Redable and writable
– : Unused
55
MB91101/MB91101A
10. External Interrupt/NMI Control Block
The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INT0
to INT3 pins.
Detecting levels can be selected from “H”, “L”, rising edge and falling edge (not for NMI pin).
• Block diagram
8
Interrupt enable register
9
5
Gate
R-bus
Interrupt
request
Cause F/F
INT0 to INT3
NMI
Edge detection circuit
8
Interrupt cause register
8
Request level setting register
• Register configuration
Address
bit 15
bit 8
ENIR
00000095H
00000094H
EIRR
00000099H
( ) : Access
R/W : Redable and writable
56
bit 0
ELVR
Initial value
00000000 B
(R/W)
00000000 B
(R/W)
00000000 B
(R/W)
MB91101/MB91101A
11. Delayed Interrupt Module
Delayed interrupt module is a module which generates a interrupt for changing a task. By using this delayed
interrupt module, an interrupt request to CPU can be generated/cancelled by the software.
Refer to the section “9. Interrupt Controller” for delayed interrupt module block diagram.
• Register configuration
Address
bit 7
00000430H
bit 0
DICR
Initial value
- - - - - - - 0
B
(R/W)
( ) : Access
R/W : Redable and writable
– : Unused
57
MB91101/MB91101A
12. Clock Generation (Low-power consumption mechanism)
The clock control block is a module which undertakes the following functions.
•
•
•
•
•
•
CPU clock generation (including gear function)
Peripheral clock generation (including gear function)
Reset generation and cause hold
Standby function (including hardware standby)
DMA request prohibit
PLL (multiplier circuit) embedded
• Block diagram
[Gear control block]
Gear control register (GCR)
X0
X1
Oscillator
circuit
PCTR register
PLL
1/2
Internal
interrupt request
Internal reset
Peripheral
gear
Selection
circuit
R-bus
CPU gear
CPU clock
Internal bus clock
External bus clock
Peripheral
DMA clock
Internal
peripheral clock
Internal clock
generation
circuit
[Stop/sleep control block]
Standby control
register (STCR)
STOP state
Status
transition
control circuit
CPU hold enable
HST pin
SLEEP state
CPU hold request
Reset
generation
F/F
[DMA prohibit circuit]
DMA
request
DMA request prohibit
register (PDRR)
[Reset cause circuit]
Power on sel
RST pin
Reset cause register (RSRR)
[Watchdog control block]
Watchdog reset generation
postpone register (WPR)
Watchdog reset
postpone register
Timebase timer clear
register (CTBR)
Timebase timer
58
Count clock
Internal reset
MB91101/MB91101A
• Register configuration
Address
00000480H
bit 15
bit 8
RSRR/WTCR
00000481H
00000482H
STCR
PDRR
00000483H
00000484H
CTBR
GCR
00000485H
00000488H
()
R/W
W
–
X
:
:
:
:
:
bit 0
WPR
PCTR
Initial value
1XXXX - 0 0
B
(R/W)
000111 - -
B
(R/W)
- - - - 0000
B
(R/W)
XXXXXXXX
B
(W)
110011 - 1
B
(R/W)
XXXXXXXX
B
(W)
00 - - 0 - - -
B
(R/W)
Access
Redable and writable
Write only
Unused
Indeterminate
59
MB91101/MB91101A
13. External Bus Interface
The external bus interface controls the interface between the device and the external memory and also the
external I/O, and has the following features.
• 25-bit (32 Mbytes) address output
• 6 independent banks owing to the chip select function.
Can be set to anywhere on the logical address space for minimum unit 64 Kbytes.
Total 32 Mbytes × 6 area setting is available by the address pin and the chip select pin.
• 8/16-bit bus width setting are available for every chip select area.
• Programmable automatic memory wait (max. for 7 cycles) can be inserted.
• DRAM interface support
Three kinds of DRAM interface: Double CAS DRAM (normally DRAM I/F)
Single CAS DRAM
Hyper DRAM
2 banks independent control (RAS, CAS, etc. control signals)
DRAM select is available from 2CAS/1WE and 1CAS/2WE.
Hi-speed page mode supported
CBR/self refresh supported
Programmable wave form
• Unused address/data pin can be used for I/O port.
• Little endian mode supported
• Clock doubler: Internal bus 50 MHz, external bus 25 MHz
60
MB91101/MB91101A
• Block diagram
Address bus
32
A-OUT
Data bus
32
External data bus
Write buffer
Switch
Read buffer
Switch
MUX
DATA BLOCK
ADDRESS BLOCK
+1 or +2
External address bus
Inpage
Shifter
Address buffer
6
ASR
AMR
CS0 to CS5
Comparator
8
DRAM control
RAS0, RAS1
CS0L, CS1L
CS0H, CS1H
DW0, DW1
Underflow
DMCR
Refresh counter
To TBT
3
External pin control block
All blocks control
4
Registers and control
RD
WR0, WR1
BRQ
BGRNT
CLK
RDY
61
MB91101/MB91101A
• Register configuration
Address
Initial value
bit 31
bit 16
0000060CH
0000060DH
bit 0
ASR1
0000060EH
0000060FH
AMR1
00000610H
00000611H
ASR2
00000612H
00000613H
AMR2
00000614H
00000615H
ASR3
00000616H
00000617H
AMR3
00000618H
00000619H
ASR4
0000061AH
0000061BH
AMR4
0000061CH
0000061DH
ASR5
0000061EH
0000061FH
00000620H
AMR5
AMD0
00000621H
AMD1
00000622H
AMD32
00000623H
00000624H
AMD4
AMD5
00000625H
DSCR
00000626H
00000627H
00000628H
00000629H
RFCR
EPCR0
EPCR1
0000062BH
0000062CH
0000062DH
DMCR4
0000062EH
0000062FH
000007FEH
000007FFH
()
R/W
W
–
X
62
:
:
:
:
:
Access
Redable and writable
Write only
Unused
Indeterminate
DMCR5
LER
MODR
00000000
00000001
B
00000000
00000000
B
00000000
00000010
B
00000000
00000000
B
00000000
00000011
B
00000000
00000000
B
00000000
00000100
B
00000000
00000000
B
00000000
00000101
B
00000000
00000000
B
- - - 00111
B
(R/W)
0 - - 00000
B
(R/W)
00000000
B
(R/W)
0 - - 00000
B
(R/W)
0 - - 00000
B
(R/W)
00000000
B
(W)
- - XXXXXX
00 - - - 000
B
(R/W)
- - - - 1100
- 1111111
B
11111111
B
(W)
00000000
0000000 -
B
(R/W)
00000000
0000000 -
B
- - - - - 000
B
(W)
XXXXXXXX
B
(W)
B
B
B
B
B
B
B
B
B
B
B
B
B
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(R/W)
B
MB91101/MB91101A
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min.
Max.
VCC5
VSS – 0.3
VSS + 6.5
V
VCC3
—
—
V
VCC5
VCC3 – 0.3
VSS + 6.5
V
*1
VCC3
VSS – 0.3
VSS + 3.6
V
*1
Analog supply voltage
AVCC
VSS – 0.3
VSS + 3.6
V
*2
Analog reference voltage
AVRH
VSS – 0.3
VSS + 3.6
V
*2
Analog pin input voltage
VIA
VSS – 0.3
AVCC + 0.3
V
Input voltage
VI
VSS – 0.3
VCC5 + 0.3
V
Output voltage
VO
VSS – 0.3
VCC5 + 0.3
V
“L” level maximum output current
IOL
—
10
mA
*3
“L” level average output current
IOLAV
—
4
mA
*4
“L” level maximum total output current
ΣIOL
—
100
mA
“L” level average total output current
ΣIOLAV
—
50
mA
*5
“H” level maximum output current
IOH
—
–10
mA
*3
“H” level average output current
IOHAV
—
–4
mA
*4
“H” level maximum total output current
ΣIOH
—
–50
mA
“H” level average total output current
ΣIOHAV
—
–20
mA
Power consumption
PD
—
500
mW
Operating temperature
TA
0
+70
°C
Storage temperature
Tstg
–55
+150
°C
At 5 V power supply
Power supply
voltage
At 3 V power supply
*1:
*2:
*3:
*4:
*5:
*5
VCC5 must not be less than VSS – 0.3 V.
Make sure that the voltage does not exceed VCC5 + 0.3 V, such as when turning on the device.
Maximum output current is a peak current value measured at a corresponding pin.
Average output current is an average current for a 100 ms period at a corresponding pin.
Average total output current is an average current for a 100 ms period for all corresponding pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
63
MB91101/MB91101A
2. Recommended Operating Conditions
(1) At 5 V operation (4.5 V to 5.5 V)
(VSS = AVSS = 0.0 V)
Value
Symbol
Parameter
Unit
Remarks
Min.
Max.
VCC5
4.5
5.5
V
Normal operation
VCC5
*1
*1
V
Retaining the RAM state in
stop mode
VCC3
—
—
V
*2
Analog supply voltage
AVCC
VSS + 2.7
VCC + 3.6
V
Analog reference voltage
AVRH
VSS – 0.3
AVCC
V
Operating temperature
TA
0
+70
°C
Smoothing capacitor
CS
0.1
1.0
µF
Power supply voltage
VCC3 pin *2
*1: At VCC5, the RAM state holding is not warranted in stop mode.
*2: VCC3 is used for the bypass capacitor pin.
*3: Use the ceramic capacitor or the capacitor whose frequency characteristic is equivalent to that of the ceramic
capacitor.
And select the larger capacity smoothing condenser to connect to the power supply (VCC5) than CS.
(2) At 3 V operation (2.7 V to 3.6 V)
(VSS = AVSS = 0.0 V)
Value
Symbol
Parameter
Unit
Remarks
Min.
Max.
VCC5
2.7
3.6
V
Normal operation
VCC5
2.7
3.6
V
Retaining the RAM state in
stop mode
VCC3
2.7
3.6
V
*
Analog power supply voltage
AVCC
VSS + 2.7
VCC + 3.6
V
Analog reference voltage
AVRH
AVSS
AVCC
V
Operating temperature
TA
0
+70
°C
Power supply voltage
* : Connect to VCC5 for the power supply pin.
• Connecting to a power supply
Using with 3 V power supply
Using with 5 V power supply
3V
5V
3V
VCC5
AVCC
AVRH
AVSS
VSS
GND
64
VCC3
VCC5
AVCC
About
0.1 µF
AVRH
AVSS
GND
VSS
VCC3
MB91101/MB91101A
VCC (V)
Normal operation warranty range (TA = 0°C to +70°C)
Net masked area are fCPP.
Power supply at 5 V
Supply voltage
5.5
4.5
3.0 V ±0.3 V
Power supply at 3 V
3.6
3.3
3.0
2.7
3.3 V ±0.3 V
0
25
Internal clock
0.625
40
50
fCP/fCPP
(MHz)
Max. internal clock frequency setting
fCP/fCPP
(MHz)
fCP
50
CPU
40
fCPP
PLL system (4 multiplication)
25
Peripheral
20
Divide-by-2 system
12.5
5
0
0
10 12.5
25
50
External clock
fC
(MHz)
Source oscillating input clock
Self-oscillation
Notes: • When using PLL, the external clock must be used between 10.0 MHz to 12.5 MHz.
• PLL oscillation stabilizing period > 100 µs
• The setting of internal clock must be within above ranges.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
65
MB91101/MB91101A
3. DC Characteristics
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol
Pin name
Condition
VIH
Input pin except
for hysteresis
input
Value
Unit
Remarks
Min.
Typ.
Max.
—
0.65 × VCC3
—
VCC5 + 0.3
V
*
VIHS
HST, NMI, RST,
PA1 to PA6,
PB0 to PB7,
PE0 to PE7,
PF0 to PF7
—
0.8 × VCC3
—
VCC5 + 0.3
V
Hysteresis
input *
VIL
Input other than
following
symbols
—
VSS – 0.3
—
0.25 × VCC3
V
*
VILS
HST, NMI, RST,
PA1 to PA6,
PB0 to PB7,
PE0 to PE7,
PF0 to PF7
—
VSS – 0.3
—
0.2 × VCC3
V
Hysteresis
input *
“H” level input
voltage
“L” level input
voltage
“H” level output
VOH
voltage
D16 to D31,
A00 to A24,
P6 to PF
VCC5 = 4.5 V
IOH = –4.0 mA
VCC – 0.5
—
—
V
“L” level output
voltage
D16 to D31,
A00 to A24,
P6 to PF
VCC5 = 4.5 V
IOL = 4.0 mA
—
—
0.4
V
Input leakage
current
ILI
(Hi-Z output
leakage current)
D00 to D31,
A00 to A23,
P8 to PF
VCC5 = 5.5 V
0.45 V < VI
< VCC
–5
—
+5
µA
Pull-up
resistance
RPULL
RST
VCC5 = 5.5 V
VI = 0.45 V
25
50
100
kΩ
ICC
VCC
FC = 12.5 MHz
VCC5 = 5.5 V
—
75
100
mA Operation at
50 MHz
ICCS
VCC
FC = 12.5 MHz
VCC5 = 5.5 V
—
40
60
mA Sleep mode
ICCH
VCC
TA = +25°C
VCC5 = 5.5 V
—
10
100
µA Stop mode
CIN
Except for
VCC5, VCC3,
AVCC, AVSS, VSS
—
10
—
Power supply
current
Input
capacitance
VOL
—
(4 multiplication)
pF
* : VCC3 = 3.3 ±0.2 V (internal regulator output voltage) when using 5 V power supply, VCC3 = power supply voltage
when using 3 V power supply (internal regulator unused)
66
MB91101/MB91101A
4. AC Characteristics
Measurement Conditions
• VCC = 5.0 V ±10%
Parameter
Symbol
Value
Min.
Typ.
Max.
Unit
“H” level input voltage
VIH
—
2.4
—
V
“L” level input voltage
VIL
—
0.8
—
V
“H” level output voltage
VOH
—
2.4
—
V
“L” level output voltage
VOL
—
0.8
—
V
VCC
Input
Remarks
Output
VIH
VOH
VIL
VOL
0.0 V
• VCC = 2.7 V to 3.6 V
Parameter
Symbol
Value
Min.
Typ.
Max.
Unit
“H” level input voltage
VIH
—
1/2 × VCC
—
V
“L” level input voltage
VIL
—
1/2 × VCC
—
V
“H” level output voltage
VOH
—
1/2 × VCC
—
V
“L” level output voltage
VOL
—
1/2 × VCC
—
V
VCC
Input
Remarks
Output
VIH
VOH
VIL
VOL
0.0 V
• Load conditions
Output pin
C = 50 pF
(VCC = 5.0V ± 10%)
67
MB91101/MB91101A
• Load capacitance - Delay characteristics (Output delay with reference to the internal)
(ns)
35
5 V Fall
30
3 V Rise
25
20
15
5 V Rise
10
5
3 V Fall
0
0
68
20
40 50 60
80
100
120 C (pF)
MB91101/MB91101A
(1) Clock Timing Rating
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Symbol
Parameter
Clock frequency
Clock cycle time
Frequency shift ratio
(when locked)
Input clock pulse width
Input clock rising/falling time
Internal operating clock
frequency
Internal operating clock
cycle time
Pin
name
Condition
Value
Min.
Max.
Unit
Remarks
fC
X0, X1
When using PLL
10
12.5
MHz
fC
X0, X1
Self-oscillation
(divide-by-2 input)
10
25
MHz
fC
X0, X1
External clock
(divide-by-2 input)
10
25
MHz
tC
X0, X1
When using PLL
80
100
ns
tC
X0, X1
40
100
ns
∆f
—
—
5
%
*1
—
When using PLL
25
—
ns
Input to X0
only, when
using 5 V
power supply
X0, X1
10
—
ns
Input to X0,
X1
tCR,
tCF
X0, X1
—
8
ns
(tCR + tCF)
fCP
—
CPU system
fCPB
—
fCPP
PWH,
PWL
X0, X1
PWH,
PWL
—
0.625*2
50
MHz
Bus system
2
0.625*
25*
—
Peripheral system
0.625*2
25
MHz
tCP
—
CPU system
20
1600*2
ns
tCPB
—
Bus system
40*3
1600*2
ns
tCPP
—
Peripheral system
40
1600*2
ns
3
MHz
*1: Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock
multiplication system.
+
+α
∆f
=
|α|
× 100 (%)
f0
Center frequency f 0
–α
–
*2: These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation and
a 1/8 gear.
*3: Values when using the doubler and CPU operation at 50 MHz.
69
MB91101/MB91101A
• Clock timing rating measurement conditions
tC
0.8 VCC
0.2 VCC
PWH
PWL
tCF
70
tCR
MB91101/MB91101A
(2) Clock Output Timing
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol Pin name
tCYC
CLK
tCYC
CLK
CLK ↑ → CLK ↓
tCHCL
CLK
CLK ↓ → CLK ↑
tCLCH
CLK
Cycle time
Value
Condition
—
Using the
doubler
—
Unit
Min.
Max.
tCP
—
ns
tCPB
—
ns
Remarks
*1
1/2 × tCYC – 10 1/2 × tCYC + 10
ns
*2
1/2 × tCYC – 10 1/2 × tCYC + 10
ns
*3
tCP, tCPB (internal operating clock cycle time): Refer to “(1) Clock Timing Rating.”
*1: tCYC is a frequency for 1 clock cycle including a gear cycle.
Use the doubler when CPU frequency is above 25 MHz.
*2: Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8,
respectively.
Min. : (1 – n/2) × tCYC – 10
Max. : (1 – n/2) × tCYC + 10
Select a gear cycle of × 1 when using the doubler.
*3: Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8,
respectively.
Min. : n/2 × tCYC – 10
Max. : n/2 × tCYC + 10
Select a gear cycle of × 1 when using the doubler.
tCYC
tCLCH
tCHCL
CLK
VOH
VOH
VOL
71
MB91101/MB91101A
The relation between source oscillation input and CLK pin for configured by CHC/CCK1/CCK0 settings of GCR
(gear control register) is as follows:
However, in this chart source oscillation input means X0 input clock.
Source oscillation input
(when using the doublure)
(1) PLL system
(CHC bit of GCR set to “0”)
(a) Gear × 1 CLK pin
CCK1/0: “00”
tCYC
Source oscillation input
(2) 2 dividing system
(CHC bit of GCR set to “1”)
(a) Gear × 1 CLK pin
CCK1/0: “00”
(b) Gear × 1/2 CLK pin
CCK1/0: “01”
(c) Gear × 1/4 CLK pin
CCK1/0: “10”
(d) Gear × 1/8 CLK pin
CCK1/0: “11”
72
tCYC
tCYC
tCYC
tCYC
MB91101/MB91101A
• Ceramic oscillator applications
Recommended circuit (3 contacts)
Recommended circuit (2 contacts)
X0
X0
X1
X1
*
*
C1
C1
C2
C2
C1, C2 internally
connected.
* : Murata Mfg. Co., Ltd.
• Discreet type
Oscillation frequency
[MHz]
5.00 to 6.30
6.31 to 10.0
10.1 to 13.0
13.01 to 15.00
Model
Load capacitance
C1 = C2 [pF]
30
CSA
MG
CST
MGW
CSA
MG093
CST
MGW093
CSA
MTZ
30
CST
MTW
(30)
CSA
MTZ093
30
CST
MTW093
(30)
CSA
MTZ
30
CST
MTW
(30)
CSA
MTZ093
30
CST
MTW093
(30)
(30)
30
(30)
CSA
MXZ040
15
CST
MXW0C3
(15)
Power supply voltage
VCC5 [V]
2.9 to 5.5
2.7 to 5.5
2.9 to 5.5
2.7 to 5.5
3.0 to 5.5
2.9 to 5.5
3.2 to 5.5
( ): C1 and C2 internally connected 3 contacts type.
73
MB91101/MB91101A
(3) Reset/Hardware Standby Input Ratings
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol Pin name Condition
Reset input time
tRSTL
RST
Hardware standby input time
tHSTL
HST
—
Value
Max.
tCP × 5
—
ns
tCP × 5
—
ns
tCP (internal operating clock cycle time): Refer to “(1) Clock Timing Rating.”
tRSTL, tHSTL
RST
HST
0.2 VCC
74
Unit
Min.
0.2 VCC
Remarks
MB91101/MB91101A
(4) Power on Supply Specifications (Power-on Reset)
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol Pin name
tR
VCC
tR
VCC
tR
VCC
tR
VCC
Power supply shut off time
tOFF
VCC
Oscillation stabilizing time
tOSC
Power supply rising time
Value
Condition
50
—
µs
*
—
30
ms
*
50
—
µs
*
—
18
ms
*
1
—
ms
Repeated
operations
2 × tC × 221
+ 100 µs
—
ns
VCC = 3.0/
3.3 V
—
Remarks
Max.
VCC = 5.0 V
—
Unit
Min.
tC (clock cycle time): Refer to “(1) Clock Timing Rating.”
* : VCC < 0.2 V before the power supply rising
tR
VCC
0.9 × VCC
0.2 V
tOFF
Note: Sudden change in supply voltage during operation may initiate a power-on sequence.
To change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid
fluctuations in the supply voltage.
VCC
A voltage rising rate of 50 mV/ms or
less is recommended.
VSS
42 ms approx. 336 ms approx. (@12.5 MHz)
VCC
Regulator
(Oscillation stabilizing time)
tOSC
Stabilizing time *
RST
tRSTL + (tC × 219)
tRSTL: Reset input time
*: Reset can’t be done during regulator stabilizing time.
Note: Set RST pin to “L” level when turning on the device, at least the described above duration after the
supply voltage reaches Vcc is necessary before turning the RST to “H” level.
75
MB91101/MB91101A
(5) Normal Bus Access Read/write Operation
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol
Pin name
Condition
Value
Min.
Max.
Unit
Remarks
tCHCSL
CLK,
CS0 to CS5
—
15
ns
tCHCSH
CLK,
CS0 to CS5
—
15
ns
Address delay time
tCHAV
CLK,
A24 to A00
—
15
ns
Data delay time
tCHDV
CLK,
D31 to D16
—
15
ns
tCLRL
CLK, RD
—
6
ns
tCLRH
CLK, RD
—
6
ns
tCLWL
CLK,
WR0, WR1
—
6
ns
tCLWH
CLK,
WR0, WR1
—
6
ns
tAVDV
A24 to A00,
D31 to D16
—
3/2 × tCYC
– 25
ns
*1
*2
RD ↓→ valid data input time tRLDV
RD,
D31 to D16
—
tCYC – 10
ns
*1
Data set up → RD ↑ time
tDSRH
RD,
D31 to D16
10
—
ns
RD ↑→ data hold time
tRHDX
RD,
D31 to D16
0
—
ns
CS0 to CS5 delay time
RD delay time
WR0, WR1 delay time
Valid address → valid data
input time
—
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
*1: When bus timing is delayed by automatic wait insertion or RDY input, add (tCYC × extended cycle number for
delay) to this rating.
*2: Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8,
respectively.
Equation: (2 – n/2) × tCYC – 25
76
MB91101/MB91101A
BA2
BA1
tCYC
CLK
VOH
VOH
VOL
VOH
VOL
tCHCSL
CS0 to CS5
tCHCSH
VOH
VOL
tCHAV
A24 to A00
VOH
VOL
VOH
VOL
tCLRL
tCLRH
RD
VOH
VOL
tRLDV
tRHDX
tAVDV
VIH
VIL
D31 to D16
VIH
VIL
Read
tDSRH
tCLWL
WR0, WR1
VOH
VOL
tCLWH
tCHDV
D31 to D16
VOH
VOL
Write
VOH
VOL
77
MB91101/MB91101A
(6) Ready Input Timing
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol
Pin name
RDY set up time → CLK ↓ tRDYS
RDY, CLK
CLK ↓→ RDY hold time
RDY, CLK
tRDYH
Condition
Value
Max.
15
—
ns
0
—
ns
—
tCYC
CLK
VOH
VOH
VOL
RDY
When wait(s)
is inserted.
RDY
When no wait
is inserted.
78
VIL
VIH
VOL
tRDYH
tRDYS
VIH
VIL
Unit
Min.
tRDYH
tRDYS
VIL
VIH
VIH
VIL
Remarks
MB91101/MB91101A
(7) Hold Timing
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Symbol Pin name Condition
Parameter
Value
Unit
Min.
Max.
—
6
ns
—
6
ns
tCHBGL
CLK,
BGRNT
tCHBGH
CLK,
BGRNT
Pin floating → BGRNT ↓
time
tXHAL
BGRNT
tCYC – 10
tCYC + 10
ns
BGRNT ↑→ pin valid time
tHAHV
BGRNT
tCYC – 10
tCYC + 10
ns
BGRNT delay time
—
Remarks
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
Note: There is a delay time of more than 1 cycle from BRQ input to BGRNT change.
tCYC
CLK
VOH
VOH
VOH
VOH
BRQ
tCHBGH
tCHBGL
BGRNT
VOH
VOL
tXHAL
Each pin
VOH
VOL
tHAHV
High impedance
VOH
VOL
79
MB91101/MB91101A
(8) Normal DRAM Mode Read/Write Cycle
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol
Pin name
Condition
Value
Min.
Max.
Unit
Remarks
tCLRAH
CLK, RAS
—
6
ns
tCHRAL
CLK, RAS
—
6
ns
tCLCASL
CLK, CAS
—
6
ns
tCLCASH
CLK, CAS
—
6
ns
ROW address delay time
tCHRAV
CLK,
A24 to A00
—
15
ns
COLUMN address delay
time
tCHCAV
CLK,
A24 to A00
—
15
ns
tCHDWL
CLK, DW
—
15
ns
tCHDWH
CLK, DW
—
15
ns
Output data delay time
tCHDV1
CLK,
D31 to D16
—
15
ns
RAS ↓→ valid data input
time
tRLDV
RAS,
D31 to D16
—
5/2 × tCYC
– 16
ns
*1
*2
CAS ↓→ valid data input
time
tCLDV
CAS,
D31 to D16
—
tCYC – 17
ns
*1
CAS ↑→ data hold time
tCADH
CAS,
D31 to D16
0
—
ns
RAS delay time
CAS delay time
DW delay time
—
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
CAS: CS0L to CS1H pins are for CAS signal outputs.
DW: DW0, DW1 and CS0H to CS1H are used for WE outputs.
*1: When Q1 cycle or Q4 cycle is extended for 1 cycle, add tCYC time to this rating.
*2: Rating at a gear cycle of × 1.
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8,
respectively.
Equation: (3 – n/2) × tCYC – 16
80
MB91101/MB91101A
Q1
Q2
Q3
Q4
Q5
tCYC
CLK
VOH
VOL
VOH
VOH
VOH
RAS
VOH
VOL
VOL
VOH
VOL
tCLRAH
tCHRAL
tCLCASH
tCLCASH
CAS
VOH
VOL
tCHCAV
tCHRAV
VOH
VOL
A24 to A00
ROW address
VOH
VOL
VOH
VOL
COLUMN address
VOH
VOL
tRLDV
tCADH
tCLDV
VIH
VIL
D31 to D16
VIH
VIL
Read
VOH
DW
VOL
tCHDWH
tCHDWL
D31 to D16
VOH
VOL
Write
VOH
VOL
tCHDV1
81
MB91101/MB91101A
(9)
Normal DRAM Mode Fast Page Read/Write Cycle
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Parameter
RAS delay time
Symbol
Pin name
Condition
Value
Min.
Max.
tCLRAH
CLK, RAS
—
6
ns
tCLCASL
CLK, CAS
—
6
ns
tCLCASH
CLK, CAS
—
6
ns
COLUMN address delay
time
tCHCAV
CLK,
A24 to A00
—
15
ns
DW delay time
tCHDWH
CLK, DW
—
15
ns
Output data delay time
tCHDV1
CLK,
D31 to D16
—
15
ns
CAS ↓→ valid data input
time
tCLDV
CAS,
D31 to D16
—
tCYC – 17
ns
CAS ↑→ data hold time
tCADH
CAS,
D31 to D16
0
—
ns
CAS delay time
—
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
CAS: CS0L to CS1H pins are for CAS signal outputs.
DW: DW0, DW1 and CS0H to CS1H are used for WE outputs.
* : When Q4 cycle is extended for 1 cycle, add tCYC time to this rating.
82
Unit
Remarks
*
MB91101/MB91101A
Q5
Q4
VOH
CLK
Q5
VOL
Q4
Q5
VOH
VOL
VOL
tCLRAH
VOH
RAS
tCLCASL
CAS
tCLCASH
VOH
VOL
tCHCAV
A24 to A00
VOH
VOL
COLUMN address
VOH
VOL
COLUMN address
tCADH
tCLDV
D31 to D16
VIH
VIL
Read
VIH
VIL
VIH
VIL
VOH
VOL
COLUMN address
Read
VIH
VIL
VIH
VIL
Read
VIH
VIL
tCHDWH
VOH
DW
tCHDV1
D31 to D16
VOH
VOL
Write
VOH
VOL
VOH
VOL
Write
VOH
VOL
83
MB91101/MB91101A
(10) Single DRAM Timing
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol
Pin name
Condition
Value
Max.
—
6
ns
6
ns
tCLRAH2
CLK, RAS
tCHRAL2
CLK, RAS
tCHCASL2
CLK, CAS
—
n/2 × tCYC
ns
tCHCASH2
CLK, CAS
—
6
ns
ROW address delay time
tCHRAV2
CLK,
A24 to A00
—
15
ns
COLUMN address delay
time
tCHCAV2
CLK,
A24 to A00
—
15
ns
RAS delay time
CAS delay time
—
tCHDWL2
CLK, DW
—
15
ns
tCHDWH2
CLK, DW
—
15
ns
Output data delay time
tCHDV2
CLK,
D31 to D16
—
15
ns
CAS ↓→ Valid data input
time
tCLDV2
CAS,
D31 to D16
—
(1 – n/2) ×
tCYC – 17
ns
CAS ↑→ data hold time
tCADH2
CLK,
D31 to D16
0
—
ns
DW delay time
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
84
Unit
Min.
Remarks
MB91101/MB91101A
tCYC
*1
Q1
CLK
VOH
Q2
Q3
VOH
VOL
VOH
RAS
Q4S
Q4S
VOH
Q4S
VOH
VOH
VOL
tCHRAL2
tCLRAH2
tCHCASL2
tCHCASH2
CAS
VOH
VOL
VOH
VOL
A24 to A00
ROW address
tCHRAV2
VOH
VOL
VOH
VOL COLUMN-0
VOH
VOL
COLUMN-1
COLUMN-2
tCHCAV2
tCADH2
tCLDV2
Read-0
D31 to D16
VIH
VIL
Read-1
VIH
VIL
Read-2
DW
VOH
VOL
tCHDWL2
D31 to D16
VOH
VOL
Write-0
tCHDV2
*2
VOH
VOL
tCHDWH2
VOH
VOL
tCHDV2
VOH
VOH
VOL
VOL
Write-1
Write-2
*1: Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle.
*2:
indicates the timing when the bus cycle begins from the high spead page mode.
85
MB91101/MB91101A
(11) Hyper DRAM Timing
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol
Pin name
Condition
Value
Min.
Max.
tCLRAH3
CLK, RAS
—
6
ns
tCHRAL3
CLK, RAS
—
6
ns
tCHCASL3
CLK, CAS
—
n/2 × tCYC
ns
tCHCASH3
CLK, CAS
—
6
ns
ROW address delay time
tCHRAV3
CLK,
A24 to A00
—
15
ns
COLUMN address delay
time
tCHCAV3
CLK,
A24 to A00
—
15
ns
tCHRL3
CLK, RD
—
15
ns
—
15
ns
RAS delay time
CAS delay time
—
tCHRH3
CLK, RD
tCLRL3
CLK, RD
—
15
ns
tCHDWL3
CLK, DW
—
15
ns
tCHDWH3
CLK, DW
—
15
ns
Output data delay time
tCHDV3
CLK,
D31 to D16
—
15
ns
CAS ↓→ valid data input
time
tCLDV3
CAS,
D31 to D16
—
tCYC – 17
ns
CAS ↓→ data hold time
tCADH3
CLK,
D31 to D16
0
—
ns
RD delay time
DW delay time
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
86
Unit
Remarks
MB91101/MB91101A
tCYC
*1
Q1
CLK
VOH
Q2
Q3
VOH
VOL
VOH
RAS
Q4H
VOH
Q4H
Q4H
VOH
VOL
VOH
VOL
tCHRAL3
tCLRAH3
tCHCASL3
tCHCASH3
CAS
VOH
VOL
VOH
VOL
A24 to A00
ROW address
tCHRAV3
VOH
VOL
VOHCOLUMN-0
VOL
VOL
VOL
COLUMN-1
COLUMN-2
tCHCAV3
*2
VOL
RD
VOL
tCHRL3
VOH
tCLRL3
tCHRH3
tCLDV3
tCADH3
Read-0
D31 to D16
VIH
VIL
Read-1
VIH
VIL
DW
VOH
VOL
tCHDWL3
D31 to D16
VOH
VOL
Write-0
tCHDV3
*2
VOH
VOL
tCHDWH3
VOH
VOL
tCHDV3
VOH
VOH
VOL
VOL
Write-1
Write-2
*1: Q4H indicates Q4HR (Read) of Single DRAM cycle or Q4HW (Write) cycle.
*2:
indicates the timing when the bus cycle begins from the high spead page mode.
87
MB91101/MB91101A
(12) CBR Refresh
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Parameter
RAS delay time
CAS delay time
Symbol
Pin name
tCLRAH
CLK, RAS
tCHRAL
CLK, RAS
tCLCASL
CLK, CAS
tCLCASH
CLK, CAS
Value
Condition
Unit
Min.
Max.
—
6
ns
—
6
ns
—
6
ns
—
6
ns
—
CAS: CS0L to CS1H pins are for CAS signal outputs.
tCYC
R1
CLK
RAS
VOH
R2
VOH
VOL
R3
VOH
VOL
VOH
tCHRAL
VOL
tCLCASL
DW
88
VOL
VOL
tCLRAH
CAS
R4
VOH
tCLCASH
Remarks
MB91101/MB91101A
(13) Self Refresh
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Symbol
Parameter
RAS delay time
CAS delay time
Pin name
tCLRAH
CLK, RAS
tCHRAL
CLK, RAS
tCLCASL
CLK, CAS
tCLCASH
CLK, CAS
Condition
—
Value
Unit
Min.
Max.
—
6
ns
—
6
ns
—
6
ns
—
6
ns
Remarks
CAS: CS0L to CS1H pins are for CAS signal outputs.
tCYC
SR1
CLK
VOH
SR2
VOH
SR3
VOL
VOH
VOL
tCHRAL
RAS
CAS
VOL
SR3
tCLRAH
VOH
VOH
VOL
tCLCASL
tCLCASH
89
MB91101/MB91101A
(14) UART Timing
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol Pin name Condition
Serial clock cycle time
tSCYC
SCLK ↓→ SCLK ↑
tSCLCH
SCLK ↑→ SCLK ↓
tSCHCL
—
SCLK ↓→ SOUT delay time tSLOV
—
Valid SIN → SCLK ↑
tIVSH
—
SCLK ↑→ valid SIN hold
time
tSHIX
Serial clock “H” pulse width
Serial clock “L” pulse width
Internal
shift clock
mode
Value
Min.
Max.
8 × tCYCP
—
Unit
ns
4 × tCYCP –10 4 × tCYCP +10
ns
4 × tCYCP –10 4 × tCYCP +10
ns
–80
80
ns
100
—
ns
—
60
—
ns
tSHSL
—
4 × tCYCP
—
ns
tSLSH
—
4 × tCYCP
—
ns
—
150
ns
60
—
ns
60
—
ns
SCLK ↓→ SOUT delay time tSLOV
—
Valid SIN → SCLK ↑
tIVSH
—
SCLK ↑→ valid SIN hold
time
tSHIX
—
External
shift clock
mode
tCYCP: A cycle time of peripheral system clock
Notes: This rating is for AC characteristics in CLK synchronous mode.
• Internal shift clock mode
tSCYC
tSCLCH
tSCHCL
VOH
SCLK
VOL
VOL
tSLOV
VOH
VOL
SOUT
tIVSH
tSHIX
VIH
VIL
SIN
VIH
VIL
• External shift clock mode
tSLSH
tSHSL
VIH
VIH
SCLK
VIL
VIL
tSLOV
SOUT
VOH
VOL
tIVSH
SIN
90
VIH
VIL
tSHIX
VIH
VIL
Remarks
MB91101/MB91101A
(15) Trigger System Input Timing
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Parameter
A/D start trigger input time
Symbol
tTRGH,
tTRGL
PWM external trigger input tTRGH,
tTRGL
time
Pin name
Condition
ATG
Value
Unit
Min.
Max.
5 × tCYCP
—
ns
5 × tCYCP
—
ns
Remarks
—
TRG0 to TRG3
tCYCP: A cycle time of peripheral system clock
tTRGH
ATG
TRG0 to TRG3
VIH
tTRGL
VIH
VIL
VIL
91
MB91101/MB91101A
(16) DMA Controller Timing
(VCC5 = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
Parameter
Symbol
Pin name
Condition
Value
Max.
DREQ0 to DREQ2
2 × tCYC
—
ns
tCLDL
CLK,
DACK0 to DACK2
—
6
ns
tCLDH
CLK,
DACK0 to DACK2
—
6
ns
EOP delay time
(Normal bus)
(Normal DRAM)
tCLEL
CLK,
EOP0 to EOP2
—
6
ns
tCLEH
CLK,
EOP0 to EOP2
—
6
ns
DACK delay time
(Single DRAM)
(Hyper DRAM)
tCHDL
CLK,
DACK0 to DACK2
—
n/2 × tCYC
ns
tCHDH
CLK,
DACK0 to DACK2
—
6
ns
tCHEL
CLK,
EOP0 to EOP2
—
n/2 × tCYC
ns
tCHEH
CLK,
EOP0 to EOP2
—
6
ns
DREQ input pulse width tDRWH
DACK delay time
(Normal bus)
(Normal DRAM)
EOP delay time
(Single DRAM)
(Hyper DRAM)
—
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
tCYC
CLK
VOH
VOH
VOL
VOL
tCLDL
tCLEL
DACK0 to DACK2
EOP0 to EOP2
(Normal bus)
(Normal DRAM)
tCLDH
tCLEH
VOH
VOL
DACK0 to DACK2
EOP0 to EOP2
(Single DRAM)
(Hyper DRAM)
VOH
VOL
tCHDL
tCHEL
tCHDH
tDRWH
DREQ0 to DREQ2
92
Unit
Min.
VIH
VIH
Remarks
MB91101/MB91101A
5. A/D Converter Block Electrical Characteristics
(AVCC = 2.7 V to 3.6 V, AVSS = 0.0 V, AVRH = 2.7 V, TA = 0°C to +70°C)
Symbol
Pin name
Resolution
—
Total error
Parameter
Value
Unit
Min.
Typ.
Max.
—
—
10
10
bit
—
—
—
—
±4.0
LSB
Linearity error
—
—
—
—
±3.5
LSB
Differentiation linearity error
—
—
—
—
±2.0
LSB
–1.5
+0.5
+2.5
LSB
Zero transition voltage
VOT
AN0 to AN3
Full-scale transition voltage
VFST
AN0 to AN3 AVRH – 4.5 AVRH – 1.5 AVRH + 0.5 LSB
Conversion time
—
—
5.6 *1
—
—
µs
Analog port input current
IAIN
AN0 to AN3
—
0.1
10
µA
Analog input voltage
VAIN
AN0 to AN3
AVSS
—
AVRH
V
AVRH
AVSS
—
AVCC
V
IA
AVCC
—
4
—
mA
IAH
AVCC
—
—
5*
IR
AVRH
—
200
—
IRH
AVRH
—
—
5*
AN0 to AN3
—
—
4
Reference voltage
—
Power supply current
Reference voltage supply current
Conversion variance between channels
—
2
2
µA
µA
µA
LSB
*1: AVCC = 2.7 V – 3.6 V
*2: Current value for A/D converters not in operation, CPU stop mode (VCC = AVCC = AVRH = 3.6 V)
Notes: • As the absolute value of AVRH decreases, relative error increases.
• Output impedance of external circuit of analog input under following conditions;
Output impedance of external circuit < 10 kΩ.
If output impedance of external circuit is too high, analog voltage sampling time may be too short for
accurate sampling (sampling time is 5.6 µs for a machine clock of 25 MHz).
• Analog input circuit model plan
Sample and hold circuit
Analog input
C0
Comparator
RON1
RON1 : 0.2 kΩ
RON2 : 1.4 kΩ
RON3 : 1.4 kΩ
RON4 : 0.2 kΩ
RON2
RON3
RON4
C1
C0 : 16.6 pF
C1 : 4.0 pF
Note: Listed values are for reference purposes only.
93
MB91101/MB91101A
6. A/D Converter Glossary
• Resolution
The smallest change in analog voltage detected by A/D converter.
• Linearity error
A deviation of actual conversion characteristic from a line connecting the zero-traction point (between “00 0000
0000” ↔ “00 0000 0001”) to the full-scale transition point (between “11 1111 1110” ↔ “11 1111 1111”).
• Differential linearity error
A deviation of a step voltage for changing the LSB of output code from ideal input voltage.
Differential linearity error
Linearity error
3FF
Ideal characteristic
Actual conversion
characteristic
3FE
N+1
{1 LSB × (N – 1) + VOT}
Actual characteristic
Digital output
Digital output
3FD
VFST
(measured
value)
004
VNT
(measured value)
Actual conversion
characteristic
003
N
N–1
V(N + 1)T
VNT (measured value)
(measured value)
002
Ideal characteristic
N–2
001
VOT (measured value)
AVRL
Actual conversion characteristic
AVRH
AVRL
Linearity error of
digital output N =
1 LSB =
VFST – VOT
1022
VNT – {1 LSB × (N – 1) + VOT}
1 LSB
AVRH
Analog input
Analog input
[LSB]
Differential linearity error
of digital output N =
V(N + 1)T – VNT
1 LSB
– 1 [LSB]
[V]
VOT: A voltage for causing transition of digital output from (000)H to (001)H
VFST: A voltage for causing transition of digital output from (3FE)H to (3FF)H
VNT: A voltage for causing transition of digital output from (N – 1)H to N
(Continued)
94
MB91101/MB91101A
(Continued)
• Total error
A difference between actual value and theoretical value. The overall error includes zero-transition error, fullscale transition error and linearity error.
Total error
3FF
1.5 LSB’
3FE
Actual conversion
characteristic
Digital output
3FD
{1 LSB’ × (N – 1)
+ 0.5 LSB’}
004
VNT
(measured value)
003
Actual conversion
characteristic
002
Ideal characteristic
001
0.5 LSB’
AVRL
AVRH
Analog input
Total error of digital output N =
1 LSB’ (ideal value) =
AVRH – AVRL
1024
VOT’
VNT – {1 LSB’ × (N – 1) + 0.5 LSB’}
1 LSB'
[LSB]
[V]
(ideal value) = AVRL + 0.5 LSB’ [V]
VFST’ (ideal value) = AVRL – 1.5 LSB’ [V]
VNT: A voltage for causing transition of digital output from (N – 1) to N
95
MB91101/MB91101A
■ REFERENCE DATA
1. Operating frequency vs. ICC characteristics
Internal DC - DC regulator is not used (VCC = 3 V)
Internal DC - DC regulator is used (VCC = 5 V)
ICC (mA)
ICC (mA)
90
90
(VCC)
80
(VCC)
80
3.6 V
4.5 V to 5.5 V
70
70
3.3 V
60
60
3.0 V
50
50
2.7 V
40
40
30
30
20
20
10
10
0
0
0
10
f (MHz)
20
30
40
50
0
10
f (MHz)
20
30
40
50
Operating conditions : Source oscillation 12.5 MHz (crystal), PLL is used (50 M, 25 M, 12.5 M)
Gear : CPU = 1/1, Peripherals = 1/1
(Doubler is used for 50MHz, Gear peripherals = 1/2)
2. VCC vs. ICC characteristics
Internal DC - DC regulator is not used (VCC = 3 V)
Internal DC - DC regulator is used (VCC = 5 V)
ICC (mA)
Icc (mA)
18
18
Gear : 1/1
16
16
14
14
Gear : 1/1
Gear : 1/2
12
12
14
14
Gear : 1/2
Gear : 1/4
10
10
Gear : 1/8
Gear : 1/4
8
8
Gear : 1/8
(PLL : off)
4
Gear : 1/8
4
Gear : 1/8
(PLL : off)
2
2
0
0
VCC (V)
2.7
3.0
3.3
3.6
VCC (V)
4.5
5.0
5.5
Operating conditions : Source oscillation 12.5 MHz (crystal), divide-by-2 input, PLL : ON
Gear : CPU = Peripherals
96
MB91101/MB91101A
■ INSTRUCTIONS (165 INSTRUCTIONS)
1. How to Read Instruction Set Summary
Mnemonic
ADD
* ADD
↓
(1)
Rj,
Ri
#s5, Ri
,
,
↓
(2)
Type
OP
CYC
NZVC
Operation
A
C
,
,
A6
A4
,
,
1
1
,
,
CCCC
CCCC
,
,
Ri + Rj → Ri
Ri + s5 → Ri
,
,
↓
(3)
↓
(4)
↓
(5)
↓
(6)
↓
(7)
Remarks
(1) Names of instructions
Instructions marked with * are not included in CPU specifications. These are extended instruction codes
added/extended at assembly language levels.
(2) Addressing modes specified as operands are listed in symbols.
Refer to “2. Addressing mode symbols” for further information.
(3) Instruction types
(4) Hexa-decimal expressions of instructions
(5) The number of machine cycles needed for execution
a: Memory access cycle and it has possibility of delay by Ready function.
b: Memory access cycle and it has possibility of delay by Ready function.
If an object register in a LD operation is referenced by an immediately following instruction, the interlock
function is activated and number of cycles needed for execution increases.
c: If an immediately following instruction operates to an object of R15, SSP or USP in read/write mode or
if the instruction belongs to instruction format A group, the interlock function is activated and number of
cycles needed for execution increases by 1 to make the total number of 2 cycles needed.
d: If an immediately following instruction refers to MDH/MDL, the interlock function is activated and number
of cycles needed for execution increases by 1 to make the total number of 2 cycles needed.
For a, b, c and d, minimum execution cycle is 1.
(6) Change in flag sign
• Flag change
C : Change
– : No change
0 : Clear
1 : Set
• Flag meanings
N : Negative flag
Z : Zero flag
V : Over flag
C : Carry flag
(7) Operation carried out by instruction
97
MB91101/MB91101A
2. Addressing Mode Symbols
Ri
Rj
R13
Ps
Rs
CRi
CRj
#i8
: Register direct (R0 to R15, AC, FP, SP)
: Register direct (R0 to R15, AC, FP, SP)
: Register direct (R13, AC)
: Register direct (Program status register)
: Register direct (TBR, RP, SSP, USP, MDH, MDL)
: Register direct (CR0 to CR15)
: Register direct (CR0 to CR15)
: Unsigned 8-bit immediate (–128 to 255)
Note: –128 to –1 are interpreted as 128 to 255
#i20
: Unsigned 20-bit immediate (–0X80000 to 0XFFFFF)
Note: –0X7FFFF to –1 are interpreted as 0X7FFFF to 0XFFFFF
#i32
: Unsigned 32-bit immediate (–0X80000000 to 0XFFFFFFFF)
Note: –0X80000000 to –1 are interpreted as 0X80000000 to 0XFFFFFFFF
#s5
: Signed 5-bit immediate (–16 to 15)
#s10
: Signed 10-bit immediate (–512 to 508, multiple of 4 only)
#u4
: Unsigned 4-bit immediate (0 to 15)
#u5
: Unsigned 5-bit immediate (0 to 31)
#u8
: Unsigned 8-bit immediate (0 to 255)
#u10
: Unsigned 10-bit immediate (0 to 1020, multiple of 4 only)
@dir8
: Unsigned 8-bit direct address (0 to 0XFF)
@dir9
: Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only)
@dir10
: Unsigned 10-bit direct address (0 to 0X3FC, multiple of 4 only)
label9
: Signed 9-bit branch address (–0X100 to 0XFC, multiple of 2 only)
label12
: Signed 12-bit branch address (–0X800 to 0X7FC, multiple of 2 only)
label20
: Signed 20-bit branch address (–0X80000 to 0X7FFFF)
label32
: Signed 32-bit branch address (–0X80000000 to 0X7FFFFFFF)
@Ri
: Register indirect (R0 to R15, AC, FP, SP)
@Rj
: Register indirect (R0 to R15, AC, FP, SP)
@(R13, Rj)
: Register relative indirect (Rj: R0 to R15, AC, FP, SP)
@(R14, disp10) : Register relative indirect (disp10: –0X200 to 0X1FC, multiple of 4 only)
@(R14, disp9) : Register relative indirect (disp9: –0X100 to 0XFE, multiple of 2 only)
@(R14, disp8) : Register relative indirect (disp8: –0X80 to 0X7F)
@(R15, udisp6) : Register relative (udisp6: 0 to 60, multiple of 4 only)
@Ri+
: Register indirect with post-increment (R0 to R15, AC, FP, SP)
@R13+
: Register indirect with post-increment (R13, AC)
@SP+
: Stack pop
@–SP
: Stack push
(reglist)
: Register list
98
MB91101/MB91101A
3. Instruction Types
MSB
Type A
Type B
LSB
16 bits
OP
Rj
Ri
8
4
4
OP
i8/o8
Ri
4
8
4
Type C
OP
u4/m4
Ri
8
4
4
ADD, ADDN, CMP, LSL, LSR and ASR instructions only
Type *C’
Type D
Type E
Type F
OP
s5/u5
Ri
7
5
4
OP
u8/rel8/dir/reglist
8
8
OP
SUB-OP
Ri
8
4
4
OP
rel11
5
11
99
MB91101/MB91101A
4. Detailed Description of Instructions
• Add/subtract operation instructions (10 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
ADD
* ADD
Rj, Ri
#s5, Ri
A
C’
A6
A4
1
1
C C C C Ri + Rj → Ri
C C C C Ri + s5 → Ri
ADD
ADD2
#i4, Ri
#i4, Ri
C
C
A4
A5
1
1
C C C C Ri + extu (i4) → Ri
C C C C Ri + extu (i4) → Ri
ADDC
Rj, Ri
A
A7
1
C C C C Ri + Rj + c → Ri
ADDN
* ADDN
Rj, Ri
#s5, Ri
A
C’
A2
A0
1
1
– – – – Ri + Rj → Ri
– – – – Ri + s5 → Ri
ADDN
ADDN2
#i4, Ri
#i4, Ri
C
C
A0
A1
1
1
– – – – Ri + extu (i4) → Ri
– – – – Ri + extu (i4) → Ri
SUB
Rj, Ri
A
AC
1
C C C C Ri – Rj → Ri
SUBC
Rj, Ri
A
AD
1
C C C C Ri – Rj – c → Ri
SUBN
Rj, Ri
A
AE
1
– – – – Ri – Rj → Ri
Remarks
MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension
Add operation with
sign
MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension
Subtract operation with
carry
• Compare operation instructions (3 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
CMP
* CMP
Rj, Ri
#s5, Ri
A
C’
AA
A8
1
1
C C C C Ri – Rj
C C C C Ri – s5
CMP
CMP2
#i4, Ri
#i4, Ri
C
C
A8
A9
1
1
C C C C Ri + extu (i4)
C C C C Ri + extu (i4)
Remarks
MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension
• Logical operation instructions (12 instructions)
100
Mnemonic
Type
OP
Cycle N Z V C
AND
AND
ANDH
ANDB
Rj, Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
A
A
A
A
82
84
85
86
1
1 + 2a
1 + 2a
1 + 2a
CC
CC
CC
CC
–
–
–
–
–
–
–
–
Ri &
(Ri) &
(Ri) &
(Ri) &
= Rj
= Rj
= Rj
= Rj
Word
Word
Half word
Byte
OR
OR
ORH
ORB
Rj, Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
A
A
A
A
92
94
95
96
1
1 + 2a
1 + 2a
1 + 2a
CC
CC
CC
CC
–
–
–
–
–
–
–
–
Ri
(Ri)
(Ri)
(Ri)
|
|
|
|
= Rj
= Rj
= Rj
= Rj
Word
Word
Half word
Byte
EOR
EOR
EORH
EORB
Rj, Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
A
A
A
A
9A
9C
9D
9E
1
1 + 2a
1 + 2a
1 + 2a
CC
CC
CC
CC
–
–
–
–
–
–
–
–
Ri ^
(Ri) ^
(Ri) ^
(Ri) ^
= Rj
= Rj
= Rj
= Rj
Word
Word
Half word
Byte
Operation
Remarks
MB91101/MB91101A
• Bit manipulation arithmetic instructions (8 instructions)
Mnemonic
BANDL
BANDH
* BAND
BORL
BORH
* BOR
BEORL
BEORH
* BEOR
BTSTL
BTSTH
#u4, @Ri
(u4: 0 to 0FH)
#u4, @Ri
(u4: 0 to 0FH)
#u8, @Ri
#u4, @Ri
(u4: 0 to 0FH)
#u4, @Ri
(u4: 0 to 0FH)
#u8, @Ri
#u4, @Ri
(u4: 0 to 0FH)
#u4, @Ri
(u4: 0 to 0FH)
#u8, @Ri
Type
OP
Cycle N Z V C
C
80
1 + 2a – – – – (Ri) & = (F0H + u4)
Manipulate lower 4 bits
C
81
1 + 2a – – – – (Ri) & = ((u4<<4) + 0FH)
Manipulate upper 4 bits
–
*1
Remarks
– – – – (Ri) & = u8
C
90
1 + 2a – – – – (Ri) | = u4
Manipulate lower 4 bits
C
91
1 + 2a – – – – (Ri) | = (u4<<4)
Manipulate upper 4 bits
–
*2
– – – – (Ri) | = u8
C
98
1 + 2a – – – – (Ri) ^ = u4
Manipulate lower 4 bits
C
99
1 + 2a – – – – (Ri) ^ = (u4<<4)
Manipulate upper 4 bits
–
*3
#u4, @Ri
(u4: 0 to 0FH)
#u4, @Ri
(u4: 0 to 0FH)
Operation
– – – – (Ri) ^ = u8
C
88
2+a
0 C – – (Ri) & u4
Test lower 4 bits
C
89
2+a
C C – – (Ri) & (u4<<4)
Test upper 4 bits
*1: Assembler generates BANDL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates
BANDH if “u8&0xF0” leaves an active bit. Depending on the value in the “u8” format, both BANDL and BANDH
may be generated.
*2: Assembler generates BORL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates
BORH if “u8&0xF0” leaves an active bit.
*3: Assembler generates BEORL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates
BEORH if “u8&0xF0” leaves an active bit.
• Add/subtract operation instructions (10 instructions)
Mnemonic
Type
OP
Cycle N Z V C
MUL
MULU
MULH
MULUH
Rj, Ri
Rj, Ri
Rj, Ri
Rj, Ri
A
A
A
A
AF
AB
BF
BB
5
5
3
3
CCC
CCC
CC–
CC–
DIVOS
DIVOU
DIV1
DIV2
DIV3
DIV4S
* DIV
Ri
Ri
Ri
Ri
E
E
E
E
E
E
97 – 4
97 – 5
97 – 6
97 – 7
9F – 6
9F – 7
Ri
*1
1
1
d
1
1
1
–
–
–
–
–
–
–
–
* DIVU
Ri
*2
–
–
–
C
C
–
–
C
–
–
–
–
–
–
–
–
–
–
–
Operation
Rj × Ri → MDH, MDL
Rj × Ri → MDH, MDL
Rj × Ri → MDL
Rj × Ri → MDL
–
–
C
C
–
–
C MDL/Ri → MDL,
MDL%Ri → MDH
– C – C MDL/Ri → MDL,
MDL%Ri → MDH
Remarks
32-bit × 32-bit = 64-bit
Unsigned
16-bit × 16-bit = 32-bit
Unsigned
Step calculation
32-bit/32-bit = 32-bit
Unsigned
*1: DIVOS, DIV1 × 32, DIV2, DIV3 and DIV4S are generated. A total instruction code length of 72 bytes.
*2: DIVOU and DIV1 × 32 are generated. A total instruction code length of 66 bytes.
101
MB91101/MB91101A
• Shift arithmetic instructions (9 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
LSL
* LSL
LSL
LSL2
Rj, Ri
#u5, Ri
#u4, Ri
#u4, Ri
A
C’
C
C
B6
B4
B4
B5
1
1
1
1
CC
CC
CC
CC
–
–
–
–
C
C
C
C
Ri<<Rj → Ri
Ri<<u5 → Ri
Ri<<u4 → Ri
Ri<<(u4 + 16) → Ri
Logical shift
LSR
* LSR
LSR
LSR2
Rj, Ri
#u5, Ri
#u4, Ri
#u4, Ri
A
C’
C
C
B2
B0
B0
B1
1
1
1
1
CC
CC
CC
CC
–
–
–
–
C
C
C
C
Ri>>Rj → Ri
Ri>>u5 → Ri
Ri>>u4 → Ri
Ri>>(u4 + 16) → Ri
Logical shift
ASR
* ASR
ASR
ASR2
Rj, Ri
#u5, Ri
#u4, Ri
#u4, Ri
A
C’
C
C
BA
B8
B8
B9
1
1
1
1
CC
CC
CC
CC
–
–
–
–
C
C
C
C
Ri>>Rj → Ri
Ri>>u5 → Ri
Ri>>u4 → Ri
Ri>>(u4 + 16) → Ri
Logical shift
• Immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer
instruction) (3 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
LDI: 32
LDI: 20
#i32, Ri
#i20, Ri
E
C
9F – 8
9B
3
2
– – – – i32 → Ri
– – – – i20 → Ri
LDI: 8
* LDI
#i8, Ri
# {i8 | i20 | i32}, Ri
*1
B
C0
1
– – – – i8 → Ri
{i8 | i20 | i32} → Ri
Remarks
Upper 12 bits are zeroextended
Upper 24 bits are zeroextended
*1: If an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection.
If an immediate value contains relative value or external reference, assembler selects i32.
• Memory load instructions (13 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
(Rj) → Ri
(R13 + Rj) → Ri
(R14 + disp10) → Ri
(R15 + udisp6) → Ri
(R15) → Ri, R15 + = 4
(R15) → Rs, R15 + = 4
Remarks
LD
LD
LD
LD
LD
LD
@Rj, Ri
@(R13, Rj), Ri
@(R14, disp10), Ri
@(R15, udisp6), Ri
@R15 +, Ri
@R15 +, Rs
A
A
B
C
E
E
04
00
20
03
07 – 0
07 – 8
b
b
b
b
b
b
LD
@R15 +, PS
E
07 – 9
1+a+b
LDUH
LDUH
LDUH
@Rj, Ri
@(R13, Rj), Ri
@(R14, disp9), Ri
A
A
B
05
01
40
b
b
b
– – – – (Rj) → Ri
– – – – (R13 + Rj) → Ri
– – – – (R14 + disp9) → Ri
Zero-extension
Zero-extension
Zero-extension
LDUB
LDUB
LDUB
@Rj, Ri
@(R13, Rj), Ri
@(R14, disp8), Ri
A
A
B
06
02
60
b
b
b
– – – – (Rj) → Ri
– – – – (R13 + Rj) → Ri
– – – – (R14 + disp8) → Ri
Zero-extension
Zero-extension
Zero-extension
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
C C C C (R15) → PS, R15 + = 4
Rs: Special-purpose
register
Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler
description from disp8 to disp10 are as follows:
disp8 → o8 = disp8
disp9 → o8 = disp9>>1
Each disp is a code extension.
disp10 → o8 = disp10>>2
udisp6 → u4 = udisp6>>2
udisp4 is a 0 extension.
102
MB91101/MB91101A
• Memory store instructions (13 instructions)
Mnemonic
Type
OP
Cycle N Z V C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Operation
Ri → (Rj)
Ri → (R13 + Rj)
Ri → (R14 + disp10)
Ri → (R15 + usidp6)
R15 – = 4, Ri → (R15)
R15 – = 4, Rs → (R15)
Remarks
ST
ST
ST
ST
ST
ST
Ri, @Rj
Ri, @(R13, Rj)
Ri, @(R14, disp10)
Ri, @(R15, udisp6)
Ri, @–R15
Rs, @–R15
A
A
B
C
E
E
14
10
30
13
17 – 0
17 – 8
a
a
a
a
a
a
–
–
–
–
–
–
Word
Word
Word
ST
PS, @–R15
E
17 – 9
a
– – – – R15 – = 4, PS → (R15)
STH
STH
STH
Ri, @Rj
Ri, @(R13, Rj)
Ri, @(R14, disp9)
A
A
B
15
11
50
a
a
a
– – – – Ri → (Rj)
– – – – Ri → (R13 + Rj)
– – – – Ri → (R14 + disp9)
Half word
Half word
Half word
STB
STB
STB
Ri, @Rj
Ri, @(R13, Rj)
Ri, @(R14, disp8)
A
A
B
16
12
70
a
a
a
– – – – Ri → (Rj)
– – – – Ri → (R13 + Rj)
– – – – Ri → (R14 + disp8)
Byte
Byte
Byte
Rs: Special-purpose
register
Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler
description from disp8 to disp10 are as follows:
disp8 → o8 = disp8
disp9 → o8 = disp9>>1
Each disp is a code extension.
disp10 → o8 = disp10>>2
udisp6 → u4 = udisp6>>2
udisp4 is a 0 extension.
• Transfer instructions between registers/special-purpose registers transfer instructions
(5 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
MOV
Rj, Ri
A
8B
1
– – – – Rj → Ri
MOV
Rs, Ri
A
B7
1
– – – – Rs → Ri
MOV
Ri, Rs
A
B3
1
– – – – Ri → Rs
MOV
MOV
PS, Ri
Ri, PS
E
E
17 – 1
07 – 1
1
c
– – – – PS → Ri
C C C C Ri → PS
Remarks
Transfer between
general-purpose
registers
Rs: Special-purpose
register
Rs: Special-purpose
register
103
MB91101/MB91101A
• Non-delay normal branch instructions (23 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
JMP
@Ri
E
97 – 0
2
– – – – Ri → PC
CALL
label12
F
D0
2
CALL
@Ri
E
97 – 1
2
– – – – PC + 2 → RP,
PC + 2 + rel11 × 2 → PC
– – – – PC + 2 → RP, Ri → PC
E
97 – 2
2
– – – – RP → PC
D
1F
3+3a
RET
INT
#u8
Remarks
Return
– – – – SSP – = 4, PS → (SSP),
SSP – = 4,
PC + 2 → (SSP),
0 → I flag,
0 → S flag,
(TBR + 3FC – u8 × 4) →
PC
INTE
E
9F – 3 3 + 3a – – – – SSP – = 4, PS → (SSP), For emulator
SSP – = 4,
PC + 2 → (SSP),
0 → S flag,
(TBR + 3D8 – u8 × 4) →
PC
RETI
E
97 – 3 2 + 2a C C C C (R15) → PC, R15 – = 4,
(R15) → PS, R15 – = 4
BNO
BRA
BEQ
BNE
BC
BNC
BN
BP
BV
BNV
BLT
BGE
BLE
BGT
BLS
BHI
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
E1
E0
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
1
2
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Non-branch
PC + 2 + rel8 × 2 → PC
PCif Z = = 1
PCif Z = = 0
PCif C = = 1
PCif C = = 0
PCif N = = 1
PCif N = = 0
PCif V = = 1
PCif V = = 0
PCif V xor N = = 1
PCif V xor N = = 0
PCif (V xor N) or Z = = 1
PCif (V xor N) or Z = = 0
PCif C or Z = = 1
PCif C or Z = = 0
Notes: • “2/1” in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch.
• The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and
assembler discription label9 and label12 are as follows.
label9 → rel8 = (label9 – PC – 2)/2
label12 → rel11 = (label12 – PC – 2)/2
• RETI must be operated while S flag = 0.
104
MB91101/MB91101A
• Branch instructions with delays (20 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
JMP:D
@Ri
E
9F – 0
1
– – – – Ri → PC
CALL:D
label12
F
D8
1
CALL:D
@Ri
E
9F – 1
1
– – – – PC + 4 → RP,
PC + 2 + rel11 × 2 → PC
– – – – PC + 4 → RP, Ri → PC
E
9F – 2
1
– – – – RP → PC
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
F1
F0
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
RET:D
BNO:D
BRA:D
BEQ:D
BNE:D
BC:D
BNC:D
BN:D
BP:D
BV:D
BNV:D
BLT:D
BGE:D
BLE:D
BGT:D
BLS:D
BHI:D
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Remarks
Return
Non-branch
PC + 2 + rel8 × 2 → PC
PCif Z = = 1
PCif Z = = 0
PCif C = = 1
PCif C = = 0
PCif N = = 1
PCif N = = 0
PCif V = = 1
PCif V = = 0
PCif V xor N = = 1
PCif V xor N = = 0
PCif (V xor N) or Z = = 1
PCif (V xor N) or Z = = 0
PCif C or Z = = 1
PCif C or Z = = 0
Notes: • The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and
assembler discription label9 and label12 are as follows.
label9 → rel8 = (label9 – PC – 2)/2
label12 → rel11 = (label12 – PC – 2)/2
• Delayed branch operation always executes next instruction (delay slot) before making a branch.
• Instructions allowed to be stored in the delay slot must meet one of the following conditions. If the other
instruction is stored, this device may operate other operation than defined.
The instruction described “1” in the other cycle column than branch instruction.
The instruction described “a”, “b”, “c” or “d” in the cycle column.
105
MB91101/MB91101A
• Direct addressing instructions
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
DMOV
DMOV
DMOV
DMOV
DMOV
DMOV
@dir10,
R13,
@dir10,
@R13+,
@dir10,
@R15+,
R13
@dir10
@R13+
@dir10
@–R15
@dir10
D
D
D
D
D
D
08
18
0C
1C
0B
1B
b
a
2a
2a
2a
2a
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(dir10) → R13
R13 → (dir10)
(dir10) → (R13), R13 + = 4
(R13) → (dir10), R13 + = 4
R15 – = 4, (dir10) → (R15)
(R15) → (dir10), R15 + = 4
Word
Word
Word
Word
Word
Word
DMOVH
DMOVH
DMOVH
DMOVH
@dir9,
R13,
@dir9,
@R13+,
R13
@dir9
@R13+
@dir9
D
D
D
D
09
19
0D
1D
b
a
2a
2a
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(dir9) → R13
R13 → (dir9)
(dir9) → (R13), R13 + = 2
(R13) → (dir9), R13 + = 2
Half word
Half word
Half word
Half word
DMOVB
DMOVB
DMOVB
DMOVB
@dir8,
R13,
@dir8,
@R13+,
R13
@dir8
@R13+
@dir8
D
D
D
D
0A
1A
0E
1E
b
a
2a
2a
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(dir8) → R13
R13 → (dir8)
(dir8) → (R13), R13 + +
(R13) → (dir8), R13 + +
Byte
Byte
Byte
Byte
Note: The relations between the dir field of TYPE-D in the instruction format and the assembler description from
disp8 to disp10 are as follows:
disp8 → dir + disp8
disp9 → dir = disp9>>1
Each disp is a code extension
disp10 → dir = disp10>>2
• Resource instructions (2 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
LDRES
@Ri+,
#u4
C
BC
a
– – – – (Ri) → u4 resource
Ri + = 4
u4: Channel number
STRES
#u4,
@Ri+
C
BD
a
– – – – u4 resource → (Ri)
Ri + = 4
u4: Channel number
• Co-processor instructions (4 instructions)
Mnemonic
COPOP
COPLD
COPST
COPSV
106
#u4, #CC, CRj, CRi
#u4, #CC, Rj, CRi
#u4, #CC, CRj, Ri
#u4, #CC, CRj, Ri
Type
OP
E
E
E
E
9F – C
9F – D
9F – E
9F – F
Cycle N Z V C
2+a
1 + 2a
1 + 2a
1 + 2a
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Operation
Calculation
Rj → CRi
CRj → Ri
CRj → Ri
Remarks
No error traps
MB91101/MB91101A
• Other instructions (16 instructions)
Mnemonic
Type
OP
NOP
E
9F – A
1
– – – – No changes
ANDCCR #u8
ORCCR #u8
D
D
83
93
c
c
C C C C CCR and u8 → CCR
C C C C CCR or u8 → CCR
STILM
#u8
D
87
1
– – – – i8 → ILM
Set ILM immediate
value
ADDSP
#s10
D
A3
1
– – – – R15 + = s10
ADD SP instruction
EXTSB
EXTUB
EXTSH
EXTUH
Ri
Ri
Ri
Ri
E
E
E
E
97 – 8
97 – 9
97 – A
97 – B
1
1
1
1
–
–
–
–
LDM0
(reglist)
D
8C
*4
Load-multi R0 to R7
LDM1
(reglist)
D
8D
*4
* LDM
(reglist)
– – – – (R15) → reglist,
R15 increment
– – – – (R15) → reglist,
R15 increment
– – – – (R15 + +) → reglist,
STM0
(reglist)
D
8E
*6
Store-multi R0 to R7
STM1
(reglist)
D
8F
*6
* STM2
(reglist)
*5
– – – – R15 decrement,
reglist → (R15)
– – – – R15 decrement,
reglist → (R15)
– – – – reglist → (R15 + +)
ENTER
#u10
*2
LEAVE
XCHB
@Rj, Ri
*1
*3
Cycle N Z V C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Operation
Remarks
Sign extension 8 → 32 bits
Zero extension 8 → 32 bits
Sign extension 16 → 32 bits
Zero extension 16 → 32 bits
Load-multi R8 to R15
Load-multi R0 to R15
Store-multi R8 to R15
Store-multi R0 to R15
D
0F
1+a
– – – – R14 → (R15 – 4),
R15 – 4 → R14,
R15 – u10 → R15
Entrance processing
of function
E
9F – 9
b
– – – – R14 + 4 → R15,
(R15 – 4) → R14
Exit processing of
function
A
8A
2a
– – – – Ri → TEMP,
(Rj) → Ri,
TEMP → (Rj)
For SEMAFO
management
Byte data
*1: In the ADDSP instruction, the reference between u8 of TYPE-D in the instruction format and assembler
description s10 is as follows.
s10 → s8 = s10>>2
*2: In the ENTER instruction, the reference between i8 of TYPE-C in the instruction format and assembler
description u10 is as follows.
u10 → u8 = u10>>2
*3: If either of R0 to R7 is specified in reglist, assembler generates LDM0. If either of R8 to R15 is specified,
assembler generates LDM1. Both LDM0 and LDM1 may be generated.
*4: The number of cycles needed for execution of LDM0 (reglist) and LDM1 (reglist) is given by the following
calculation; a × (n – 1) + b + 1 when “n” is number of registers specified.
*5: If either of R0 to R7 is specified in reglist, assembler generates STM0. If either of R8 to R15 is specified,
assembler generates STM1. Both STM0 and STM1 may be generated.
*6: The number of cycles needed for execution of STM0 (reglist) and STM1 (reglist) is given by the following
calculation; a × n + 1 when “n” is number of registers specified.
107
MB91101/MB91101A
• 20-bit normal branch macro instructions
Mnemonic
Operation
Remarks
* CALL20
label20, Ri
Next instruction address → RP, label20 → PC
Ri: Temporary register
*1
* BRA20
* BEQ20
* BNE20
* BC20
* BNC20
* BN20
* BP20
* BV20
* BNV20
* BLT20
* BGE20
* BLE20
* BGT20
* BLS20
* BHI20
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20 → PC
if (Z = = 1) then label20 → PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
*2
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*1: CALL20
(1) If label20 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL
label12
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20 #label20, Ri
CALL
@Ri
*2: BRA20
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA
label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20 #label20, Ri
JMP
@Ri
*3: Bcc20 (BEQ20 to BHI20)
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc
label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:20 #label20, Ri
JMP
@Ri
false:
108
MB91101/MB91101A
• 20-bit delayed branch macro instructions
Mnemonic
Operation
Remarks
* CALL20:D label20, Ri
Next instruction address + 2 → RP, label20 → PC
Ri: Temporary register
*1
* BRA20:D
* BEQ20:D
* BNE20:D
* BC20:D
* BNC20:D
* BN20:D
* BP20:D
* BV20:D
* BNV20:D
* BLT20:D
* BGE20:D
* BLE20:D
* BGT20:D
* BLS20:D
* BHI20:D
label20 → PC
if (Z = = 1) then label20 → PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
*2
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
*1: CALL20:D
(1) If label20 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL:D label12
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20 #label20, Ri
CALL:D @Ri
*2: BRA20:D
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA:D label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20 #label20, Ri
JMP:D @Ri
*3: Bcc20:D (BEQ20:D to BHI20:D)
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc:D
label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:20 #label20, Ri
JMP:D @Ri
false:
109
MB91101/MB91101A
• 32-bit normal macro branch instructions
Mnemonic
Operation
Remarks
* CALL32
label32, Ri
Next instruction address → RP, label32 → PC
Ri: Temporary register
*1
* BRA32
* BEQ32
* BNE32
* BC32
* BNC32
* BN32
* BP32
* BV32
* BNV32
* BLT32
* BGE32
* BLE32
* BGT32
* BLS32
* BHI32
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32 → PC
if (Z = = 1) then label32 → PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
*2
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*1: CALL32
(1) If label32 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL
label12
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:32 #label32, Ri
CALL
@Ri
*2: BRA32
(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA
label9
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:32 #label32, Ri
JMP
@Ri
*3: Bcc32 (BEQ32 to BHI32)
(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc
label9
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:32 #label32, Ri
JMP
@Ri
false:
110
MB91101/MB91101A
• 32-bit delayed macro branch instructions
Mnemonic
Operation
Remarks
* CALL32:D label32, Ri
Next instruction address + 2 → RP, label32 → PC
Ri: Temporary register
*1
* BRA32:D
* BEQ32:D
* BNE32:D
* BC32:D
* BNC32:D
* BN32:D
* BP32:D
* BV32:D
* BNV32:D
* BLT32:D
* BGE32:D
* BLE32:D
* BGT32:D
* BLS32:D
* BHI32:D
label32 → PC
if (Z = = 1) then label32 → PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
*2
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
*1: CALL32:D
(1) If label32 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL:D label12
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:32 #label32, Ri
CALL:D @Ri
*2: BRA32:D
(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA:D label9
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:32 #label32, Ri
JMP:D @Ri
*3: Bcc32:D (BEQ32:D to BHI32:D)
(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc:D
label9
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:32 #label32, Ri
JMP:D @Ri
false:
111
MB91101/MB91101A
■ ORDERING INFORMATION
Part number
112
Package
MB91101APFV
100-pin Plastic LQFP
(FPT-100P-M05)
MB91101APF
100-pin Plastic QFP
(FPT-100P-M06)
Remarks
MB91101/MB91101A
■ PACKAGE DIMENSIONS
100-pin Plastic LQFP
(FPT-100P-M05)
+0.20
16.00±0.20(.630±.008)SQ
75
1.50 –0.10
+.008
14.00±0.10(.551±.004)SQ
76
(Mouting height)
.059 –.004
51
50
12.00
(.472)
REF
15.00
(.591)
NOM
Details of "A" part
0.15(.006)
INDEX
100
0.15(.006)
26
0.15(.006)MAX
LEAD No.
1
"B"
25
0.40(.016)MAX
"A"
0.50(.0197)TYP
+0.08
0.18 –0.03
+.003
.007 –.001
+0.05
0.08(.003)
M
0.127 –0.02
+.002
Details of "B" part
.005 –.001
0.10±0.10
(STAND OFF)
(.004±.004)
0.10(.004)
C
1995 FUJITSU LIMITED F100007S-2C-3
0.50±0.20(.020±.008)
0~10°
Dimensions in mm (inches)
(Continued)
113
MB91101/MB91101A
(Continued)
100-pin Plastic QFP
(FPT-100P-M06)
23.90±0.40(.941±.016)
3.35(.132)MAX
(Mounting height)
0.05(.002)MIN
(STAND OFF)
20.00±0.20(.787±.008)
80
51
81
50
14.00±0.20
(.551±.008)
12.35(.486)
REF
17.90±0.40
(.705±.016)
16.30±0.40
(.642±.016)
INDEX
31
100
"A"
LEAD No.
1
30
0.65(.0256)TYP
0.30±0.10
(.012±.004)
0.13(.005)
0.15±0.05(.006±.002)
M
Details of "A" part
0.25(.010)
Details of "B" part
"B"
0.10(.004)
18.85(.742)REF
22.30±0.40(.878±.016)
C
1994 FUJITSU LIMITED F100008-3C-2
0.30(.012)
0.18(.007)MAX
0.53(.021)MAX
0
10°
0.80±0.20
(.031±.008)
Dimensions in mm (inches)
Note: The design may be modified changed without notice, contact to Fujitsu sales division when using the device.
114
MB91101/MB91101A
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and
measurement equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
F9907
 FUJITSU LIMITED Printed in Japan
115