FUJITSU MB90246APFV

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13505-5E
16-bit Proprietary Microcontroller
CMOS
F2MC-16F MB90246A Series
MB90246A
■ DESCRIPTION
The MB90246A series is a 16-bit microcontroller optimum to control mechatronics such as a hard disk drive unit.
The instruction set of F2MC-16F CPU core inherits AT architecture of F2MC*-16/16H family with additional
instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division
instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for
processing long word data (32-bit).
The MB90246A series contains a production addition unit as peripheral resources for enabling easy
implementation of functions supported by IIR and FIR digital filters. It also supports a wealth of peripheral functions
including:
- an 8/10-bit A/D converter having eight channels;
- an 8-bit D/A converter having three channels;
- UART;
- an 8-bit PWM timer having four channels;
- a timer having three plus one channels;
- an input capture (ICU) having two channels; and
- a DTP/external interrupt circuit having four channels.
* : F2MC stands for FUJITSU Flexible Microcontroller.
■ PACKAGE
100-pin Plastic LQFP
(FPT-100P-M05)
MB90246A Series
■ FEATURES
• Clock
Operating clock can be selected from divided-by-2, 4, 8 or 32 of oscillation (at oscillation of 32 MHz, 1 MHz
to 16 MHz).
Minimum instruction execution time of 62.5 ns (at machine clock of 16 MHz)
• CPU addressing space of 16 Mbytes
Internal addressing of 24-bit
External accessing can be performed by selecting 8/16-bit bus width (external bus mode)
• Instruction set optimized for controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
High code efficiency
Enhanced precision calculation realized by the 32-bit accumulator
Signed multiplication/division instruction
• Instruction set designed for high level language (C) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Enhanced execution speed
8-byte instruction queue
• Enhanced interrupt function
Priority levels: 8 levels
External interrupt input ports: 4 ports
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS)
• Low-power consumption (stand-by) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
Hardware stand-by mode
Gear function
• Process
CMOS technology
• I/O port
General-purpose I/O ports (CMOS): 38
General-purpose I/O ports (TTL): 11
General-purpose I/O ports (N-ch open-drain): 8
Total: 57
• Timer
Timebase timer/watchdog timer: 1 channel
8-bit PWM timer: 4 channels
16-bit re-load timer: 3 channels
• 16-bit I/O timer
16-bit free-run timer: 1 channel
Input capture (ICU): 2 channels
• I/O simple serial interface
Clock synchronized transmission can be used.
• UART: 1 channel
Clock asynchronized or clock synchronized serial transmission can be selectively used.
• DTP/external interrupt circuit: 4 channels
A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt triggered
by an external input.
(Continued)
2
MB90246A Series
(Continued)
• Delayed interrupt generation module
Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter: 8 channels
8-bit or 10-bit resolution can be selectively used.
Starting by an external trigger input.
• 8-bit D/A converter
Resolution: 8 bits × 3 channels
• DSP interface for the IIR filter
Function dedicated to IIR calculation
Up to eight items of results of signed multiplication of 16 × 16 bits are added.
N
M
Execution time of Yk = Σ bn Yk – n + Σ am Xk – m : 0.625 µs (When oscillation is 32 MHz and when N = M =3)
n=0
m=0
Up to three N and M values can be set at your disposal.
3
MB90246A Series
■ PRODUCT LINEUP
Part number
Item
Classification
MB90246A
MB90V246
Mass-produced product
Evaluation product
ROM size
None
4 k × 8 bits
RAM size
6 k × 8 bits
CPU functions
The number of instructions: 412
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 4 bits, 8 bits, 16 bits, 32 bits
Minimum execution time: 62.5 ns (at machine clock of 16 MHz)
Interrupt processing time: 1.0 µs (at machine clock of 16 MHz, minimum
value)
Ports
General-purpose I/O ports (CMOS output): 38
General-purpose I/O ports (TTL input): 11
General-purpose I/O ports (N-ch open-drain output): 8
Total: 57
Timebase timer
18-bit counter
Interrupt interval: 0.256 ms, 1.024 ms, 4.096 ms, 16.384 ms
(at oscillation of 32 MHz)
Watchdog timer
Reset generation interval: 3.58 ms, 14.33 ms, 28.67 ms, 57.34 ms
(at oscillation of 32 MHz, minimum value)
8/16-bit PWM timer
Number of channels: 4
Pulse interval: 0.25 µs to 32.77 ms (at oscillation of 32 MHz)
16-bit re-load timer
Number of channels: 3
16-bit re-load timer operation
Interval: 125 ns to 131 ms (at machine clock of 16 MHz)
External event count can be performed.
16-bit
I/O timer
16-bit free-run
timer
Number of channel: 1
Overflow interrupts or intermediate bit interrupts may be generated.
Input capture
(ICU)
Number of channel: 2
Rewriting a register value upon a pin input (rising, falling, or both edges)
I/O simple serial interface
UART
Number of channels: 2
Clock synchronized transmission (62.5 kbps to 8 Mbps)
Clock asynchronized transmission (2404 bps to 500 kbps)
Clock synchronized transmission (250 kbps to 2 Mbps)
Transmission can be performed by bi-directional serial transmission or by
master/slave connection.
DTP/external interrupt circuit
Number of inputs: 4
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
External interrupt circuit or extended intelligent I/O service (EI2OS) can be used.
Delayed interrupt generation
module
An interrupt generation module for switching tasks
used in real-time operating systems.
(Continued)
4
MB90246A Series
(Continued)
Part number
MB90246A
MB90V246
Item
8/10-bit A/D converter
Conversion precision: 10-bit or 8-bit can be selectively used.
Number of inputs: 8
One-shot conversion mode (converts selected channel only once)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
Number of channels: 3
Resolution: 8 bits
Based on the R-2R system
8-bit D/A converter
DSP interface for the IIR
filter
Low-power consumption
(stand-by) mode
Function dedicated to IIR calculation
Up to 8 items of results of signed
multiplication of 16 × 16 bits are added.
N
M
Execution time of Yk = Σ bn Yk – n + Σ am Xk – m : 0.625 µs
n=0
m=0
(When oscillation is 32 MHz and when N = M = 3)
Up to three N and M values can be set at your disposal.
Sleep/stop/hardware stand-by/gear function
Process
CMOS
Power supply voltage for
operation*
4.5 V to 5.5 V
* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”) Assurance
for the MB90V246 is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an operating
temperature of 0 to 70 degrees centigrade, and an clock frequency of 1.6 MHz to 32 MHz.
Note: A 64-word RAM for product addition is supported in addition to the above RAMs.
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
MB90246A
MB90V246
×
FPT-100P-M05
PGA-256C-A02
: Available
×
× : Not available
Note: For more information about each package, see section “■ Package Dimensions.”
■ DIFFERENCES AMONG PRODUCTS
Memory Size
In evaluation with an evaluation chips, note the difference between the evaluation chip and the chip actually used.
The RAM size is 4 Kbytes for the MB90246A, and 6 Kbytes for the MB90V246.
5
MB90246A Series
■ PIN ASSIGNMENT
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
A01
A00
P17/D15
P16/D14
P15/D13
P14/D12
P13/D11
P12/D10
P11/D09
P10/D08
P07
P06
P05
P04
P03
P02
P01
P00
VCC
X1
X0
VSS
P57
P56/RD
P55/WR/WRL
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P71/ASR1
P72
P73
P74/TIN0/TOT0
P75/TIN1/TOT1
P76/TIN2/TOT2
AVCC
AVRH
AVRL
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
VSS
P64/AN4
P65/AN5
P66/AN6
P67/AN7
DVRH
DVRL
MD0
MD1
MD2
HST
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A02
A03
A04
A05
A06
A07
A08
A09
VSS
A10
A11
A12
A13
A14
A15
P40/A16
P41/A17
P42/A18
P43/A19
P44/A20
VCC
P45/A21
P46/A22
P47/A23
P70/ASR0
(FPT-100P-M05)
6
RST
P54/WRH
P53/HRQ
P52/HAK
P51/RDY
P50/CLK
PA5/SCK2
PA4/SOD2
PA3/SID2
PA2/SCK1
PA1/SOD1
PA0/SID1
P96/SCK0
P95/SOD0
P94/SID0
P93/INT3/PWM3
P92/INT2/ATG
P91/INT1
P90/INT0
P87/PWM2
P86/PWM1
P85/PWM0
P84/DAO2
P83/DAO1
P82/DAO0
MB90246A Series
■ PIN DESCRIPTION
Pin no.
Pin name
LQFP*
80
X0
81
X1
Circuit
type
Function
A
This is a crystal oscillator pin.
MD0 to MD2
C
This is an input pin for selecting operation modes.
Connect directly to VCC or VSS.
75
RST
B
This is external reset request signal.
50
HST
C
This is a hardware stand-by input pin.
P10 to P17
D
This is a general-purpose I/O port.
This function is valid in the 8-bit mode where the external bus is
valid.
47 to 49
91 to 98
D08 to D15
16 to 20,
22 to 24
P40 to P44,
P45 to P47
This is an I/O pin for the upper 8-bit of the external address data
bus.
This function is valid in the 16-bit mode where the external bus is
valid.
E
A16 to A20,
A21 to A23
70
P50
This is an output pin for the upper 8-bit of the external address bus.
This function is valid in the mode where the external bus is valid
and the upper address control register is set to select an address.
E
CLK
71
P51
P52
D
P53
D
P54
WRH
* : FPT-100P-M05
This is a general-purpose I/O port.
This function becomes valid when the hold function are disabled.
This is a hold acknowledge output pin.
This function becomes valid when the hold function is enabled.
D
HRQ
74
This is a general-purpose I/O port.
This function becomes valid when the external ready function are
disabled.
This is a ready input pin.
This function becomes valid when the external ready function is
enabled.
HAK
73
This is a general-purpose I/O port.
This function becomes valid when the CLK output is disabled.
This is a CLK output pin.
This function becomes valid when CLK output is enabled.
RDY
72
This is a general-purpose I/O port.
This function becomes valid in the bit where the upper address
control register is set to select a port.
This is a general-purpose I/O port.
This function becomes valid when the hold function are disabled.
This is a hold request input pin.
This function becomes valid when the hold function is enabled.
E
This is a general-purpose I/O port.
This function becomes valid, in the external bus 8-bit mode, or
WRH pin output is disabled.
This is a write strobe output pin for the upper 8-bit of the data bus.
This function becomes valid when the external bus 16-bit mode is
selected, and WRH output pin is enabled.
(Continued)
7
MB90246A Series
Pin no.
Pin name
LQFP*
76
P55
Circuit
type
Function
E
This is a general-purpose I/O port.
This function becomes valid when WRL/WR pin output is disabled.
WR
This is a write strobe output pin for the lower 8-bit of data bus.
This function becomes valid when WRL/WR pin output is enabled.
WRL is used for holding the lower 8-bit for write strobe in 16-bit
access operations, while WR is used for holding 8-bit data for write
strobe in 8-bit access operations.
WRL
77
P56
E
RD
This is a read strobe output pin for the data bus.
This function is valid in the mode where the external bus is valid.
78,28,27
P57,P73,P72
E
This is a general-purpose I/O port.
36 to 39,
41 to 44
P60 to P63,
P64 to P67
G
This is an I/O port of an N-ch open-drain type.
When the data register is read by a read instruction other than the
modify write instruction with the corresponding bit in ADER set at
“0”, the pin level is acquired. The value set in the data register is
output to the pin as is.
AN0 to AN3,
AN4 to AN7
25
P70
This is an analog input pin of the 8/10-bit A/D converter.
When using this input pin, set the corresponding bit in ADER at “1”.
Also, set the corresponding bit in the data register at “1”.
E
ASR0
26
P71
29 to 31
51 to 53
P74 to P76
This is a general-purpose I/O port.
This is a data input pin for input capture 0.
Because this input is used as required when the input capture 0 is
performing input operations, and it is necessary to stop outputs
from other functions unless such outputs are made intentionally.
E
ASR1
This is a general-purpose I/O port.
This is a data input pin of input capture 1.
Because this input is used as required when input capture 1 is
performing input operations, and it is necessary to stop outputs by
other functions unless such outputs are made intentionally.
E
This is a general-purpose I/O port.
This function becomes valid when outputs from 16-bit re-load timer
0 – 2 are disabled.
TIN0 to TIN 2
This is an input pin of 16-bit timer.
Because this input is used as required whin 16-bit timer 0 - 2 is
performing input operations,and it is necessary to stop outputs by
other functions unless such outputs are made intentionally.
TOT0 to TOT2
These are output pins for 16-bit re-load timer 0 and 1.
This function becomes valid when output from 16-bit re-load timer
0 – 2 are enabled.
P82 to P84
DAO0 to DAO2
* : FPT-100P-M05
8
This pin cannot be used as a general-purpose port.
H
This is a general-purpose I/O port.
This function becomes valid when data output from 8-bit D/A
converter 0 – 2 are disabled.
This is an output pin of 8-bit D/A converter.
This function becomes valid when data output from 8-bit D/A
converter 0 – 2 are enabled.
(Continued)
MB90246A Series
Pin no.
Pin name
LQFP*
54 to 56
P85 to P87
Circuit
type
Function
E
This is a general-purpose I/O port.
This function becomes valid when output from PWM0 – PWM2 are
disabled.
PWM0 to PWM2
57,
58
P90,
P91
This is an output pin of 8-bit PWM timer.
This function becomes valid when output from PWM0 – PWM2 are
enabled.
F
INT0,
INT1
59
60
61
P92
This is a general-purpose I/O port.
This is a request input pin of the DTP/external interrupt circuit ch.0
and 1.
Because this input is used as required when the DTP/external
interrupt circuit is performing input operations, and it is necessary
to stop outputs from other functions unless such outputs are made
intentionally.
E
This is a general-purpose I/O port.
INT2
This is an input pin of the DTP/external interrupt circuit ch.2.
Because this input is used as required when the DTP/external
interrupt circuit is performing input operations, and it is necessary
to stop outputs from other functions unless such outputs are made
intentionally.
ATG
This is a trigger input pin of the 8/10-bit A/D converter.
Because this input is used as requited when the 8/10-bit A/D
converter is performing input operations, and it is necessary to
stop outputs by other functions unless such outputs are made
intentionally.
P93
E
This is a general-purpose I/O port.
This function is always valid.
This function becomes valid when output from PWM3 is disabled.
INT3
This is a request input of the DTP/external interrupt circuit
ch. 3.
Because this input is used as required when the DTP/external
interrupt circuit is performing input operations, and it is necessary
to stop outputs from other functions unless such output are made
intentionally.
PWM3
This is an output pin of 8-bit PWM timer.
This function becomes valid when output from PWM3 is enabled.
P94
SID0
* : FPT-100P-M05
E
This is a general-purpose I/O port.
This function becomes valid when serial data output from UART is
disabled.
This is a serial data I/O pin of UART.
This function becomes valid when serial data output from UART is
enabled.
Because this input is used as required when UART is performing
input operations, and it is necessary to stop outputs by other
functions unless such outputs are made intentionally.
(Continued)
9
MB90246A Series
Pin no.
Pin name
LQFP*
62
P95
Circuit
type
E
SOD0
63
P96
This is a general-purpose I/O port.
This function becomes valid when data output from UART is
disabled.
This is a data output pin of UART.
This function becomes valid when data output from UART is
enabled.
E
SCK0
This is a general-purpose I/O port.
This function becomes valid when clock output from UART is
disabled.
This is a clock I/O pin of UART.
This function becomes valid when clock output from UART is
enabled.
Because this input is used as required when UART is performing
input operations, and it is necessary to stop outputs by other
functions unless such outputs are made intentionally.
1 to 6,
100,
99
A02 to A07,
A01,
A00
E
This is an output pin for the lower 8-bit of the external address bus.
7,
8,
10 to 15
A08,
A09,
A10 to A15
E
This is an output pin for the middle 8-bit of the external address
bus.
This function is valid in the mode where the external bus is valid
and the middle address control refister is set to select an address.
PA0
E
This is a general-purpose I/O port.
64
SID1
65
PA1
This is a data input pin of I/O simple serial interface 1.
Because this input is used as required when I/O simple serial
interface 1 is performing input operations, and it is necessarey to
stop outputs by other functions unless such outputs are made
intentionally.
E
SOD1
66
PA2
SCK1
* : FPT-100P-M05
10
Function
This is a general-purpose I/O port.
This function becomes valid when data output from I/O simple
serial interface 1 is disabled.
This is a data output pin of I/O simple serial interface 1.
This function becomes valid when data output from I/O simple
serial interface 1 is enabled.
E
This is a general-purpose I/O port.
This function becomes valid when clock output from I/O simple
serial interface 1 is disabled.
This is a clock output pin of I/O simple serial interface 1.
This function becomes valid when clock output from I/O simple
serial interface 1 is enabled.
(Continued)
MB90246A Series
(Continued)
Pin no.
Pin name
LQFP*
67
PA3
Circuit
type
E
SID2
68
PA4
PA5
E
D00 to D07
This is a general-purpose I/O port.
This function becomes valid when data output from I/O simple
serial interface 2 is disabled.
This is a data output pin of I/O simple serial interface 2.
This function becomes valid when data output from I/O simple
serial interface 2 is enabled.
E
SCK2
83 to 90
This is a general-purpose I/O port.
This is a data input pin of I/O simple serial interface 2.
Because this input is used as required when is performing input
operations, and it is I/O simple serial interface 2 necessarey to stop
outputs by other functions unless such outputs are made
intentionally.
SOD2
69
Function
This is a general-purpose I/O port.
This function becomes valid when clock output from I/O simple
serial interface 2 is disabled.
This is clock output pin of I/O simple serial interface 2.
This function becomes valid when clock output from I/O simple
serial interface 2 is enabled.
D
This is an I/O pin for the lower 8-bit of the external data bus.
21,
82
VCC
Power
supply
This is power supply to the digital circuit.
9,
40,
79
VSS
Power
supply
This is a ground level of the digital circuit.
32
AVCC
Power
supply
This is power supply to the analog circuit.
Make sure to turn on/turn off this power supply with a voltage
exceeding AVCC applied to VCC.
33
AVRH
Power
supply
This is a reference voltage input to the A/D converter.
Make sure to turn on/turn off this power supply with a voltage
exceeding AVRH applied to AVCC.
34
AVRL
Power
supply
This is a reference voltage input to the A/D converter.
35
AVSS
Power
supply
This is a ground level of the analog circuit.
45
DVRH
Power
supply
This is an external reference power supply pin for the D/A
converter.
46
DVRL
Power
supply
This is an external reference power supply pin for the D/A
converter.
* : FPT-100P-M05
11
MB90246A Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
Clock
suspension
X1
• For oscillation of 32 MHz
• Oscillation feedback resistor approx.
1 MΩ
N-ch
X0
Clock input
B
• CMOS level hysteresis input
(without stand-by control)
• Pull-up resistor approx. 50 kΩ
VCC
P-ch type trigger
R
N-ch type trigger
VSS
Digital input
CMOS
C
• CMOS level hysteresis input
(without stand-by control)
VCC
P-ch type trigger
R
N-ch type trigger
VSS
Digital input
CMOS
D
P-ch
R
N-ch
Digital output
• CMOS level output
• TTL level input
(with stand-by control)
Digital output
Digital input
TTL
Standby control signal
(Continued)
12
MB90246A Series
(Continued)
Type
Circuit
Remarks
E
• CMOS level output
• CMOS level hysteresis input
(with stand-by control)
P-ch Digital output
R
N-ch
Digital output
Digital input
CMOS
Standby control signal
F
P-ch
R
N-ch
• CMOS level input
• CMOS level hysteresis input
(with stand-by control (during interrupt
disable))
Digital output
Digital output
Digital input
Standby control signal
(during interrupt disable)
G
•
•
•
•
R
Digital output
N-ch open-drain
CMOS level output
CMOS level hysteresis input
Analog input
(with analog control)
Analog input
Digital input
ADER
CMOS
H
P-ch
R
N-ch
Digital output
• CMOS level output
• Analog output
• CMOS level hysteresis input
(with stand-by control)
Digital output
Analog input
Digital input
Standby control signal CMOS
13
MB90246A Series
■ HANDLING DEVICES
1. Make Sure that the Voltage not Exceed the Maximum Rating (to Avoid a Latch-up)
In CMOS ICs, a latch-up phenomenon is caused when an voltage exceeding VCC or an voltage below VSS is
applied to input or output pins or a voltage exceeding the rating is applied across VCC and VSS.
When a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal
break-down of devices. To avoid the latch-up, make sure that the voltage not exceed the maximum rating.
In turning on/turning off the analog power supply, make sure the analog power voltage (AVCC, AVRH) and analog
input voltages not exceed the digital voltage (VCC).
2. Connection of Unused Pins
Leaving unused pins open may result in abnormal operations. Clamp the pin level by connecting it to a pull-up
or a pull-down resistor.
3. Notes on Using External Clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected.
• Using external clock
X0
Open
X1
MB90246A series
4. Power Supply Pins
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to
avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to
lower the electro-magnetic emission level and abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total current rating.
Make sure to connect VCC and VSS pins via lowest impedance to power lines.
It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pin near the device.
5. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand
area for stabilizing the operation.
14
MB90246A Series
6. Turning-on Sequence of Power Supply to A/D Converter, D/A Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL), D/A converter power supply and
analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital supplies simultaneously is
acceptable).
7. Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
8. “MOV @AL, AH”, “MOVW @AL, AH” Instructions
When the above instruction is performed to I/O space, an unnecessary writing operation may be performed
(#FF, #FFFF) in the internal bus.
Use the compiler function for inserting an NOP instruction before the above instructions to avoid the writing
operation.
Accessing RAM space with the above instruction does not cause any problem.
9. Initialization
In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers
turning on the power again.
10.External Reset Input
To reset the internal securely, “L” level input to the RST pin must be at least 5 machine cycle.
11.HST Pin
Make sure HST pin is set to “H” level when turn on the power supply. Also make sure HST pin is never set to
“L” level, when RST pin is set to “L” level.
12.CLK Pin
X1
a case 32 MHz
STOP
To the inside
X0
2 deviding circuit
P50/CLK*
P50 output
CLK output
P50 input
*: At P50/CLK pin in the external bus mode, CLK output is selected as an initial value.
15
MB90246A Series
■ BLOCK DIAGRAM
F2MC–16F.
CPU
Interrupt controller
X0
X1
RST
HST
Clock control block
(including timebase timer)
DVRH
DVRL
8-bit
D/A converter
3
Port 1
8
P10/D08 to
P17/D15
16
8
A00 to A15
D00 to D07
P40/A16 to
P47/A23
P50/CLK
P51/RDY
P52/HAK
P53/HRQ
P54/WRH
P55/WR/WRL
P56/RD
P57
3
8
2
8-bit
PWM timer
× 4 channels
External bus
interface
Port 7
3
P85/PWM0 to
P87/PWM2
3
2
P93/INT3/PWM3
DTP/external
interrupt
circuit 3
Port 9
2
UATR
4
I/O
simple serial 2
interface
Input compare
(ICU)
Port A
16-bit
free-run timer
3
P90/INT0
P91/INT1
DTP/external
interrupt circuit
0, 1, 2
DSP interface for
the IIR filter
Port 9
P92/INT2/ATG
RAM
AVRH
AVRL
AVCC
AVSS
8/10-bit
A/D converter
8
8
Port 6
P94/SID0
P95/SOD0
P96/SCK0
16-bit
re-load timer
16-bit I/O timer
P70/ASR0
P71/ASR1
Internal data bus
Port 4, 5
P74/TIN0/TOT0 to
P76/TIN2/TOT2
16
3
13
3
Other pins
MD0 to MD2,
VCC,VSS
P82/DAO0 to
P84/DAO2
Port 8
P72
P73
P60/AN0 to
P67/AN7
3
8
PA0/SID1
PA1/SOD1
PA2/SCK1
PA3/SID2
PA4/SOD2
PA5/SCK2
MB90246A Series
MEMORY MAP
External ROM
external bus mode
FFFFFFH
External area
001980H
001900H
001100H
I/O
External area
RAM
Register
000100H
External area
0000C0H
000000H
I/O
: Internal access memory
: Enternal access memory
The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler
small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address,
enabling reference of the table on the ROM without stating “far”.
17
MB90246A Series
■ F2MC-16F CPU PROGRAMMING MODEL
(1) Dedicated Registers
AH
AL
: Accumlator (A)
Dual 16-bit register used for storing results of calculation etc. The two 16-bit
registers can be combined to be used as a 32-bit register.
USP
: User stack pointer (USP)
The 16-bit pointer for containing a user stack address.
SSP
: System stack pointer (SSP)
The 16-bit pointer for displaying the status of the system stack address.
PS
: Processor status (PS)
The 16-bit register for displaying the system status.
PC
: Program counter (PC)
The 16-bit register for displaying storing location of the current instruction code.
USPCU
: User stack upper limit register (USPCU)
The 16-bit register for specifying the upper limit of the user stack.
SSCPU
: System stack upper limit register (SSPCU)
The 16-bit register for specifying the upper limit of the system stack.
USPCL
: User stack lower limit register (USPCL)
The 16-bit register for specifying the lower limit of the user stack.
SSPCL
: System stack lower limit register (SSPCL)
The 16-bit register for specifying the lower limit of the system stack.
DPR
: Direct page register (DPR)
The 8-bit register for specifying bit 8 through 15 of the operand address in the
short direct addressing mode.
PCB
: Program bank register (PCB)
The 8-bit register for displaying the program space.
DTB
: Data bank register (DTB)
The 8-bit register for displaying the data space.
USB
: User stack bank register (USB)
The 8-bit register for displaying the user stack space.
SSB
: System stack bank register (SSB)
The 8-bit register for displaying the system stack space.
ADB
: Additional data bank register (ADB)
The 8-bit register for displaying the additional data.
8-bit
16-bit
32-bit
18
MB90246A Series
(2) General-purpose Registers
Maximum of 32 banks
R7
R6
RW7
R5
R4
RW6
R3
R2
RW5
R1
R0
RW4
RL3
RL2
RW3
RL1
RW2
RW1
RL0
RW0
000180 H + (RP × 10 H )
16-bit
(3) Processor Status (PS)
ILM
RP
CCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6
PS
ILM2 ILM1 ILM0
Initial value
0
0
0
bit 5 bit 4
bit 3 bit 2
bit 1
bit 0
B4
B3
B2
B1
B0
—
I
S
T
N
Z
V
C
0
0
0
0
0
—
0
1
X
X
X
X
X
— : Unused
X : Indeterminate
19
MB90246A Series
■ I/O MAP
Address
Abbreviated
register name
000000H
000001H
Read/
write
Register name
Resource
name
Initial value
Port 1
XXXXXXXXB
(System reservation area)*1
PDR1
000002H
Port 1 data register
R/W!
(System reservation area)*1
000003H
000004H
PDR4
Port 4 data register
R/W!
Port 4
XXXXXXXXB
000005H
PDR5
Port 5 data register
R/W!
Port 5
XXXXXXXXB
000006H
PDR6
Port 6 data register
R/W!
Port 6
11111111B
000007H
PDR7
Port 7 data register
R/W!
Port 7
– XXXXXXXB
000008H
PDR8
Port 8 data register
R/W!
Port 8
XXXXXX – – B
000009H
PDR9
Port 9 data register
R/W!
Port 9
– XXXXXXXB
00000AH
PDRA
Port A data register
R/W!
Port A
– – XXXXXXB
Port 1
00000000B
00000BH
to
00000FH
(Vacancy)
000010H
(System reservation area)*1
000011H
DDR1
000012H
Port 1 direction register
R/W
(System reservation area)*1
000013H
000014H
DDR4
Port 4 direction register
R/W
Port 4
00000000B
000015H
DDR5
Port 5 direction register
R/W
Port 5
00000000B
000016H
ADER
Analog input enable register
R/W
Port 6,
8/10-bit A/D
converter
11111111B
000017H
DDR7
Port 7 direction register
R/W
Port 7
–0000000B
000018H
DDR8
Port 8 direction register
R/W
Port 8
000000––B
000019H
DDR9
Port 9 direction register
R/W
Port 9
– XXXXXXXB
00001AH
DDRA
Port A direction register
R/W
Port A
––000000B
00001BH
to
00001FH
(Vacancy)
000020H
SCR1
Serial control status register 1
000021H
SSR1
Serial status register 1
000022H
SDR1L
Serial data register 1 (L)
R/W
000023H
SDR1H
Serial data register 1 (H)
R/W
R/W
R
10000000B
I/O simple serial
interface 1
–––––––1B
XXXXXXXXB
XXXXXXXXB
(Continued)
20
MB90246A Series
Address
Abbreviated
register name
Read/
write
000024H
SCR2
Serial control status register 2
000025H
SSR2
Serial status register 2
000026H
SDR2L
Serial data register 2 (L)
R/W
000027H
SDR2H
Serial data register 2 (H)
R/W
XXXXXXXXB
000028H
UMC
Mode control register
R/W
00000100B
000029H
USR
Status register
R/W
00010000B
00002AH
UIDR/
UODR
Input data register/
output data register
R/W
00002BH
URD
Rate and data register
R/W
00002CH
PWMC3
PWM3 operating mode control
register
R/W
Register name
00002DH
R/W
R
PRLL3
PWM3 re-road register (L)
R/W
00002FH
PRLH3
PWM3 re-road register (H)
R/W
000030H
ENIR
DTP/interrupt enable register
R/W
000031H
EIRR
DTP/interrupt factor register
R/W
000032H
ELVR
Request level setting register
R/W
000033H
10000000B
I/O simple serial
interface 2
UART
–––––––1B
XXXXXXXXB
XXXXXXXXB
00000000B
8-bit PWM
timer 3
0 0 0 0 0XX1 B
8-bit PWM
timer 3
XXXXXXXXB
XXXXXXXX B
––––0000B
DTP/external
interrupt circuit
––––0000B
00000000B
(Vacancy)
PWMC0
PWM0 operating mode control
register
000035H
R/W
8-bit PWM
timer 0
0 0 0 0 0XX1 B
(Vacancy)
000036H
PRLL0
PWM0 re-road register (L)
R/W
000037H
PRLH0
PWM0 re-road register (H)
R/W
000038H
PWMC1
PWM1 operating mode control
register
R/W
000039H
8-bit PWM
timer 0
8-bit PWM
timer 1
XXXXXXXXB
XXXXXXXX B
0 0 0 0 0XX1 B
(Vacancy)
00003AH
PRLL1
PWM1 re-road register (L)
R/W
00003BH
PRLH1
PWM1 re-road register (H)
R/W
00003CH
PWMC2
PWM2 operating mode control
register
R/W
00003DH
8-bit PWM
timer 1
8-bit PWM
timer 2
XXXXXXXXB
XXXXXXXX B
0 0 0 0 0XX1 B
(Vacancy)
00003EH
PRLL2
PWM2 re-road register (L)
R/W
00003FH
PRLH2
PWM2 re-road register (H)
R/W
Timer control status register 0
lower digits
R/W
Timer control status register 0
upper digits
R/W
000040H
TMCSR0
000041H
Initial value
(Vacancy)
00002EH
000034H
Resource
name
8-bit PWM
timer 2
16-bit re-load
timer 0
XXXXXXXXB
XXXXXXXX B
00000000B
––––0000B
(Continued)
21
MB90246A Series
Address
000042H
000043H
000044H
000045H
Abbreviated
register name
TMR0
16-bit timer register 0
TMRLR0
TMCSR1
000049H
00004DH
TMR1
TMRLR1
00000000B
Timer control status register 1
upper digits
R/W
––––0000B
16-bit timer register 1
TMCSR2
000051H
000055H
16-bit re-load register 1
TMR2
TMRLR2
Timer control status register 2
upper digits
R/W
––––1111B
16-bit timer register 2
R
16-bit re-load register 2
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Vacancy)
00005BH
DACR0
D/A control register 0
R/W
00005CH
DADR1
D/A data register 1
R/W
00005DH
DACR1
D/A control register 1
R/W
00005EH
DADR2
D/A data register 2
R/W
00005FH
DACR2
D/A control register 2
R/W
IPCP0
Input capture register 0
000064H
16-bit re-load
timer 2
R/W
R/W
000063H
XXXXXXXXB
00000000B
D/A data register 0
000062H
XXXXXXXXB
R/W
DADR0
000061H
XXXXXXXXB
R/W
00005AH
000060H
XXXXXXXXB
Timer control status register 2
lower digits
000056H
to
000059H
22
R
16-bit re-load
timer 1
(Vacancy)
000050H
000054H
XXXXXXXXB
R/W
00004FH
000053H
XXXXXXXXB
Timer control status register 1
lower digits
00004EH
000052H
R/W
XXXXXXXXB
(Vacancy)
000048H
00004CH
Initial value
XXXXXXXXB
R
16-bit re-load register 0
000047H
00004BH
Resource
name
16-bit re-load
timer 0
000046H
00004AH
Read/
write
Register name
IPCP1
ICS0
Input capture register 1
Input capture control register
8-bit D/A
converter 0
XXXXXXXXB
8-bit D/A
converter 1
XXXXXXXXB
8-bit D/A
converter 2
XXXXXXXXB
R/W
–––––––0B
–––––––0B
XXXXXXXXB
R
R
–––––––0B
16-bit I/O timer
(input
capture 0, 1)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
(Continued)
MB90246A Series
Address
Abbreviated
register name
000065H
to
00006BH
00006CH
00006DH
00006EH
Read/
write
Register name
Resource
name
Initial value
(Vacancy)
TCDT
Timer data register
R/W
TCCS
Timer control status register
R/W
00006FH
16-bit I/O timer
(16-bit free-run
timer)
00000000B
00000000B
00000000B
(Vacancy)
000070H
ADCSL
A/D control status register lower
digits
R/W
000–0000B
000071H
ADCSH
A/D control status register upper
digits
R/W
–000––00B
ADCT
Conversion time setting register
R/W
000072H
000073H
000074H
ADTL0
000075H
ADTH0
000076H
ADTL1
000077H
ADTH1
000078H
ADTL2
000079H
ADTH2
00007AH
ADTL3
00007BH
ADTH3
R
A/D data register 0
R
A/D data register 1
A/D data register 2
A/D data register 3
00007CH
to
00007FH
MCSR
000081H
B
––––––* *
R
XXXXXXXXB
R
––––––* *
R
XXXXXXXXB
R
––––––* *
B
B
B
Product addition control status
register lower digits
R/W
XXX 0 XXX 0 B
Product addition control status
register digits
R/W
– XXXXXXXB
00000000B
R/W
000083H
MCCRH
Product addition continuation
control register upper digits
R/W
000088H
––––––* *
R
Product addition continuation
control register lower digits
000087H
XXXXXXXXB
XXXXXXXXB
MCCRL
000086H
8/10-bit A/D
converter
R
000082H
000085H
XXXXXXXXB
(Vacancy)
000080H
000084H
XXXXXXXXB
MDORL
MDORM
MDORH
R
Production addition output
register
R
R
DSP interface
for the IIR filter
––––––00B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
23
MB90246A Series
(Continued)
Address
Abbreviated
register name
000089H
to
00008FH
(Vacancy)
000090H
to
00009EH
(System reservation area)*1
00009FH
DIRR
Delayed interrupt factor
generation/
cancellation register
0000A0H
STBYC
Standby control register
0000A1H
to
0000A3H
Resource
name
Initial value
–––––––0B
0 0 0 1 XXXXB
R/W
Delayed
interrupt
generation
module
R/W
Low-power
consumption
(stand-by) mode
(System reservation area)*1
0000A4H
HACR
Upper address control register
W
0000A5H
EPCR
External pin control register
W
0000A8H
WDTC
Watchdog timer control register
R/W
Watchdog timer
XXXXXXXXB
0000A9H
TBTC
Timebase timer control register
R/W
Timebase timer
–XX0 0 1 0 0 B
0000B0H
ICR00
Interrupt control register 00
R/W
00000111B
0000B1H
ICR01
Interrupt control register 01
R/W
00000111B
0000B2H
ICR02
Interrupt control register 02
R/W
00000111B
0000B3H
ICR03
Interrupt control register 03
R/W
00000111B
0000B4H
ICR04
Interrupt control register 04
R/W
00000111B
0000B5H
ICR05
Interrupt control register 05
R/W
00000111B
0000B6H
ICR06
Interrupt control register 06
R/W
00000111B
0000B7H
ICR07
Interrupt control register 07
R/W
0000B8H
ICR08
Interrupt control register 08
R/W
0000B9H
ICR09
Interrupt control register 09
R/W
00000111B
0000BAH
ICR10
Interrupt control register 10
R/W
00000111B
0000BBH
ICR11
Interrupt control register 11
R/W
00000111B
0000BCH
ICR12
Interrupt control register 12
R/W
00000111B
0000BDH
ICR13
Interrupt control register 13
R/W
00000111B
0000BEH
ICR14
Interrupt control register 14
R/W
00000111B
0000BFH
ICR15
Interrupt control register 15
R/W
00000111B
0000C0H
to
0000FFH
24
Read/
write
Register name
(External area)*3
External bus pin
Interrupt
controller
*2
*2
00000111B
00000111B
MB90246A Series
Descriptions for read/write
R/W: Readable and writable
R: Read only
W: Write only
R/W!: Bits for reading operation only or writing operation only are included. Refer to the register lists for specific
resource for detailed information.
Descriptions for initial value
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is indeterminate.
– : This bit is not used. The initial value is indeterminate.
* : The storage type varies with the value of the ADCSH CREG bit.
*1: Access prohibited.
*2: The initial value varies with bus mode.
*3: This area is the only external access area having an address of 0000FFH or lower. Access to any of the addresses
specified as reserved areas in the table is handled as if an internal area were accessed. A signal for accessing
an external bus is not generated.
*4: When a register described as R/W! or W in the read/write column is accessed by a bit setting instruction or
other read modify write instructions, the bit pointed to by the instruction becomes a set value. If a bit is writable
by other bits, however, malfunction occurs. You must not, therefore, access that register using these instructions.
Note: For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial
value. Note that the values are different from reading results.
25
MB90246A Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt source
EI2OS
support
Interrupt vector
Number
Interrupt control register
Address
ICR
Address
Reset
×
# 08
08H
FFFFDCH
—
—
INT9 instruction
×
# 09
09H
FFFFD8H
—
—
Exception
×
# 10
0AH
FFFFD4H
—
—
DTP/external interrupt circuit
Channel 0
# 11
0BH
FFFFD0H
ICR00
0000B0H
DTP/external interrupt circuit
Channel 1
# 13
0DH
FFFFC8H
ICR01
0000B1H
Input capture (ICU) Channel 0
# 15
0FH
FFFFC0H
ICR02
0000B2H
Input capture (ICU) Channel 1
# 17
11H
FFFFB8H
I/O simple serial interface
Channel 2
ICR03
0000B3H
# 18
12H
FFFFB4H
DTP/external interrupt circuit
Channel 2
# 19
13H
FFFFB0H
ICR04
0000B4H
DTP/external interrupt circuit
Channel 3
# 21
15H
FFFFA8H
ICR05
0000B5H
16-bit free-run timer Overflow
# 23
17H
FFFFA0H
ICR06
0000B6H
Timebase timer Interval interrupt
# 25
19H
FFFF98H
ICR07
0000B7H
16-bit re-load timer Channel 0
# 27
1BH
FFFF90H
ICR08*1
0000B8H
# 28
1CH
FFFF8CH
# 29
1DH
FFFF88H
ICR09*1
0000B9H
# 30
1EH
FFFF84H
# 31
1FH
FFFF80H
ICR10*1
0000BAH
# 32
20H
FFFF7CH
# 33
21H
FFFF78H
ICR11*1
0000BBH
# 34
22H
FFFF74H
I/O simple serial interface
Channel 1
# 35
23H
FFFF70H
ICR12
0000BCH
UART transmission complete
# 37
25H
FFFF68H
ICR13
0000BDH
UART reception complete
# 39
27H
FFFF60H
ICR14
0000BEH
8-bit PWM timer Channel 0
×
16-bit re-load timer Channel 1
8-bit PWM timer Channel 1
×
16-bit re-load timer Channel 2
8-bit PWM timer Channel 2
×
8/10-bit A/D converter
measurement complete
8-bit PWM timer Channel 3
×
Delayed interrupt generation
module
×
# 42
2AH
FFFF54H
ICR15
0000BFH
Stack fault
×
# 255
FFH
FFFC00H
—
—
Priority*2
: Can be used
× : Can not be used
: Can be used. With Extended intelligent I/O service (EI2OS) stop function at abnormal operation.
: Can be used if interrupt request using ICR are not commonly used.
26
High
Low
MB90246A Series
*1: • Interrupt levels for peripherals that commonly use the ICR register are in the same level.
• When the extended intelligent I/O service (EI2OS) is specified in a peripheral device commonly using the ICR
register, only one of the functions can be used.
• When the extended intelligent I/O service (EI2OS) is specified for one of the peripheral functions, interrupts
can not be used on the other function.
*2: The level shows priority of same level of interrupt invoked simultaneously.
27
MB90246A Series
■ PERIPHERALS
1. I/O Port
(1) Input/output Port
Ports 1, 4, 5, 7 to 9, A are general-purpose I/O ports having a combined function as an external bus pin and a
resource input. The input output ports function as general-purpose I/O port only in the single-chip mode. In the
external bus mode, the ports are configured as external bus pins, and part of pins for port 4 can be configured
as general-purpose I/O port by setting the bus control signal select register (ECSR).
• Operation as output port
The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.
Writing data to PDR register when the port is configured as output, the data is retained in the output latch in
the PDR and directly output to the pin.
The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR
register.
Note: When a read-modify-write type instruction (e.g. bit set instruction) is performed to the port data register,
the destination bit of the operation is set to the specified value, not affecting the bits configured by the
DDR register for output, however, values of bits configured by the DDR register as inputs are changed
because input values to the pins are written into the output latch. To avoid this situation, configure the
pins by the DDR register as output after writing output data to the PDR register when configuring the bit
used as input as outputs.
• Operation as input port
The pin is configured as an input by setting the corresponding bit of the DDR register to “0”.
When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance
status.
When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs
are unaffected.
Reading the PDR register reads out the pin level (“0” or “1”).
• Block diagram
PDR (port data register)
Internal data bus
PDR read
Output latch
P-ch
PDR write
Pin
DDR (port direction register)
Direction latch
N-ch
DDR write
Standby control (SPL=1)
DDR read
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
28
MB90246A Series
(2) N-ch Open-drain Port
Port 6 is general-purpose I/O port having a combined function as resource input/output. Each pin can be switched
between resource and port bitwise.
• Operation as output port
When a data is written into the PDR register, the data is latched to the output latch of PDR. When the output
latch value is set to “0”, the output transistor is turned on and the pin status is put into an “L” level output, while
writing “1” turns off the transistor and put the pin in a high-impedance status.
If the output pin is pulled-up, setting output latch value to “1” puts the pin in the pull-up status.
Reading the PDR register returns the pin value (same as the output latch value in the PDR).
Note: Execution of a read-modify-write instruction (e.g. bit set instruction) reads out the output latch value rather
than the pin value, leaving output latch that is not manipulated unchanged.
• Operation as input port
Setting corresponding bit of the PDR register to “1” turns off the output transistor and the pin is put into a highimpedance status.
Reading the PDR register returns the pin value (“0” or “1”).
• Block diagram
ADER (analog input enable register)
ADER read
To analog input
ADER latch
Internal data bus
ADER write
PDR (port data register)
RMW
(read-modify-write
type instruction)
PDR read
Output trigger
Pin
Output latch
PDR write
Standby control (SPL=1)
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
29
MB90246A Series
(3) Register Configuration
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
000001H
P17
P16
P15
P14
P13
P12
P11
P10
(System reservation area)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address bit 15. . . . . . . . . . . . bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000004H
P47
P46
P45
P44
P43
P42
P41
P40
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(PDR5)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
000005H
P57
P56
P55
P54
P53
P52
P51
P50
(PDR4)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000006H
P67
P66
P65
P64
P63
P62
P61
P60
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
000007H
—
P76
P75
P74
P73
P72
P71
P70
(PDR6)
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000008H
P87
P86
P85
P84
P83
P82
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
000009H
—
P96
P95
P94
P93
P92
P91
P90
(PDR8)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15. . . . . . . . . . . . bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00000AH
(Vacancy)
—
—
PA5
PA4
PA3
PA2
PA1
PA0
—
—
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
R/W
.
.
.
.
.
.
.
.
.
.
.
. . bit 0
bit 7
P17
P16
P15
P14
P13
P12
P11
P10
(System reservation area)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address bit 15. . . . . . . . . . . . bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000014H
P47
P46
P45
P44
P43
P42
P41
P40
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(DDR5)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
000015H
P57
P56
P55
P54
P53
P52
P51
P50
(DDR4)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address bit 15. . . . . . . . . . . . bit 8
000016H
(DDR7)
Port 8 data register
(PDR8)
Port 9 data register
(PDR9)
Address
Address
000011H
Port 6 data register
(PDR6)
Port 7 data register
(PDR7)
Address bit 15. . . . . . . . . . . . bit 8
(PDR9)
Port 4 data register
(PDR4)
Port 5 data register
(PDR5)
Address bit 15. . . . . . . . . . . . bit 8
(PDR7)
Port 1 data register
(PDR1)
Port A data register
(PDRA)
Port 1 direction register
(DDR1)
Port 4 direction register
(DDR4)
Port 5 direction register
(DDR5)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
P67
P66
P65
P64
P63
P62
P61
P60
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Analog input enable register
(ADER)
(Continued)
30
MB90246A Series
(Continued)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
000017H
—
P76
P75
P74
P73
P72
P71
P70
(ADER)
—
Address
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.
.
.
.
.
.
.
.
.
.
.
.
bit
7
bit
6
bit
5
bit
4
bit
3
bit 2
bit 15
bit 8
Port 7 direction register
(DDR7)
000018H
(DDR9)
P86
P85
P84
P83
P82
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
000019H
—
P96
P95
P94
P93
P92
P91
P90
00001AH
Port 8 direction register
(DDR8)
bit 7 . . . . . . . . . . . . . bit 0
Port 9 direction register
(DDR9)
(DDR8)
. . . . . . . .R/W
...
R/W
R/W . R/W
R/W
R/W
R/W
R/W
.
.
.
.
.
.
.
.
.
.
.
.
bit 15
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
(Vacancy)
bit 0
P87
Address
Address
bit 1
bit 1
bit 0
—
—
PA5
PA4
PA3
PA2
PA1
PA0
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Port A direction register
(DDRA)
R/W : Readble and writable
— : Unused
31
MB90246A Series
2. Timebase Timer
The timebase timer is a 18-bit free-run counter (timebase counter) for counting up in synchronization to the
internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from
four types of 213/HCLK, 215/HCLK, 217/HCLK, and 219/HCLK.
The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation
stabilization time or the watchdog timer etc.
(1) Register Configuration
• Timebase timer control register (TBTC)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
0000A9H
RESV
—
—
TBIE
TBOF
TBR
TBC1
TBC0
R/W
—
—
R/W
R/W
W
R/W
R/W
bit 7 . . . . . . . . . . . . . bit 0
(WDTC)
Initial value
0XX0 0 0 0 0 B
R/W: Readable and writable
R : Read only
W : Write only
— : Unused
X : Indeterminate
RESV : Reserved bit
(2) Block Diagram
To 8-bit
PWM timer
To watchdog timer
Timebase timer
counter
Divided-by-2
of HCLK
× 21 × 22 × 2 3
...
...
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
OF
OF
OF
OF
To oscillation stabilization
time selector of clock control block
Power-on reset
Start stop mode
CKSCR : MCS = 1→0*1
Counter
clear circuit
Interval
timer selector
Set TBOF
Clear TBOF
Timebase timer control register
(TBTC)
RESV
—
—
TBIE TBOF TBR
Timebase timer
interrupt signal
#25(19H)*2
OF : Overflow
HCLK: Oscillation clock
*1
: Switch machine clock from oscillation clock to PLL clock
*2
: Interrupt signal
32
TBC1 TBC0
MB90246A Series
3. Watchdog Timer
The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when
the counter is not cleared for a preset period of time.
(1) Register Configuration
• Watchdog timer control register (WDTC)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
0000A8H
(TBTC)
bit 6
bit 5
bit 4
PONR STBR WRST ERST
R
R
R
bit 3
bit 2
bit 1
bit 0
SRST
WTE
WT1
WT0
R
W
W
W
R
Initial value
XXXXXXXX B
R : Read only
W: Write only
X : Indeterminate
(2) Block Diagram
Watchdog timer control register (WDTC)
PONR STBR WRST ERST SRST WTE WT1
WT0
2
Watchdog timer
CLR and start
Overflow
Start sleep mode
Start hold status
Start stop mode
Counter clear
control circuit
Count clock
selector
2-bit
counter
CLR
Watchdog reset
generation circuit
To internal reset
generation circuit
CLR
4
Clear
(Timebase timer counter)
Divided-by-2
of HCLK
× 21 × 22
...
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
HCLK: Oscillation clock
33
MB90246A Series
4. 8-bit PWM Timer
The 8-bit PWM timer is a re-load timer module that can generate a pulse wave with any period/duty ratio. It uses
pulse output control according to timer operation for PWM (Pulse Width Modulation) output.
An appropriate external circuit allows the 8-bit PWM timer to operate as a D/A converter.
The 8-bit PWM timer module consists of two 8-bit re-load registers used to specify “H” width and “L” width and
of a down counter that is loaded alternately with those values and counts down.
• A pulse waveform with any period and duty ratio is generated.
• An output pulse’s duty ratio of 0.4 to 99.6 percent can be set.
• An appropriate external circuit allows this PWM timer to operate as a D/A converter.
• An interrupt request can be generated by counter underflow.
• The count clock can be selected from two types of timebase timer output.
(1) Register Configuration
• PWM0 to 3 operating mode control register (PWM)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
PWMC0 : 000034H
(Vacancy)
PWMC1 : 000038H
PEN
PWMC2 : 00003CH
R/W
PWMC3 : 00002CH
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PCKS
POE
PIE
PUF
—
—
RESV
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0 0 0 0 0XX1 B
0 0 0 0 0XX1 B
0 0 0 0 0XX1 B
0 0 0 0 0XX1 B
• PWM0 to 3 re-load register (PRLL, PRLH)
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PRLH0 : 000037H
PRLH1 : 00003BH
PRLH2 : 00003FH
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PRLH3 : 00002FH
PRLL0 : 000036H
PRLL1 : 00003AH
PRLL2 : 00003EH
PRLL3 : 00002EH
R/W : Readable and writable
— : Unused
X : Indeterminate
RESV: Reserved bit
34
Initial value
XXXXXXX1 B
XXXXXXX1 B
XXXXXXX1 B
XXXXXXX1 B
XXXXXXX1 B
XXXXXXX1 B
XXXXXXX1 B
XXXXXXX1 B
MB90246A Series
(2) Block Diagram
Timerbase timer output (22/HCLK)
Timerbase timer output (211/HCLK)
Pin
Count clock
selector
PWM
output latch
Output enable
P85/PWM0
P86/PWM1
P87/PWM2
P93/INT3/PWM3
Reverse
Clear
Interrupt request
Down counter clear
#28(1CH)
#30(1EH)
#32(20H)
#34(22H)
Re-load
Re-load register
L/H selector
PWM re-load register
(PRLL)
Temporary buffer
PWM re-load register
(PRLH)
PEN PCKS POE PIE PUF
—
— RESV
PWM operationg mode
control register
(PWMC)
Internal data bus
HCLK : Oscillation clock
35
MB90246A Series
5. 16-bit Re-load Timer
The 16-bit re-load timer has an internal clock mode for counting down in synchronization to three types of internal
clocks and an event count mode for counting down detecting a given edge of the pulse input to the external bus
pin, and either of the two functions can be selectively used.
For this timer, an “underflow” is defined as the timing of transition from the counter value of “0000H” to “FFFFH”.
According to this definition, an underflow occurs after [re-load register setting value + 1] counts.
In operating the counter, the re-load mode for repeating counting operation after re-loading a counter value after
an underflow or the one-shot mode for stopping the counting operation after an underflow can be selectively used.
Because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent
I/O service (EI2OS).
The MB90246A series has 3 channels of 16-bit re-load timers.
(1) Register Configuration
• Timer control status register 0, 1, 2 upper digits (TMCSR0, TMCSR1, TMCSR2: H)
Address
TMCSR0 : 000041H
TMCSR1 : 000049H
TMCSR2 : 000051H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
—
—
—
—
CSL1
CSL0 MOD2 MOD1
—
—
—
—
R/W
R/W
R/W
bit 7 . . . . . . . . . . . . . bit 0
Initial value
(TMCSR : L)
- - - - 0000 B
R/W
• Timer control status register 0, 1, 2 lower digits (TMCSR0, TMCSR1, TMCSR2: L)
Address
TMCSR0 : 000040H
TMCSR1 : 000048H
TMCSR2 : 000050H
bit 15. . . . . . . . . . . . .bit 8 bit 7
bit 6
bit 5
bit 4
MOD0 OUTE OUTL RELD
(TMCSR : H)
R/W
R/W
R/W
R/W
bit 3
bit 2
bit 1
bit 0
Initial value
INTE
UF
CNTE
TRG
00000000 B
R/W
R/W
R/W
R/W
• 16-bit timer register 0, 1 (TMR0, TMR1, TMR2)
Address
TMR0 : 000042H
TMR1 : 00004AH
TMR2 : 000052H
bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
D15 D14 D13 D12 D11 D10 D9
R
R
R
R
R
R
R
D8
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
R
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
• 16-bit re-load register 0, 1 (TMRL0,TMRL1)
Address
TMRLR0 : 000044H
TMRLR1 : 00004CH
TMRLR2 : 000054H
bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
D15 D14 D13 D12 D11 D10 D9
W
W
W
R/W : Readable and writable
R : Read only
W : Write only
— : Unused
X : Indeterminate
36
W
W
W
W
D8
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
W
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
MB90246A Series
(2) Block Diagram
Internal data bus
TMRLR0*1
<TMRLR1>
<<TMRLR2>>
16-bit re-load register
Re-load signal
TMR0*1
<TMR1>
<<TMR2>>
Re-load
control circuit
16-bit timer register (down counter) UF
CLK
Count clock generation circuit
φ
Prescaler
3
Gate input
Valid clock
decision
circuit
Clear
Input
control
circuit
Output control circuit
Clock
selecter
External
clock
P74/TIN0/TOT0 3
<P75/TIN1/TOT1>
<<P76/TIN2/TOT2>>
2
—
—
Output
generation circuit
Revers
Pin
EN
P74/TIN0/TOT0
<P75/TIN1/TOT1>
<<P76/TIN2/TOT2>>
Select
signal
Function select
—
To UART (ch.1)*1
To 8/10-bit A/D converter
(ch. 2)
CLK
Internal
clock
Pin
Wait signal
Operation
control circuit
— CSL1CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
Timer control status register (TMCSR0)*1
<TMCSR1>
<<TMCSR2>>
Interrupt request signal
#27 (1BH)
<#29 (1DH)>*2
<<#31 (1FH)>>
*1: The timer has ch.0, ch.1 and ch.2, and listed in the parenthesis <> are for ch.1 and << >> for ch.2.
*2: Interrupt number
φ : Machine clock frequency
37
MB90246A Series
6. 16-bit I/O Timer
The 16-bit I/O timer module consists of one 16-bit free-run timer, two input capture (ICU) circuits, and four output
comparators.
This complex module allows two independent waveforms to be output on the basis of the 16-bit free-run timer.
Input pulse width and external clock periods can, therfore, be measured.
The 16-bit I/O timer consists of:
• a 16-bit free-run timer; and
• two input captures (ICU).
• Block diagram
Internal data bus
16-bit
free-run timer
38
Dedicated bus
Input capture
(ICU)
MB90246A Series
(1) 16-bit Free-run Timer
The 16-bit free-run timer consists of a 16-bit up counter, a prescaler, and a control register. The value output
from the timer counter is used as basic timer (base timer) for input capture (ICU).
•
•
•
•
A counter operation clock can be selected from four internal clocks.
An interrupt request can be issued to the CPU by counter overflow.
The extended intelligent I/O service (EI2OS) can be activated.
The 16-bit free-run timer counter is cleared to “0000H” by a reset or by clearing the timer (TCCS: CLK = 0).
• Register configuration
• Timer control status register (TCCS)
Address
bit 15. . . . . . . . . . . . .bit 8 bit 7
00006EH
(Vacancy)
bit 6
bit 5
bit 4
RESV
IVF
IVFE
STOP RESV
R/W
R/W
R/W
R/W
bit 3
R/W
bit 2
bit 1
bit 0
Initial value
CLR
CLK1
CLK0
00000000 B
R/W
R/W
R/W
• Timer data register (TCDT)
Address
00006DH
00006CH
bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Initial value
T15 T14 T13 T12 T11 T10 T09 T08 T07 T06 T05 T04 T03 T02 T01 T00
00000000 B
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable and writable
RESV : Reserved bit
• Block diagram
Count value output
to input capture
(ICU)
Timer data register (TCDT)
OF
16-bit free-run timer
φ
STOP
CLR
Internal data bus
CLK
Prescaler
2
Timer control
status register
(TCCS)
RESV
IVF
IVFE STOP RESV CLR
CLK1 CLK0
Free-run timer
interrupt request
#23 (17H)*
φ : Machine clock frequency
OF : Overflow
* : Interrupt number
39
MB90246A Series
(2) Input Capture (ICU)
The input capture (ICU) consists of a capture register corresponding to two 16-bit external input pins, a control
register, and an edge detector. Upon input of a trigger edge through an external input pin, the counter value of
the 16-bit free-run timer is stored into the input capture register, and an interrupt request can be generated
concurrently.
•
•
•
•
A capture interrupt can be generated independently for each capture unit.
The extended intelligent I/O service (EI2OS) can be activated.
A trigger edge direction can be selected from rising/falling/both edges.
Since two input capture units can be operated independent of each other, up to two events can be measured
independently.
• The input capture function is suited for measurements of intervals (frequencies) and pulse-widths.
• Register configuration
• Input capture control status register (ICS)
Address
ICS0 : 000064H
bit 15. . . . . . . . . . . . .bit 8
(Vacancy)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Input capture register (IPCP0, IPCP1)
Address bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
IPCP0 : 000061H CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00
IPCP1 : 000063H
IPCP0 : 000060H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
IPCP1 : 000062H
Initial value
XXXXXXXXB
XXXXXXXXB
R/W : Readable and writable
R : Read only
X : Indeterminate
• Block diagram
16-bit free-run timer
Edge detection circuit
P71/ASR1
Pin
Internal data bus
Input capture register 1 (IPCP1)
P70/ASR0
Pin
Input capture register 0 (IPCP0)
Input capture
control status
register(ICS)
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
#17 (11H)
#15 (OFH)
*: Interrupt number
40
Input capture
interrupt request
(ICU)
MB90246A Series
7. Simple I/O Serial Interface
The 8/16-bit simple I/O serial interface transfers data synchronously with a clock.
• Communications direction: Concurrent processing of transmission (Whether data is to be sent or received
must be judged by the user.)
• Transfer mode: Clock synchronization function (Only data are transferred.)
• Transfer rate:DC to φ/2 (φ: Machine clock. Frequencies of up to 8 MHz are available when the machine clock
is rated at 16 MHz.)
• Shift clock: A machine clock division clock is used as the shift clock. (One of four division ratios can be
selected.). A shift clock is output only during data transfer.
• Data transfer format: MSB first can be selected. 8 or 16 bits can be selected as data length. Only data are
transferred.
• Interrupt request: An interrupt request is issued upon termination of transfer.
• Inter-CPU connection: Only 1:1 (bidirectional communication)
(1) Register Configuration
• Serial control status register 1, 2 (SCR)
Address
bit 15. . . . . . . . . . . . .bit 8
SCR0 : 000020H
SCR1 : 000024H
(SSR)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
STOP OCKE
SOE
SIE
SIR
WBS
R/W
R/W
R/W
R/W
R/W
R/W
bit 1
bit 0
SMD1 SMD0
R/W
Initial value
10000000 B
R/W
• Serial status register 1, 2 (SSR)
Address
SSR1 : 000021H
SSR2 : 000025H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
Initial value
—
—
—
—
—
—
—
BUSY
(SCR)
- - - - - - - 1B
—
—
—
—
—
—
—
R
• Serial data register 1, 2 (SDR)
Address bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SDR1H : 000023H D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
SDR2H : 000027H
SDR1L : 000022H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
SDR2L : 000026H
Initial value
XXXXXXXXB
XXXXXXXXB
R/W : Readable and writable
R : Read only
— : Unused
X : Indeterminate
41
MB90246A Series
(2) Block Diagram
Serial data register (SDR)
SDRH
Pin
SDRL
PA0/SID1
PA3/SID2
Pin
Internal data bus
PA1/SOD1
PA4/SOD2
Pin
Control circuit
PA2/SCK1
PA5/SCK2
Shift clock counter
2
STOP OCKE SOE
SIE
SIR WBS SMD1 SMD0
Serial control
status register (SCR)
—
—
—
—
Serial status register (SSR)
φ
*
42
: Machine clock frequency
: Interrupt number
—
—
— BUSY
Serial I/O
interrupt request
#35 (23H)*
#18 (12H)*
MB90246A Series
8. UART
UART0 is a general-purpose serial data communication interface for performing synchronous or asynchronous
communication (start-stop synchronization system). In addition to the normal duplex communication function
(normal mode), UART0 has a master-slave type communication function (multi-processor mode).
• Data buffer: Full-duplex double buffer
• Transfer mode:Clock synchronized (with start and stop bit)
Clock asynchronized (start-stop synchronization system)
• Baud rate: With dedicated baud rate generator, selectable from 12 types
External clock input possible
Internal clock (A clock supplied from 16-bit re-load timer 2 can be used.)
• Data length: 7 bit to 9 bit selective (with a parity bit)
6 bit to 8 bit selective (without a parity bit)
• Signal format: NRZ (Non Return to Zero) system
• Reception error detection: Framing error
Overrun error
Parity error (not available in multi-processor mode)
• Interrupt request: Receive interrupt (receive complete, receive error detection)
Receive interrupt (transmit complete)
Transmit/receive conforms to extended intelligent I/O service (EI2OS)
• Master/slave type communication function: 1 (master) to n (slave) communication possible
(multi-processor mode)
(1) Register Configuration
• Status register (USR)
Address
bit 15
bit 14
000029H
RDRF OREF
bit 12
PE
TDRE
RIE
BCH0
RBF
TBF
R
R
R/W
R/W
R
R
Address
bit 15. . . . . . . . . . . . bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
000028H
(USR)
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
00000100B
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R
R
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . . bit 0
bit 13
(UMC)
Initial value
00010000B
• Mode control register (UMC)
• Rate and data register (URD)
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . . bit 0
Address
bit 15
bit 14
bit 13
bit 12
bit 11
00002BH
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(UIDR/UODR)
Initial value
00000000B
• Input data register (UIDR)
Address
00002AH
bit 15 . . . . . bit 9 bit 8
(URD)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D8
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
R
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
D8
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
W
Initial value
XXXXXXXXB
• Output data register (UODR)
Address
00002AH
bit 15 . . . . . bit 9 bit 8
(URD)
bit 0
Initial value
XXXXXXXXB
R/W : Readable and writable
R : Read only
W : Write only
X : Indeterminate
43
MB90246A Series
(2) Block Diagram
Control bus
Dedicated baud
rate generator
Transmit
clock
Clock
selector
16-bit re-load
timer 2
Receive
interrupt signal
#39 (27H)*
Transmit
interrupt signal
#37 (25H)*
Receive
clock
Pin
P96/SCK0
Transmit
control circuit
Receive
control circuit
Start bit
detection circuit
Transmit start
circuit
Receive bit
counter
Transmit bit
counter
Receive parity
counter
Transmit parity
counter
Pin
P95/SOD0
Shift register for
transmission
Shift register for
reception
Pin
P94/SID0
Reception
complete
UIDR
Start transmission
UODR
Receive condition
decision circuit
To EI2OS reception
error generation
signal (to CPU)
Internal data bus
UMC
register
* : Interrupt number
44
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
USR
register
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
URD
register
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
MB90246A Series
9. DTP/External Interrupt Circuit
The DTP (Data Transfer Peripheral)/external interrupt circuit is located between peripheral equipment connected
externally and the F2MC-16F CPU and transmit interrupt requests or data transfer requests generated by
peripheral equipment to the CPU, generates external interrupt request and starts the extended intelligent I/O
service (EI2OS).
(1) Register Configuration
• DTP/interrupt factor register (EIRR)
Address bit 15
bit 14
bit 13
000031H RESV RESV RESV
—
—
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
RESV
ER3
ER2
ER1
ER0
—
R/W
R/W
R/W
R/W
—
(ENIR)
Initial value
- - - - 0000 B
• DTP/interrupt enable register (ENIR)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
000030H
RESV RESV RESV
(EIRR)
RESV
—
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EN3
EN2
EN1
EN0
—
—
—
R/W
R/W
R/W
R/W
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000032H
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
- - - - 0000 B
• Request level setting register (ELVR)
(Vacancy)
Initial value
00000000 B
R/W: Readable and writable
— : Unused
RESV : Reserved bit
45
MB90246A Series
(2) Block Diagram
Request level setting register (ELVR)
LB3
LA3
LB2
2
LA2
LB1
LA1
LB0
LA0
2
2
Pin
P93/INT3/
PWM3
2
Level edge
selector 3
Level edge
selector 1
Level edge
selector 2
Level edge
selector 0
Pin
Internal data bus
P92/INT2/ATG
DTP/external interrupt input
detection circuit
Pin
P91/INT1
Pin
P90/INT0
DTP/interrupt factor register
(EIRR)
RESV RESV RESV RESV ER3
ER2
ER1
ER0
Interrupt request signal
#21 (15H)*
#19 (13H)*
#13 (0DH)*
DTP/interrupt enable register
(ENIR)
RESV RESV RESV RESV EN3
*: Interrupt signal
46
#11 (0BH)*
EN2
EN1
EN0
MB90246A Series
10. Delayed Interrupt Generation Module
The delayed interrupt generation module generates interrupts for switching tasks for development on a realtime operating system (REALOS series). The module can be used to generate softwarewise generates hardware
interrupt requests to the CPU and cancel the interrupts.
This module does not conform to the extended intelligent I/O service (EI2OS).
(1) Register Configuration
• Delayed interrupt factor generation/cancellation register (DIRR)
bit 8 bit 7 . . . . . . . . . . . . bit 0
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
00009FH
—
—
—
—
—
—
—
R0
—
—
—
—
—
—
—
R/W
(System reservation area)
Initial value
- - - - - - -0B
R/W: Readable and writable
— : Unused
(2) Block Diagram
Internal data bus
—
—
—
—
—
Delayed interrupt factor generation/
cancellation register (DIRR)
—
—
R0
S factor
R latch
Interrupt request signal
#42 (2AH)*
*: Interrupt signal
47
MB90246A Series
11. 8/10-bit A/D Converter
The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input
voltage) to digital values (A/D conversion) and has the following features.
• Minimum conversion time: 6.13 µs (at machine clock of 16 MHz, including sampling time)
• Minimum sampling time: 3.75 µs (at machine clock of 16 MHz)
• Conversion time: The sampling time can be set arbitrarily.
Serial to parallel converter with a sample hold circuit
• Conversion method
• Resolution: 10-bit or 8-bit selective
• Analog input pins: Selectable from eight channels by software
Single conversion mode: Single conversion for the specified channel
Scan conversion mode: Scan conversions for maximum of four channel
• Interrupt requests can be generated and the extended intelligent I/O service (EI2OS) can be started after the
end of A/D conversion.
• Starting factors for conversion: Selected from software activation, 16-bit re-load timer 1 output (rising edge),
and external trigger (falling edge).
• A data buffer that covers four channels is supported. The results of conversion are stored into the data buffer.
48
MB90246A Series
(1) Register Configuration
• A/D control status register upper digits (ADCSH)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
000071H
—
ACS2
ACS1
ACS0
—
—
—
R/W
R/W
R/W
—
—
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
CREG SCAN
R/W
(ADCSL)
Initial value
- 000 - - 00 B
R/W
• A/D control status register lower digits (ADCSL)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
000070H
(ADCSH)
bit 6
bit 5
bit 4
bit 3
bit 2
BUSY
INT
INTE
—
STS1
STS0
R/W
R/W
R/W
—
R/W
R/W
bit 1
bit 0
STAR RESV
R/W
Initial value
000 - 0000 B
R/W
• A/D data register 0 to 3 (ADTH, ADTL)
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
ADTH0 : 000075H
— — —
— —
— D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADTH1 : 000077H
ADTH2 : 000079H
R
R
R
R
R
R
R
R
R
R
R
R
R
R
*
*
ADTH3 : 00007BH
ADTL0 : 000074H
ADTL1 : 000076H
ADTL2 : 000078H
ADTL3 : 00007AH
Initial value
- - - - - - **B
XXXXXXXX B
• Conversion time setting register (ADCT)
Address
000073H
000072H
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SMP3 SMP2 SMP1 SMP0 CV03 CV02 CV01 CV00 CV13 CV12 CV11 CV10 CV23 CV22 CV21 CV20
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
XXXXXXXX B
XXXXXXXX B
• Analog input enable register (ADER)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
000016H
ADE6 ADE5
(DDR7)
ADE7
R/W
R/W
bit 5
R/W
bit 4
bit 3
bit 2
bit 1
bit 0
ADE4
ADE3
ADE2
ADE1
ADE0
R/W
R/W
R/W
R/W
R/W
Initial value
11111111 B
R/W: Readable and writable
R : Read only
— : Unused
X : Indeterminate
* : The CREG bit value of ADCSH makes different storage styles.
RESV : Reserved bit
49
MB90246A Series
(2) Block Diagram
Conversion time setting register (ADCT)
4
4
4
A/D data register 0 to 3
ADTH0 to ADTH3, ADTL0 to ADTL3
Internal data bus
4
Register selection
SMP3 SMP2 SMP1 SMP0 CV03 CV02 CV01 CV00 CV13 CV12 CV11 CV10 CV23 CV22 CV21 CV20
AVRH
AVRL
AVCC
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
Sample
hold
circuit
Analog
channel
selector
A/D converter
φ
TO
P92/INT2/ATG
Control circuit
Clock
selector
2
3
—
ACS2 ACS1 ACS0
—
—
CREG SCAN BUSY
INT
INTE
—
STS1 STS0 STAR RESV
A/D control status register (ADCS)
φ : Machine clock frequency
TO : 16-bit re-load timer channel 1 output
50
Interrupt request #33 (21H)
MB90246A Series
12. 8-bit D/A Converter
The 8-bit D/A converter, which is based on the R-2R system, supports 8-bit resolution mode. It contains two
channels each of which can be controlled in terms of output by the D/A control register.
(1) Register Configuration
• D/A control register 0 (DACR0)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
00005BH
—
—
—
—
—
—
—
DAE0
(DADR0)
—
—
—
—
—
—
—
R/W
Initial value
- - - - - - -0B
• D/A control register 1 (DACR1)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
00005DH
—
—
—
—
—
—
—
DAE1
(DADR1)
—
—
—
—
—
—
—
R/W
Initial value
- - - - - - -0B
• D/A control register 2 (DACR2)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
00005FH
—
—
—
—
—
—
—
DAE2
(DADR2)
—
—
—
—
—
—
—
R/W
Initial value
- - - - - - -0B
• D/A data register 0 (DADR0)
Address
00005AH
bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DA07
DA06
DA05
DA04
DA03
DA02
DA01
DA00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DA17
DA16
DA15
DA14
DA13
DA12
DA11
DA10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DA27
DA26
DA25
DA24
DA23
DA22
DA21
DA20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(DACR0)
Initial value
XXXXXXXX B
• D/A data register 1 (DADR1)
Address
00005CH
(DACR1)
Initial value
XXXXXXXX B
• D/A data register 2 (DADR2)
Address
00005EH
(DACR2)
Initial value
XXXXXXXX B
R/W : Readable and writable
— : Unused
X : Indeterminate
51
MB90246A Series
(2) Block Diagram
Internal data bus
D/A data register (DADR0)
<DADR1> <DADR2>
DA×7 DA×6 DA×5 DA×4 DA×3 DA×2 DA×1 DA×0
D/A converter
DVRH
DA×7
Pin
2R
DA×6
2R
DA×5
2R
DA×4
2R
DA×3
2R
DA×2
2R
DA×1
2R
DA×0
2R
R
P82/DAO0
<P83/DAO1>
<P84/DAO2>
R
R
R
R
R
R
R
DVRL
Standby control
D/A control register (DACR0)
<DACR1> <DACR2>
—
—
—
—
—
—
—
DAE
Internal data bus
Note: The 8-bit D/A converter supports channels 0 to 2. A value enclosed by < and >
is for channels 1 and 2.
52
MB90246A Series
13. DSP Interface for the IIR Filter
The DSP interface for the IIR filter is a unit which covers product addition (ΣBi × Yj + ΣAm × Xn) by hardware.
This interface allows IIR filter calculation to be performed readily and in a high speed.
The DSP interface for the IIR filter has the following features.
•
•
•
•
Coefficients A and B, and variables X and Y have 16-bit length, and four banks are supported.
(1 to 4) + (1 to 4) product terms can be selected.
Data can be rounded and clipped in units of 10 or 12 bits.
With two or more concatenated banks used, the results of an operation can be transferred to the subsequent
bank register.
• Operation time: ((M + N + 1) × B + 1)/φ µs(M, N = number of product terms, B = number of banks, φ: machine
clock)
(1) Register Configuration
• Product addition control status register upper digits (MCSR:H)
Address
bit 15
bit 14
bit 13
000081H
—
WEY
WENY WENX
—
R/W
bit 12
R/W
R/W
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
N1
N0
M1
M0
(MCSR:L)
R/W
R/W
R/W
R/W
Initial value
- XXXXXXX B
• Product addition control status register lower digits (MCSR:L)
Address
bit 15 . . . . . . . . . . . . bit 8 bit 7
000080H
(MCSR:H)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RND
CLP
DIV
BF
BNK1
BNK0
TRG
MAE
R/W
R/W
R/W
R
R/W
R/W
W
R/W
Initial value
XXX0XXX0 B
• Product addition control register upper digits (MCCR:H)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . . bit 0
000083H
—
—
—
—
—
—
RESV
RESV
(MCCR:L)
—
—
—
—
—
—
R/W
R/W
Initial value
- - - - - - 00 B
• Product addition control register lower digits (MCCR:L)
Address
bit 15 . . . . . . . . . . . . bit 8 bit 7
000082H
(MCCR:H)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OVF
CNTD CNTC CNTB CDRD CDRC CDRB CDRA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000 B
R/W
• Product addition output register (MDORL, M, H)
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
MDORH : 000088H
S
S
S
S
S
R
R
R
R
R
D34 D33 D32
R
R
Initial value
XXXXXXXX B
R
MDORM : 000086H D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 XXXXXXXX XXXXXXXX B
R
R
R
R
R
R
R
R
R
R
R
MDORL : 000084H D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
XXXXXXXX XXXXXXXX B
R/W: Readable and writable
R : Read only
W : Write only
— : Unused
X : Indeterminate
RESV : Reserved bit
53
MB90246A Series
(2) Block Diagram
Internal data bus
Transfer data
selector
Input data register
B0 to B3
Input data register
X0 to X3
Y0 to Y3
Bank
selection
A0 to A3
Coefficient register
Coefficient register
selector
Register
selection
Coefficient register
Transfer data
selector
Register selection
Input data selector
Register
selection
Bank/register
selector
Product addition unit
Product adder
3
4
Right shift and clip
OVF
CNTD CNTC CNTB CDRD CDRC CDRB CDRA
Product addition control register (MCCR)
Product addition output register L
(MDORL)
Product addition output register M
(MDORM)
Product addition
output register H
(MDORH)
2
3
—
4
WEY WENY WENX
N1
N0
M1
M0
RND
Product addition control status register (MCSR)
54
CLP
DIV
BF
BNK1 BNK0
TRG
MAE
MB90246A Series
14. Low-power Consumption (Stand-by) Mode
The F2MC-16F has the following CPU operating mode configured by selection of an clock operation control.
• Stand-by mode
The hardware stand-by mode is a mode for reducing power consumption by stopping clock supply to the CPU
by the low-power consumption control circuit, and stopping oscillation clock (stop mode, hardware standby
mode).
Gear function contributes to the low-power dissipation by providing options of divide-by-2, 4, or 16 external
clock frequencies, whichiare usually derived from non-divided frequencies.
(1) Register Configuration
• Standby control register (STBYC)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
0000A0H
STP
SLP
SPL
RST
W
W
R/W
R/W
(Vacancy)
bit 3
bit 2
OSC1 OSC0
R/W
R/W
bit 1
bit 0
CLK1
CLK0
R/W
R/W
Initial value
0 0 0 1XXXX B
R/W : Readable and writable
W : Write only
X : Indeterminate
55
MB90246A Series
(2) Block Diagram
Low-power consumption mode control register (STBYC)
STP
SLP
SPL
RST OSC1 OSC0 CLK1 CLK0
Pin
high-impedance
control circuit
RST
Pin
Cancellation of reset
RST
Standby control
circuit
2
Cancellation of interrupt
HST
Pin Hi-z control
Internal reset
generation
circuit
Internal reset
CPU clock
control circuit
CPU clock
Stop and sleep signal
Pin
Stop signal
Machine clock
Peripheral clock
control circuit
Cancellation of
oscillation
stabilization time
Clock
generation
block
Peripheral clock
Clock selector
Oscillation
stabilization
time selector
2
2
Divided
-by-2
Divided
-by-2
System clock
generation
circuit
X0
Pin
X0
Pin
DDC: Direct duty control
56
Main clock
DDC
Oscillation
clock
Divided
-by-4
Divided
-by-214
Divided
-by-2
Divided
-by-2
Divided
-by-2
Timebase timer
MB90246A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
VSS – 0.3
VSS + 7.0
V
AVCC
VSS – 0.3
VSS + 7.0
V
*1
AVRH,
AVRL
VSS – 0.3
VSS + 7.0
V
*1
DVRH,
DVRL
VSS – 0.3
VSS + 7.0
V
*1
Input voltage
VI
VSS – 0.3
VCC + 0.3
V
*2
Output voltage
VO
VSS – 0.3
VCC + 0.3
V
*2
“L” level maximum output current
IOL

10
mA
*3
“L” level average output current
IOLAV

4
mA
*4
“L” level total average output current
ΣIOLAV

50
mA
*5
“H” level maximum output current
IOH

–10
mA
*3
“H” level average output current
IOHAV

–4
mA
*4
“H” level total average output current
ΣIOHAV

–48
mA
*5
Power consumption
PD

600
mW
Operating temperature
TA
–30
+70
°C
Storage temperature
Tstg
–55
+150
°C
Power supply voltage
*1: AVCC, AVRH, AVRL, DVRH and DVRL shall never exceed VCC.
DVRL shall never exceed DVRH. AVRL shall never exceed AVRH.
*2: VI and VO shall never exceed VCC + 0.3 V.
*3: The maximum output current is a peak value for a corresponding pin.
*4: Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*5: Total average current is an average current value observed for a 100 ms period for all corresponding pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
57
MB90246A Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Power supply voltage
Operating temperature
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
4.5
5.5
V
Normal operation
VCC
2.0
5.5
V
Retains RAM data at the time of
operation stop
TA
–30
+70
°C
External bus mode
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
58
MB90246A Series
3. DC Characteristics
Parameter Symbol
Pin name
VIH
CMOS input pin
VIH2
TTL input pin
VIH1S
Hysteresis input
pin
VIHM
MD0 to MD2
VIL1
CMOS input pin
VIL2
TTL input pin
VIL1S
Hysteresis input
pin
VILM
“H” level
output
voltage
“L” level
output
voltage
“H” level
input
voltage
“L” level
input
voltage
—
0.7 VCC
—
VCC + 0.3
V
VCC = 5.0 V ±10%
2.2
—
VCC + 0.3
V
0.8 VCC
—
VCC + 0.3
V
VCC – 0.3
—
VCC + 0.3
V
VCC – 0.3
—
0.3 VCC
V
VCC – 0.3
—
0.8
V
VCC – 0.3
—
0.2 VCC
V
MD0 to MD2
VCC – 0.3
—
VCC + 0.3
V
VOH
All ports other
VCC = 4.5 V
than P60 to P67 IOH = –4.0 mA
VCC – 0.5
—
—
V
VOL
All output pins
—
—
0.4
V
—
0.1
10
µA
Open-drain
output
ILEAK
leakage
current
“H” level
input
current
“L” level
input
current
Pull-up
resistance
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Condition
Unit Remarks
Min.
Typ.
Max.
P60 to P67
—
VCC = 5.0 V ±10%
—
VCC = 4.5 V
IOL = 4.0 mA
—
IIH1
CMOS input
pins other than
RST
VCC = 5.5 V
VIH = 0.7 VCC
—
—
–10
µA
IIH2
TTL input pin
VCC = 5.5 V
VIH = 2.2 VCC
—
—
–10
µA
IIH3
Hysteresis input VCC = 5.5 V
pin
VIH = 0.8 VCC
—
—
–10
µA
IIL1
CMOS input
pins other than
RST
VCC = 5.5 V
VIL = 0.3 VCC
—
—
10
µA
IIL2
TTL input pin
VCC = 5.5 V
VIL = 0.8 V
—
—
10
µA
IIL3
Hysteresis input VCC = 5.5 V
pin
VIL = 0.2 VCC
—
—
10
µA
R
RST
22
—
110
kΩ
—
(Continued)
59
MB90246A Series
(Continued)
Parameter Symbol
ICC
Power
supply
current
ICCS
ICCH
Input
CIN
capacitance
60
Pin name
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Condition
Unit Remarks
Min.
Typ.
Max.
Internal operation
at 16 MHz
VCC = 5.0 V ±10%
Normal operation
—
80
100
mA
—
Internal operation
at 16 MHz
VCC = 5.0 V ±10%
In sleep mode
—
30
50
mA
—
TA = +25°C
VCC = 4.5 V to 5.5 V
In stop mode and
hardware standby
mode
—
0.1
10
µA
Other than AVCC,
AVSS, VCC, VSS
—
—
10
—
pF
VCC
MB90246A Series
4. AC Characteristics
(1) Reset, Hardware Standby Input Timing
Parameter
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Symbol Pin name Condition
Unit
Remarks
Min.
Max.
tRSTL
RST
Hardware standby input time tHSTL
HST
Reset input time
—
5 tCYC*
—
ns
5 tCYC*
—
ns
* : For tCYC (cycle time (machine cycle)), see paragraph (4), "Clock output timing."
Note: Upon hardware standby input, divide-by-32 is selected as the machine cycle.
tRSTL, tHSTL
RST
HST
0.2 VCC
0.2 VCC
• Measurement conditions for AC ratings
Pin
CL
CL is a load capacitance connected to a pin under test.
Capacitors of CL = 30 pF should be connected to CLK pin, while CL of 80 pF is connected
to address bus (A23 to A00) and data bus (D15 to D00), RD, WRH and WRL pins.
61
MB90246A Series
(2) Specification for Power-on Reset
Parameter
Symbol Pin name Condition
Power supply rising time
tR
VCC
Power supply cut-off time
tOFF
VCC
—
(AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Unit
Remarks
Min.
Max.
—
30
ms *
Due to repeated
1
—
ms
operations
* : VCC must be kept lower than 0.2 V before power-on.
Notes: • The above ratings are values for causing a power-on reset.
• When HST is set to “L”, apply power according to this table to cause a power-on reset irrespective of
whether or not a power-on reset is required.
• For built-in resources in the device, re-apply power to the resources to cause a power-on reset.
tR
VCC
4.5 V
0.2 V
0.2 V
0.2 V
tOFF
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to raise the voltage
smoothly to suppress fluctuations as shown below.
Main power
supply voltage
VCC
It is recommended to keep the rising
speed of the supply voltage at 50 mV/ms.
Sub power supply voltage
VSS
62
RAM data retained
MB90246A Series
(3) Clock Timings
• Operation at 5.0 V ±10%
Parameter
Symbol Pin name
Clock frequency
Clock cycle time
FC
tC
X0, X1
X0, X1
Input clock pulse
width
PWH,
PWL
X0
Input clock rising/
falling time
tCR,
tCF
X0
Condition
VCC = 5.0 V ±10%
—
VCC = 5.0 V ±10%
(AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Unit
Remarks
Min. Typ. Max.
16
—
32
MHz
1/Fc
—
—
ns
Recommended
10
—
—
ns duty ratio of
30% to 70%
Maximum value
—
—
11
ns
= tCR + tCF
• Clock timings
tC
0.7 VCC
0.7 VCC
0.7 VCC
0.3 VCC
PWH
0.3 VCC
PWL
tCF
tCR
• Relationship between clock frequency and power supply voltage
Power supply voltage VCC
(V)
5.5
Normal operation range
(TA = –30°C to +70°C)
4.5
0
16
32
(MHz)
Clock frequency FC
63
MB90246A Series
(4) Clock Output Timing
Parameter
Cycle time
(machine cycle)
CLK ↑ → CLK ↓
Symbol
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Pin name
Condition
Unit Remarks
Min.
Max.
tCYC
CLK
tCHCL
CLK
—
2 tC*1
32tC*1*2
VCC = 5.0 V ±10% 1 tCYC/2 – 20 1 tCYC/2 + 20
ns
ns
*1: For tC (clock cycle time), refer to “(3) Clock Timings.”
*2: This case is applied when the lowest speed (1/16) is selected by the clock gear function with the clock frequency
(FC) set at 16 MHz.
tCYC
tCHCL
2.4 V
CLK
64
2.4 V
0.8 V
MB90246A Series
(3) Bus Read Timing
Parameter
Symbol
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit Remarks
Pin name
Condition
Min.
Max.
Effective address →
RD ↓ time
tAVRL
Effective address →
effective data input
tAVDV
D15 to D00
RD pulse width
tRLRH
RD
A00 to A23
1 tCYC*/2 – 20
—
ns
—
(N + 1.5) ×
1 tCYC* – 40
ns
—
(N + 1) ×
1 tCYC* – 25
—
ns
VCC = 5.0 V ±10%
—
(N + 1) ×
1 tCYC** – 30
ns
0
—
ns
1 tCYC*/2 – 20
—
ns
1 tCYC*/2 – 25
—
ns
1 tCYC*/2 – 25
—
ns
VCC = 5.0 V ±10%
RD ↓ → effective data
tRLDV
input
D15 to D00
RD ↑ → data hold time tRHDX
D15 to D00
RD ↑ → address
effective time
tRHAX
A00 to A23
Effective address →
CLK ↑ time
tAVCH
CLK,
A00 to A23
RD ↓ → CLK ↑ time
tRLCL
RD, CLK
—
N: Stands for the number of wait cycles. With no wait, N is set at “0”. (The number of wait cycles depends on an
automatic wait and external RDY.)
* : For tCYC (cycle time (machine cycle)), see paragraph (4), “Clock output timing.”
tAVCH
CLK
0.8 V
tRLCL
2.4 V
tAVRL
0.8 V
tRLRH
RD
2.4 V
0.8 V
tRHAX
A00 to A23
2.4 V
0.8 V
2.4 V
0.8 V
tRLDV
tRHDX
tAVDV
D00 to D15
2.2 V
0.8 V
2.2 V
0.8 V
65
MB90246A Series
(4) Bus Write Timing
Parameter
Effective address →
WRL, WRH ↓ time
Symbol
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Unit Remarks
Pin name
Condition
Min.
Max.
1 tCYC*/
2 – 20
—
ns
WRL, WRH
(N + 1) ×
1 tCYC** – 25
—
ns
tDVWH
D15 to D00
(N + 1) ×
1 tCYC* – 40
—
ns
WRL, WRH ↑ → data
hold time
tWHDX
D15 to D00
1 tCYC*/
2 – 20
—
ns
WRL, WRH ↑ →
address effective time
tWHAX
A00 to A23
1 tCYC*/
2 – 20
—
ns
WRL, WRH ↓ → CLK ↓
tWLCL
time
WRL, CLK
1 tCYC*/
2 – 25
—
ns
tAVWL
A00 to A23
WRL, WRH pulse width tWLWH
Write data → WRL,
WRH ↑ time
VCC = 5.0 V ±10%
VCC = 5.0 V ±10%
—
N: Stands for the number of wait cycles. With no wait, N is set at “0”. (The number of wait cycles depends on an
automatic wait and external RDY.)
* : For tCYC (cycle time (machine cycle)), see paragraph (4), “Clock output timing.”
tWLCL
0.8 V
CLK
tAVWL
tWLWH
2.4 V
WRL, WRH
0.8 V
tWHAX
A00 to A23
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
D00 to D15
2.4 V
0.2 V
66
tWHDX
2.4 V
Write data
0.2 V
MB90246A Series
(5) Ready Input Timing
• CLK signal standards
Parameter
Symbol
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Pin name
Condition
Unit Remarks
Min.
Max.
RD/WRH/WRL ↓ →
RDY ↓ time
tRYHS
RD/WRH/
WRL,
RDY
RDY setup time
(in diallocating)
tRHDV
RDY
RDY hold time
tRYHH
RDY
0
N ×1 tCYC*
+ 15
ns
VCC = 5.0 V ±10%
30
—
ns
—
0
—
ns
N: Stands for the number of wait cycles. With no wait, N is set at “0”. (The number of wait cycles depends on an
automatic wait and external RDY.)
* : For tCYC (cycle time (machine cycle)), see paragraph (4), “Clock output timing.”
Note: Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient.
• Ready input timing (CLK signal standards)
CLK
A00 to A23
RD/WRH/WRL
0.8 V
tRYHH
tRYH
RDY
(wait not inserted)
2.2 V
2.2 V
RDY
(wait inserted)
2.2 V
0.8 V
2.2 V
0.8 V
tRHDV
tRYHH
67
MB90246A Series
• RD/WRH/WRL signal standards
Parameter
Symbol
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Pin name
Condition
Unit Remarks
Min.
Max.
RD/WRH/WRL ↓ →
RDY ↓ time
tRYHS
RD/WRH/
WRL,
RDY
RDY pulse width
tRYPW
RDY
RDY ↑ → RD ↑
tRHDV
RD/WRH/
WRL,
RDY
—
0
N ×1 tCYC*3
+ 15*1
ns
VCC = 5.0 V ±10%
1/2 tCYC*3
+ 20
(m + 1) × 1
tCYC*2,*3
ns
—
1 tCYC*3
– 15
2 tCYC*3
– 25
ns
N: Stands for the number of wait cycles. With no wait, N is set at “0”. (The number of wait cycles depends on an
automatic wait and external RDY.)
m: Stands for the number of RDY wait cycles. With no wait, m is set at “0”.
*1: Use the automatic ready function when the setup time is not sufficient.
*2: If the pulse width has exceeded the maximum value, the wait period may be extended beyond the specified
number of cycles by one cycle.
*3: For tCYC (cycle time (machine cycle)), see paragraph (4), “Clock output timing.”
• Ready input timing (RD/WRH/WRL signal standards)
A00 to A23
RD/WRH/WRL
0.8 V
2.4 V
tRYHS
RDY
(wait not inserted)
tRYPW
2.2 V
2.2 V
0.8 V
0.8 V
RDY
(wait inserted)
2.2 V
tRHDV
68
MB90246A Series
(8) Hold Timing
Parameter
Symbol
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Pin name
Condition
Unit Remarks
Min.
Max.
Pins in floating status →
tXHAL
HAK ↓ time
HAK
VCC = 5.0 V ±10%
30
1 tCYC*
ns
HAK ↑ → pin valid time
HAK
—
1 tCYC*
2 tCYC*
ns
tHAHV
* : For tCYC (cycle time (machine cycle)), see paragraph (4), “Clock output timing.”
Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.
HRQ
HAK
2.4 V
0.8 V
tXHAL
tHAHV
Pins
High impedance
(9)
UART Timing
Parameter
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Symbol Pin name
Condition
Unit
Remarks
Min.
Max.
tSCYC
SCK0
SCK ↓ → SOD delay
time
tSLOV
SCK0,
SOD0
8 tCYC*
—
ns
–80
80
ns
Valid SID → SCK ↑
tIVSH
SCK0,
SID0
100
—
ns
SCK ↑ → valid SID hold
tSHIX
time
SCK0,
SID0
60
—
ns
Serial clock “H” pulse
width
tSHSL
SCK0
4 tCYC*
—
ns
Serial clock “L” pulse
width
tSLSH
SCK0
4 tCYC*
—
ns
SCK ↓ → SOD delay
time
tSLOV
SCK0,
SID0
—
150
ns
Valid SID → SCK ↑
tIVSH
—
60
—
ns
SCK ↑ → valid SID hold
tSHIX
time
SCK0,
SID0
60
—
ns
Serial clock cycle time
—
VCC = 5.0 V ±10%
Internal shift
clock mode
CL = 80 pF for
an output pin
—
VCC = 5.0 V ±10%
External shift
clock mode
CL = 80 pF for
an output pin
* : For tCYC (cycle time (machine cycle)), see paragraph (4), “Clock output timing.”
Notes: • These are AC ratings in the CLK synchronous mode.
• CL is the load capacitor value connected to pins while testing.
69
MB90246A Series
• Internal shift clock mode
tSCYC
SCK0
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SOD0
0.8 V
tIVSH
SID0
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
• External shift clock mode
tSLSH
SCK0
tSHSL
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLOV
SOD0
2.4 V
0.8 V
tIVSH
SID0
70
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
MB90246A Series
(10) Timer Input Timing
Parameter
Input pulse width
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
ASR0, ASR1,
tTIWH,
—
ns
—
4 tCYC*
tTIWL
TIN0 to TIN2
* : For tCYC (cycle time (machine cycle)), see paragraph (4), “Clock output timing.”
0.8 VCC
0.8 VCC
0.2 VCC
ASR0, ASR1
TIN0 to TIN2
tTIWH
0.2 VCC
tTIWL
(11) Timer Output Timing
Parameter
CLK ↑ → TOT
transition time
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
TOT0 to TOT2,
tTO
PWM0 to
VCC = 5.0 V ±10%
—
40
ns
PWM3
2.4 V
CLK
TOT
2.4 V
0.8 V
tTO
71
MB90246A Series
(12) I/O Simple Serial Timing
Parameter
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Pin name
Condition
Unit
Remarks
Min.
Max.
Symbol
Serial clock cycle time
tSCYC
SCK1, SCK2
2 tCYC*
—
ns
SCK ↓ → SOD delay
time
tSLOV
SCK1, SOD1,
SCK2, SOD2,
—
1 tCYC*/2
ns
Valid SID → SCK ↑
tIVSH
SCK1, SID1,
SCK2, SID2,
1 tCYC*
—
ns
SCK ↑ → valid SID hold
tSHIX
time
SCK1, SID1,
SCK2, SID2,
1 tCYC*
—
ns
—
* : For tCYC (cycle time (machine cycle)), see paragraph (4), “Clock output timing.”
Note: CL is the load capacitor value connected to pins while testing.
• Internal shift clock mode
tSCYC
2.4 V
SCK1, SCK2
0.8 V
0.8 V
tSLOV
SOD1, SOD2
2.4 V
0.8 V
tIVSH
SID1, SID2
72
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
Internal shift
clock mode
CL = 80 pF for
an output pin
MB90246A Series
(13) Trigger input timing
Parameter
Input pulse width
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Pin name
Condition
Unit
Remarks
Min.
Max.
Symbol
tTRGH,
tTRGL
ATG,
INT0 to INT3
—
5 tCYC*
—
ns
* : For tCYC (cycle time (machine cycle)), see paragraph (4), “Clock output timing.”
0.8 VCC
0.8 VCC
0.2 VCC
ATG
INT0 to INT3
tTRGH
0.2 VCC
tTRGL
73
MB90246A Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Pin name
Condition
Unit
Min.
Typ.
Max.
—
—
8, 10
10
bit
—
—
—
±3.0
LSB
—
—
—
±2.0
LSB
—
—
—
±1.9
LSB
—
Symbol
Parameter
Resolution
Total error
Linearity error
Differential linearity error
—
—
—
—
Zero transition voltage
VOT
Full-scale transition
VFST
voltage
—
Conversion time*1
Sampling
—
period
Conversion
—
period a
Conversion
—
period b
Conversion
—
period c
Analog port input current IAIN
Analog input voltage
VAIN
AN0 to AN7
AVRL
AVRL
AVRL
– 1.0 LSB + 1.0 LSB + 3.0 LSB
mV
AN0 to AN7
AVRH
AVRH
AVRH
– 4.0 LSB – 1.0 LSB + 1.0 LSB
mV
—
1.25
—
—
µs
—
560
—
—
ns
125
—
—
ns
125
—
—
ns
250
—
—
ns
—
AVRL
AVRL
+ 2.7
0.1
—
3
AVRH
µA
V
—
AVCC
V
—
—
—
AN0 to AN7
AN0 to AN7
AVRH
—
AVRL
0
—
AVCC
—
IA
IAS*2
IR
Reference voltage
supply current
IRS*2
Offset between channels
—
—
Reference voltage
Power supply current
Use the A/D data
register for setup.
VCC = 5.0 V ±10%
—
AVRH – AVRL ≥ 2.7
—
Supply current when
the CPU stops
AVCC
(AVCC = 5.5 V)
AVRH
—
Supply current when
AVRH
the CPU stops
(AVCC = 5.5 V)
AN0 to AN7
—
15
AVRH
– 2.7
20
mA
—
—
5
µA
—
0.7
2
µA
—
—
5
µA
—
—
4
LSB
V
*1: Glossary for conversion time
Conversion time
1 tCYC*
Sampling period
A/D activation
ADCS bit 1: Sets STAR
Conversion period a Conversion period b Conversion period c
2 tCYC*
End of conversion
ADCS bit 6: INT “H”
(Interrupt occurred to CPU)
* : For tCYC, see ■ Electrical Characteristics, 4, “AC Characteristics,” Cycle time (machine cycle) in
paragraph (4), “Clock output timing.”
*2: IAS and IRS signify currents when the A/D converter does not operate and when the CPU is out of service,
respectively.
74
MB90246A Series
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter
With 10 bits supported, an analog voltage can be divided into 210 parts.
Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00
0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual
conversion characteristics
Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error: The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error, linearity error, differential linearity error and
error caused by noise.
Digital output
11 1111 1111
11 1111 1110
•
•
•
•
•
•
•
•
•
•
•
(1 LSB × N + VOT)
Linearity error
00 0000 0010
00 0000 0001
00 0000 0000
VNT V(N + 1)T
VOT
1 LSB =
VFST
VFST – VOT
1022
Linearity error =
VNT – (1 LSB × N + VOT)
[LSB]
1 LSB
Differential linearity error =
V( N+1 )T – VNT
– 1 LSB [LSB]
1 LSB
75
MB90246A Series
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions.
Output impedance values of the external circuit of 300 Ω or lower are recommended.
When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor
value is recommended to minimized the effect of voltage distribution between the external capacitor and internal
capacitor.
When the output impedance of the external circuit is too high, the sampling time for analog voltages may not
be sufficient (sampling time = 0.56 µs @machine clock of 16 MHz).
• Block diagram of analog input circuit model
Analog input pin
C0
Comparator
RON1
RON2
Comparator
RON1: Approx. 300 Ω
RON2: Approx. 150 Ω
C0: Approx. 60 pF
C1: Approx. 4 pF
C1
Comparator
Note: Listed values must be considered as standards.
• Error
The smaller the | AVRH – AVRL |, the greater the error would become relatively.
8. 8-bit D/A Converter Electrical Characteristics
Parameter
Symbol
Resolution
Differential linearity error
—
—
Absolute accuracy
—
Conversion time
—
—
—
Analog power supply
voltage
Reference voltage
supply current
Analog output
impedance
76
ID
IDH
—
(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)
Value
Pin name
Condition
Unit
Min.
Typ.
Max.
—
—
8
8
bit
—
—
—
—
±0.9
LSB
VCC = DVRH = 5.0 V,
—
—
—
1.2
%
DVRL = 0.0 V
—
—
10
20
µs
Load capacitance:
20
pF
—
VCC
V
DVRH
VSS + 2.0
≥
SS
—
V
CC
–
2.0
V
DVRL
V
DVRH – DVRL 2.0 V
DVRH
During conversion
—
1.0
1.5
mA
When the CPU is
DVRH
—
—
10
µA
stopped
—
—
—
28
—
kΩ
MB90246A Series
■ EXAMPLE CHARACTERISTICS
(1) “H” Level Output Voltage
VCC – VOH
(2) “L” Level Output Voltage
VOL (V)
VOH – IOH
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
TA = +25°C
VCC = 5.0 V
0
–2
–4
–6
VOL – IOL
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–8
IOH (mA)
TA = +25°C
VCC = 5.0 V
0
2
4
6
8
IOL (mA)
(3) Power Supply Current
ICC – VCC
ICC (mA)
80
ICCS – VCC
ICCS (mA)
25
Internal operating frequency
Internal operating frequency
16 MHz
70
16 MHz
20
60
13 MHz
13 MHz
50
10 MHz
40
8 MHz
15
10 MHz
8 MHz
10
30
4 MHz
20
4 MHz
5
2 MHz
10
2 MHz
0
4.0
4.5
5.0
5.5
6.0
VCC (V)
0
4.0
4.5
5.0
5.5
6.0
VCC (V)
77
MB90246A Series
■ INSTRUCTIONS (421 INSTRUCTIONS)
Table 1
Description of Items in Instruction List
Item
Mnemonic
Description
English upper case and symbol: Described directly in assembler code.
English lower case: Converted in assembler code.
Number of letters after English lower case: Describes bit width in code.
#
Describes number of bytes.
~
Describes number of cycles.
For other letters in other items, refer to table 4.
B
Describes correction value for calculating number of actual states.
Number of actual states is calculated by adding value in the ~section.
Operation
Describes operation of instructions.
LH
Describes a special operation to 15 bits to 08 bits of the accumulator.
Z : Transfer 0.
X : Sign-extend and transfer.
– : No transmission
AH
Describes a special operation to the upper 16-bit of the accumulator.
* : Transmit from AL to AH.
– : No transfer.
Z : Transfer 00H to AH.
X : Sign-extend AL and transfer 00H or FFH to AH.
I
S
T
N
Describes status of I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero),
V (overflow), and C (carry) flags.
* : Changes after execution of instruction.
– : No changes.
S : Set after execution of instruction.
R : Reset after execution of instruction.
Z
V
C
RMW
78
Describes whether or not the instruction is a read-modify-write type (a data is read out from
memory etc. in single cycle, and the result is written into memory etc.).
* : Read-modify-write instruction
– : Not read-modify-write instruction
Note: Not used to addresses having different functions for reading and writing operations.
MB90246A Series
Table 2
Description of Symbols in Instruction Table
Item
A
Description
32-bit accumlator
The bit length is dependent on the instructions to be used.
Byte : Lower 8-bit of AL
Word :16-bit of AL
Long : AL: 32-bit of AH
AH
Upper 16-bit of A
AL
Lower 16-bit of A
SP
Stack pointer (USP or SSP)
PC
Program counter
SPCU
Stack pointer upper limited register
SPCL
Stack pointer lower limited register
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB
brg2
DTB, ADB, SSB, USB, DPR
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
addr16
addr24
ad24 0 to 15
ad24 16 to 23
io
#imm4
#imm8
#imm16
#imm32
ext (imm8)
disp8
disp16
bp
vct4
vct8
Specify shortened direct address.
Specify direct address.
Specify physical direct address.
bit0 to bit15 of addr24
bit16 to bit 23 of addr24
I/O area (000000H to 0000FFH)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data calculated by sign-extending an 8-bit immediate data
8-bit displacement
16-bit displacement
Bit offset value
Vector number (0 to 15)
Vector number (0 to 255)
(Continued)
79
MB90246A Series
(Continued)
Item
Description
( )b
Bit address
rel
ear
eam
Specify PC relative branch.
Specify effective address (code 00 to 07).
Specify effective address (code 08 to 1F).
rlst
Register allocation
Table 3
Code
00
01
02
03
04
05
06
07
Symbol
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Effective Address Field
Address type
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Number of bytes in address
extension block*
Register direct
"ea" corresponds to byte, word, and
long word from left respectively.
—
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
Register indirect
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacement
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
0
Register indirect with post increment
0
1
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
2
0
0
2
2
Note: Number of bytes for address extension corresponds to “+” in the # (number of bytes) part in the instruction
table.
80
MB90246A Series
Table 4
Number of Execution Cycles in Addressing Modes
(a)*
Code
Operand
00 to 07
Ri
RWi
RLi
Listed in instruction table
08 to 0B
@RWj
1
0C to 0F
@RWj +
4
10 to 17
@RWi + disp8
1
18 to 1B
@RWj + disp16
1
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
2
2
2
1
Number of execution cycles for addressing modes
Note: (a) is used for ~ (number of cycles) and B (correction value) in instruction table.
Table 5
Correction Value for Number of Cycles for Calculating Actual Number of Cycles
(b)*
(c)*
(d)*
byte
word
long
Internal register
+0
+0
+0
Internal RAM even address
Internal RAM odd address
+0
+0
+0
+1
+0
+2
Other than internal RAM even address
Other than internal RAM odd address
+1
+1
+1
+3
+2
+6
External data bus 8-bit
+1
+3
+6
Operand
Notes: • (b), (c), (d) is used for ~ (number of cycles) and B (correction value) in instruction table.
81
MB90246A Series
Table 6
Transmission Instruction (Byte) [50 Instructions]
Mnemonic
MOV A, dir
MOV A, addr16
MOV A, Ri
MOV A, ear
MOV A, eam
MOV A, io
MOV A, #imm8
MOV A, @A
MOV A, @RLi + disp8
MOV A, @SP + disp8
MOVP A, addr24
MOVP A, @A
MOVN A, #imm4
#
~
2
2
2
3
1
1
1
2
2 + 2 + (a)
2
2
2
2
2
2
6
3
3
3
3
5
2
2
1
1
B
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RWi + disp8
A, @RLi + disp8
A, @SP + disp8
MOVPX A, addr24
MOVPX A, @A
2
2
2
3
1
2
1
2
2 + 2 + (a)
2
2
2
2
2
2
3
2
6
3
3
3
3
5
2
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
(b)
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVP
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi + disp8, A
@SP + disp8, A
addr24, A
2
2
2
3
1
1
2
2
2 + 2 + (a)
2
2
6
3
3
3
3
5
MOV
MOV
MOVP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
Ri, ear
Ri, eam
@A, Ri
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
2
2
2 + 3 + (a)
3
2
3
2
2 + 3 + (a)
2
2
3
3
3
3
2
3
3 + 2 + (a)
MOV
@AL, AH
XCH
XCH
XCH
XCH
A, ear
A, eam
Ri, ear
Ri, eam
2
2
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
*
*
*
*
*
*
*
–
*
*
*
–
*
I
–
–
–
–
–
–
–
–
–
–
–
–
–
X
X
X
X
X
X
X
X
byte (A) ← ((RWi) + disp8) X
byte (A) ← ((RLi) + disp8) X
byte (A) ← ((SP) + disp8) X
X
byte (A) ← (addr24)
X
byte (A) ← ((A))
*
*
*
*
*
*
*
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(b)
(b)
0
0
(b)
(b)
(b)
(b)
(b)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte (addr24) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
(b)
(b)
0
(b)
0
(b)
(b)
0
(b)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte ((A)) ← (Ri)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
–
*
*
*
*
*
*
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(b)
byte ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
3
2
2 + 3 + (a) 2 × (b)
0
4
2
2 + 5 + (a) 2 × (b)
byte (A) ← ((RLi) + disp8)
byte (A) ← ((SP) + disp8)
byte (A) ← (addr24)
byte (A) ← ((A))
byte (A) ← imm4
byte ((RLi) + disp8) ← (A)
byte ((SP) + disp8) ← (A)
LH AH
S
–
–
–
–
–
–
–
–
–
–
–
–
–
T
–
–
–
–
–
–
–
–
–
–
–
–
–
N
*
*
*
*
*
*
*
*
*
*
*
*
R
Z
*
*
*
*
*
*
*
*
*
*
*
*
*
V
–
–
–
–
–
–
–
–
–
–
–
–
–
C RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Note: For (a) and (b), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
82
MB90246A Series
Table 7
Mnemonic
#
Transmission Instruction (Word) [40 Instructions]
~
B
2
A, dir
2
2
A, addr16
3
2
A, SP
1
1
A, RWi
1
1
A, ear
2
A, eam
2 + 2 + (a)
2
A, io
2
2
A, @A
2
2
A, #imm16
3
3
A, @RWi + disp8 2
6
A, @RLi + disp8
3
3
A, @SP + disp8 3
3
5
MOVPW A, addr24
2
2
MOVPW A, @A
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
(c)
2
3
4
1
1
2
2+
2
2
3
3
5
2
2
2+
2
2+
3
4
4
4+
2
2
2
2
1
2
2 + (a)
2
3
6
3
3
3
2
3 + (a)
3
3 + (a)
2
3
2
2 + (a)
(c)
(c)
0
0
0
0
(c)
(c)
(c)
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
2
2
(c)
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVPW
MOVPW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
dir, A
addr16, A
SP, #imm16
SP, A
RWi, A
ear, A
eam, A
io, A
@RWi + disp8, A
@RLi + disp8, A
@SP + disp8, A
addr24, A
@A, RWi
RWi, ear
RWi, eam
ear, RWi
eam, RWi
RWi, #imm16
io, #imm16
ear, #imm16
eam, #imm16
MOVW @AL, AH
XCHW
XCHW
XCHW
XCHW
A, ear
A, eam
RWi, ear
RWi, eam
Operation
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
–
–
–
–
–
–
–
–
–
word (A) ← ((RWi)
–
+disp8)
–
word (A) ← ((RLi) +disp8) –
word (A) ← ((SP) + disp8) –
–
word (A) ← (addr24)
word (A) ← ((A))
–
–
word (dir) ← (A)
–
word (addr16) ← (A)
–
word (SP) ← imm16
–
word (SP) ← (A)
–
word (RWi) ← (A)
–
word (ear) ← (A)
–
word (eam) ← (A)
–
word (io) ← (A)
word ((RWi) +disp8) ←
–
(A)
–
word ((RLi) +disp8) ← (A) –
word ((SP) + disp8) ← (A) –
–
word (addr24) ← (A)
–
word ((A)) ← (RWi)
–
word (RWi) ← (ear)
–
word (RWi) ← (eam)
–
word (ear) ← (RWi)
–
word (eam) ← (RWi)
–
word (RWi) ← imm16
–
word (io) ← imm16
word (ear) ← imm16
–
word (eam) ← imm16
0
3
2
word ((A)) ← (AH)
2 + 3 + (a) 2 × (c)
0
4
2
word (A) ↔ (ear)
2 + 5 + (a) 2 × (c) word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
I
S
T
N
Z
V
C RMW
*
*
*
*
*
*
*
–
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
LH AH
–
–
–
–
Note: For (a) and (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
83
MB90246A Series
Table 8
Mnemonic
MOVL A, ear
MOVL A, eam
MOVL A, #imm32
MOVL A, @SP + disp8
MOVPL A, addr24
MOVPL A, @A
MOVPL @A, RLi
MOVL
MOVPL
MOVL
MOVL
@SP + disp8, A
addr24, A
ear, A
eam, A
Transmission Instruction (Long) [11 Instructions]
#
~
2
2
2 + 3 + (a)
5
3
3
4
5
4
2
3
2
5
3
4
5
4
2
2
2 + 3 + (a)
B
0
(d)
0
(d)
(d)
(d)
Operation
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (A) ← (addr24)
long (A) ← ((A))
–
–
–
–
–
–
–
–
–
–
–
–
I
–
–
–
–
–
–
(d)
long ((A)) ← (RLi)
–
–
–
–
–
*
*
–
–
–
(d)
(d)
0
(d)
long ((SP) + disp8) ← (A)
long (addr24) ← (A)
long (ear) ← (A)
long (eam) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
long (A) ← ((SP) + disp8)
LH AH
S
–
–
–
–
–
–
T
–
–
–
–
–
–
N
*
*
*
*
*
*
Z
*
*
*
*
*
*
V
–
–
–
–
–
–
C RMW
–
–
–
–
–
–
–
–
–
–
–
–
Note: For (a) and (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
84
MB90246A Series
Table 9
Mnemonic
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
#
~
Add/Subtract (Byte, Word, Long) [42 Instructions]
B
A,#imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
A, #imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
2
2
2+
2
2+
1
2
2+
1
2
0
3
(b)
2
0
3 + (a) (b)
2
0
3 + (a) 2 × (b)
2
0
2
0
3 + (a) (b)
3
0
2
0
3
(b)
2
0
3 + (a) (b)
2
0
3 + (a) 2 × (b)
2
0
2
0
3 + (a) (b)
3
0
ADDW A
ADDW A, ear
ADDW A, eam
ADDW A, #imm16
ADDW ear, A
ADDW eam, A
ADDCW A, ear
ADDCW A, eam
SUBW A
SUBW A, ear
SUBW A, eam
SUBW A, #imm16
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
0
2
0
3 + (a) (c)
2
0
2
0
3 + (a) 2 × (c)
2
0
3 + (a) (c)
2
0
2
0
3 + (a) (c)
2
0
2
0
3 + (a) 2 × (c)
2
0
3 + (a) (c)
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
2
5
2 + 6 + (a)
5
4
2
5
2 + 6 + (a)
5
4
A, ear
A, eam
A, #imm32
A, ear
A, eam
A, #imm32
0
(d)
0
0
(d)
0
LH AH
I
S
T
N
Z
V
C RMW
byte (A) ← (AH) – (AL) – (C) (decimal)
Z
Z
Z
Z
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
–
Z
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) – (ear) + (A)
word (eam) – (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
word (A) ← (A) – (eam)
word (A) ← (A) – imm16
word (ear) ← (ear) – (A)
word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
word (A) ← (A) – (eam) – (C)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
*
–
–
–
–
–
–
*
*
–
–
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) – (ear)
long (A) ← (A) – (eam)
long (A) ← (A) – imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
Operation
byte (A) ← (A) +imm8
byte (A) ← (A) +(dir)
byte (A) ← (A) +(ear)
byte (A) ← (A) +(eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear) + (C)
byte (A) ← (A) + (eam) + (C)
byte (A) ← (AH) + (AL) + (C) (decimal)
byte (A) ← (A) – imm8
byte (A) ← (A) – (dir)
byte (A) ← (A) – (ear)
byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
byte (eam) ← (eam) – (A)
byte (A) ← (AH) – (AL) – (C)
byte (A) ← (A) – (ear) – (C)
byte (A) ← (A) – (eam) – (C)
Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
85
MB90246A Series
Table 10
Mnemonic
#
Increment/Decrement (Byte, Word, Long) [12 Instructions]
~
B
Operation
LH AH
I
S
T
N
Z
V
C RMW
INC
INC
ear
eam
2
2
0
byte (ear) ← (ear) +1
2 + 3 + (a) 2 × (b) byte (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
DEC
DEC
ear
eam
2
2
0
byte (ear) ← (ear) –1
2 + 3 + (a) 2 × (b) byte (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
INCW
INCW
ear
eam
2
2
0
word (ear) ← (ear) +1
2 + 3 + (a) 2 × (c) word (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
–
–
–
–
–
*
DECW ear
2
2
0
word (ear) ← (ear) –1
*
–
*
*
–
*
DECW eam
2 + 3 + (a) 2 × (c) word (eam) ← (eam) –1
–
–
–
–
–
*
*
*
INCL
INCL
ear
eam
2
4
0
long (ear) ← (ear) +1
2 + 5 + (a) 2 × (d) long (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECL
DECL
ear
eam
2
4
0
long (ear) ← (ear) –1
2 + 5 + (a) 2 × (d) long (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
Table 11
Mnemonic
#
~
Compare (Byte, Word, Long) [11 Instructions]
B
Operation
LH AH
I
S
T
N
Z
V
C RMW
CMP
CMP
CMP
CMP
A
A, ear
A, eam
A, #imm8
1
1
2
2
2 + 3 + (a)
2
2
0
0
(b)
0
byte (AH) – (AL)
byte (A) – (ear)
byte (A) – (eam)
byte (A) – imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW
CMPW
CMPW
CMPW
A
A, ear
A, eam
A, #imm16
1
1
2
2
2 + 3 + (a)
3
2
0
0
(c)
0
word (AH) – (AL)
word (A) – (ear)
word (A) – (eam)
word (A) – imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPL
CMPL
CMPL
A, ear
A, eam
A, #imm32
2
6
2 + 7 + (a)
5
3
0
(d)
0
word (A) – (ear)
word (A) – (eam)
word (A) – imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
86
MB90246A Series
Table 12
Mnemonic
Unsigned Multiply/Division (Word, Long) [11 Instructions]
#
~
B
0
Operation
DIVU
A
1
*1
DIVU
A, ear
2
*2
DIVU
A, eam
DIVUW
A, ear
2
*4
DIVUW
A, eam
2+
*5
MULU
MULU
MULU
MULUW
MULUW
MULUW
A
A, ear
A, eam
A
A, ear
A, eam
1
2
2+
1
2
2+
*8 0 byte (AH) byte (AL) → word (A)
*9 0 byte (A) byte (ear) → word (A)
*10 (b) byte (A) byte (eam) → word (A)
*11 0 word (AH) word (AL) → long (A)
*12 0 word (A) word (ear) → long (A)
*13 (c) word (A) word (eam) → long (A)
2 + *3
word (AH) /byte (AL)
Quotient → byte (AL)
Remainder → byte (AH)
0 word (A)/byte (ear)
Quotient → byte (A)
Remainder → byte (ear)
*6 word (A)/byte (eam)
Quotient → byte (A)
Remainder → byte (eam)
0 long (A)/word (ear)
Quotient → word (A)
Remainder → word (ear)
*7 long (A)/word (eam)
Quotient → word (A)
Remainder → word (eam)
LH AH
I
S
T
N
Z
V
C RMW
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Note: For (b) and (c), refer to “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of
Cycles.”
*1: Set to 3 when the division-by-0, 6 for an overflow, and 14 for normal operation.
*2: Set to 3 when the division-by-0, 6 for an overflow, and 13 for normal operation.
*3: Set to 5 + (a) when the division-by-0, 7 + (a) for an overflow, and 17 + (a) for normal operation.
*4: Set to 3 when the division-by-0, 5 for an overflow, and 21 for normal operation.
*5: Set to 4 + (a) when the division-by-0, 7 + (a) for an overflow, and 25 + (a) for normal operation.
*6: When the division-by-0, (b) for an overflow, and 2 × (b) for normal operation.
*7: When the division-by-0, (c) for an overflow, and 2 × (c) for normal operation.
*8: Set to 3 when byte (AH) is zero, 7 when byte (AH) is not zero.
*9: Set to 3 when byte (ear) is zero, 7 when byte (ear) is not zero.
*10:Set to 4 + (a) when byte (eam) is zero, 8 + (a) when byte (eam) is not zero.
*11:Set to 3 when word (AH) is zero, 11 when word (AH) is not zero.
*12:Set to 4 when word (ear) is zero, 11 when word (ear) is not zero.
*13:Set to 4 + (a) when word (eam) is zero, 12 + (a) when word (eam) is not zero.
87
MB90246A Series
Table 0
Signed multiplication/division (Word, Long) [11 Instructions]
Mnemonic
DIV
A
#
2
~
*1
DIV
A, ear
2
*2
DIV
A, eam
DIVW
A, ear
DIVW
A, eam
2 + *5
MUL
MUL
MUL
MULW
MULW
MULW
A
A, ear
A, eam
A
A, ear
A, eam
2
2
2+
2
2
2+
2 + *3
2
*4
*8
*9
*10
*11
*12
*13
B
Operation
0 word (AH)/byte (AL)
Quotient → byte (AL)
Remainder → byte (AH)
0 word (A)/byte (ear)
Quotient → byte (A)
Remainder → byte (ear)
*6 word (A)/byte (eam)
Quotient → byte (A)
Remainder → byte (eam)
0 long (A)/word (ear)
Quotient → word (A)
Remainder → word (ear)
*7 long (A)/word (eam)
Quotient → word (A)
Remainder → word (eam)
0 byte (AH) × byte (AL) → word (A)
0 byte (A) × byte (ear) → word (A)
(b) byte (A) × byte (eam) → word (A)
0 word (AH) × word (AL) → long (A)
0 word (A) × word (ear) → long (A)
(b) word (A) × word (eam) → long (A)
Z
–
I
–
Z
–
–
–
–
–
–
*
*
–
Z
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
LH AH
S
–
T
–
N
–
Z
–
V
*
C RMW
*
–
For (b) and (c), refer to “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1:
*2:
*3:
*4:
Set to 3 for divide-by-0, 8 or 18 for an overflow, and 18 for normal operation.
Set to 3 for divide-by-0, 10 or 21 for an overflow, and 22 for normal operation.
Set to 4 + (a) for divide-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation.
Positive divided: Set to 4 for divide-by-0, 10 or 29 for an overflow, and 30 for normal operation.
Negative divided: Set to 4 for divide-by-0, 11 or 30 for an overflow, and 31 for normal operation.
*5: Positive divided: Set to 4 + (a) for divide-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation.
Negative divided: Set to 4 + (a) for divide-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal
operation.
*6: Set to (b) when the division-by-0 or an overflow, and 2 × (b) for normal operation.
*7: Set to (c) when the division-by-0 or an overflow, and 2 × (c) for normal operation.
*8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
*10:Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative.
*11:Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*12:Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
*13:Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative.
Note: When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two
values because of detection before and after an operation.
When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed.
88
MB90246A Series
Table 14
Mnemonic
#
~
B
Logic 1 (Byte, Word) [39 Instructions]
Operation
LH AH
I
S
T
N
Z
V
C RMW
AND
AND
AND
AND
AND
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
0
2
2
0
2 + 3 + (a) (b)
2
3
0
2 + 3 + (a) 2 × (b)
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
byte (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
*
*
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
0
2
2
0
2 + 3 + (a) (b)
2
3
0
2 + 3 + (a) 2 × (b)
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
byte (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
*
*
XOR
XOR
XOR
XOR
XOR
NOT
NOT
NOT
A, #imm8
A, ear
A, eam
ear, A
eam, A
A
ear
eam
2
2
0
2
2
0
2 + 3 + (a) (b)
2
3
0
2 + 3 + (a) 2 × (b)
1
2
0
2
2
0
2 + 3 + (a) 2 × (b)
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
byte (eam) ← (eam) xor (A)
byte (A) ← not (A)
byte (ear) ← not (ear)
byte (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
ANDW
ANDW
ANDW
ANDW
ANDW
ANDW
A
A, #imm16
A, ear
A, eam
ear, A
eam, A
1
2
0
3
2
0
2
2
0
2 + 3 + (a) (c)
2
3
0
2 + 3 + (a) 2 × (c)
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
word (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
*
*
ORW
ORW
ORW
ORW
ORW
ORW
A
A, #imm16
A, ear
A, eam
ear, A
eam, A
1
2
0
3
2
0
2
2
0
2 + 3 + (a) (c)
2
3
0
2 + 3 + (a) 2 × (c)
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
word (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
*
*
XORW
XORW
XORW
XORW
XORW
XORW
NOTW
NOTW
NOTW
A
A, #imm16
A, ear
A, eam
ear, A
eam, A
A
ear
eam
1
2
0
3
2
0
2
2
0
2 + 3 + (a) (c)
2
3
0
2 + 3 + (a) 2 × (c)
1
2
0
2
3
0
2 + 3 + (a) 2 × (c)
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
word (eam) ← (eam) xor (A)
word (A) ← not (A)
word (ear) ← not (ear)
word (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
Note: For (a) to (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
89
MB90246A Series
Table 15
Mnemonic
#
~
Logic 2 (Long) [6 Instructions]
B
Operation
LH AH
I
S
T
N
Z
V
C RMW
ANDL
ANDL
A, ear
A, eam
2
5
2 + 6 + (a)
0
(d)
long (A) ← (A) and (ear)
long (A) ← (A) and (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
ORL
ORL
A, ear
A, eam
2
5
2 + 6 + (a)
0
(d)
long (A) ← (A) or (ear)
long (A) ← (A) or (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
XORL
XORL
A, ear
A, eam
2
5
2 + 6 + (a)
0
(d)
long (A) ← (A) xor (ear)
long (A) ← (A) xor (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
Note: For (a) and (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
Table 16
Mnemonic
NEG
A
NEG
NEG
ear
eam
Sign Reverse (Byte, Word) [6 Instructions]
#
~
RG
B
Operation
1
2
0
0
byte (A) ← 0 – (A)
LH AH
I
S
T
N
Z
V
C
RMW
X
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
word (A) ← 0 – (A)
–
–
–
–
–
*
*
*
*
–
0
word (ear) ← 0 – (ear)
2 × (c) word (eam) ← 0 – (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
2
3
2
0
byte (ear) ← 0 – (ear)
2 + 5 + (a) 0 2 × (b) byte (eam) ← 0 – (eam)
NEGW A
1
NEGW ear
NEGW eam
2
0
2
3
2
2 + 5 + (a) 0
0
Note: For (a) and (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
Table 17
Mnemonic
ABS
A
ABSW A
ABSL A
Mnemonic
NRML
A, R0
Absolute Values (Byte, Word, Long) [3 Instructions]
#
~
B
2
2
2
2
2
4
0
0
0
Operation
byte (A) ← Absolute value (A)
word (A) ← Absolute value (A)
long (A) ← Absolute value (A)
I
S
T
N
Z
V
C RMW
Z
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
Table 18
Normalize Instruction (Long) [1 Instruction]
#
~
RG
B
Operation
2
*1
1
0
long (A) ← Shift to where “1”
is originally located
byte (R0) ← Number of shifts
in the operation
* : Set to 5 when the accumulator is all “0”, otherwise set to 5 + (R0).
90
LH AH
LH AH
–
–
–
–
–
I
S
T
N
Z
V
C
RMW
–
–
–
–
*
–
–
–
MB90246A Series
Table 19
Mnemonic
RORC A
ROLC A
Shift Type Instruction (Byte, Word, Long) [27 Instructions]
#
~
B
2
2
2
2
0
0
2
Operation
LH AH
I
S T N Z V C
RMW
byte (A) ← With right-rotate carry
byte (A) ← With left-rotate carry
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
*
*
–
–
3 + (a)
0
2 × (b)
0
2 × (b)
byte (ear) ← With right-rotate carry
byte (eam) ← With right-rotate carry
byte (ear) ← With left-rotate carry
byte (eam) ← With left-rotate carry
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
*
*
*
*
RORC
RORC
ROLC
ROLC
ear
eam
ear
eam
2
2+
2
2+
ASR
LSR
LSL
A, R0
A, R0
A, R0
2
2
2
*1
*1
*1
0
0
0
byte (A) ← Arithmetic right barrel shift (A, R0)
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASR
LSR
LSL
A, #imm8
A, #imm8
A, #imm8
3
3
3
*3
*3
*3
0
0
0
byte (A) ← Arithmetic right barrel shift (A, imm8)
byte (A) ← Logical right barrel shift (A, imm8)
byte (A) ← Logical left barrel shift (A, imm8)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
1
1
1
2
2
2
0
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
–
–
–
–
–
–
–
–
–
–
–
–
* *
* R
– *
*
*
*
–
–
–
*
*
*
–
–
–
2
2
2
*1
*1
*1
0
0
0
word (A) ← Arithmetic right barrel shift (A, R0)
word (A) ← Logical right barrel shift (A, R0)
word (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
3
ASRW A, #imm8 3
LSRW A, #imm8 3
LSLW A, #imm8
*3
*3
*3
0
0
0
word (A) ← Arithmetic right barrel shift (A, imm8)
word (A) ← Logical right barrel shift (A, imm8)
word (A) ← Logical left barrel shift (A, imm8)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRL A, R0
LSRL A, R0
LSLL A, R0
2
2
2
*2
*2
*2
0
0
0
long (A) ← Arithmetic right barrel shift (A, R0)
long (A) ← Logical right barrel shift (A, R0)
long (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRL A, #imm8 3
LSRL A, #imm8 3
LSLL A, #imm8 3
*4
*4
*4
0
0
0
long (A) ← Arithmetic right barrel shift (A, imm8)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRW A
LSRW A/SHRW
A
LSLW
3 + (a)
2
A/SHLW A
ASRW A, R0
LSRW A, R0
LSLW A, R0
long (A) ← Logical right barrel shift (A, imm8)
long (A) ← Logical left barrel shift (A, imm8)
Note: For (a) and (b), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1:
*2:
*3:
*4:
Set to 3 when R0 is 0, otherwise 3 + (R0).
Set to 3 when R0 is 0, otherwise 4 + (R0).
Set to 3 when imm8 is 0, otherwise 3 + imm8.
Set to 3 when imm8 is 0, otherwise 4 + imm8.
91
MB90246A Series
Table 20
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN
rel
BP
rel
BV
rel
BNV
rel
BT
rel
BNT
rel
BLT
rel
BGE
rel
BLE
rel
BGT
rel
BLS
rel
BHI
rel
BRA
rel
#
~
B
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
JMP
JMP
JMP
JMP
JMPP
JMPP
JMPP
@A
addr16
@ear
@eam
@ear *3
@eam *3
addr24
1
2
3
2
2
3
2 + 4 + (a)
2
3
2 + 4 + (a)
4
3
CALL
CALL
CALL
CALLV
CALLP
@ear *4
@eam *4
addr16 *5
#vct4 *5
@ear *6
2
4
(c)
2 + 5 + (a) 2 × (c)
3
5
(c)
1
5
2 × (c)
2
7
2 × (c)
CALLP
@eam *6
2 + 8 + (a)
CALLP
addr24 *7
4
7
0
0
0
(c)
0
(d)
0
*2
2 × (c)
Branch 1 [31 Instructions]
Operation
Branch if (Z) = 1
Branch if (Z) = 0
Branch if (C) = 1
Branch if (C) = 0
Branch if (N) = 1
Branch if (N) = 0
Branch if (V) = 1
Branch if (V) = 0
Branch if (T) = 1
Branch if (T) = 0
Branch if (V) xor (N) = 1
Branch if (V) xor (N) = 0
Branch if ((V) xor (N)) or (Z) = 1
Branch if ((V) xor (N)) or (Z) = 0
Branch if (C) or (Z) = 1
Branch if (C) or (Z) = 0
Branch unconditionally
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← (ear), (PCB) ← (ear + 2)
word (PC) ← (eam), (PCB) ← (eam + 2)
word (PC) ← ad24 0 – 15,
(PCB) ← ad24 16 – 23
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← addr16
Vector call instruction
word (PC) ← (ear) 0 – 15
(PCB) ← (ear) 16 – 23
word (PC) ← (eam) 0 – 15
(PCB) ← (eam) 16 – 23
word (PC) ← addr0 – 15,
(PCB) ← addr16 – 23
LH AH
I
S T N Z V C RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Note: For (a), (c) and (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5
Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1:
*2:
*3:
*4:
*5:
*6:
*7:
92
Set to 3 when branch is executed, and 2 when branch is not executed.
3 × (c) + (b)
Reads (word) of the branch destination address.
W pushes to stack (word), and R reads (word) of the branch destination address.
Pushes to stack (word).
W pushes to stack (long), and R reads (long) of the branch destination address.
Pushes to stack (long).
MB90246A Series
Table 21
Mnemonic
CBNE A, #imm8, rel
CWBNE A, #imm16, rel
CBNE
CBNE
CWBNE
CWBNE
ear, #imm8, rel
eam, #imm8, rel
ear, #imm16, rel
eam, #imm16, rel
DBNZ
ear, rel
DBNZ
eam, rel
DWBNZ ear, rel
DWBNZ eam, rel
#
~
B
3 *1
4 *1
0
0
4
4+
5
5+
*1
*3
*1
*3
3 *2
0
(b)
0
(c)
Operation
8 × (c)
6 × (c)
6 × (c)
8 × (c)
6 × (c)
*5
LINK
2
6
(c)
UNLINK
1
5
(c)
RET *7
RETP *8
1
1
4
5
(c)
(d)
T
N
Z
V
C RMW
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
Branch if byte (ear) ≠ imm8
Branch if byte (eam) ≠ imm8
Branch if word (ear) ≠ imm16
Branch if word (eam) ≠ imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
R
R
R
R
*
*
S
S
S
S
*
*
–
–
–
–
*
*
–
–
–
–
*
*
–
–
–
–
*
*
–
–
–
–
*
*
–
–
–
–
*
*
–
–
–
–
–
–
Stores old frame pointer in –
the beginning of the
function, set new frame
pointer, and reserves local
pointer area
Restore old frame pointer –
from stack in the end of
the function
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Return from subroutine
Return from subroutine
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (ear) = (ear) – 1,
Branch if (ear) ≠ 0
3 + *4 2 × (c) word (eam) = (eam) – 1,
Branch if (eam) ≠ 0
14
12
13
14
9
11
S
–
–
0
2
3
4
1
1
2
I
Branch if byte (A) ≠ imm8
byte (ear) = (ear) – 1,
Branch if (ear) ≠ 0
3 + *4 2 × (b) byte (eam) = (eam) – 1,
Branch if (eam) ≠ 0
3 *2
LH AH
Branch if word (A) ≠ imm16
0
INT
#vct8
INT
addr16
INTP
addr24
INT9
RETI
RETIQ *6
#imm8
Branch 2 [20 Instructions]
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
Return from interrupt
–
–
Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1:
*2:
*3:
*4:
*5:
*6:
Set to 4 when branch is executed, and 3 when branch is not executed.
Set to 5 when branch is executed, and 4 when branch is not executed.
Set to 5 + (a) when branch is executed, and 4 + (a) when branch is not executed.
Set to 6 + (a) when branch is executed, and 5 + (a) when branch is not executed.
Set to 3 × (b) + 2 × (c) when an interrupt request is issued, and 6 × (c) for return.
This is a high-speed interrupt return instruction. In the instruction, an interrupt request is detected. When an
interrupt occurs, stack operation is not performed, with this instruction branching to the interrupt vector.
*7: Return from stack (word).
*8: Return from stack (long).
93
MB90246A Series
Table 22
Mnemonic
Miscellaneous Control Types (Byte, Word, Long) [36 Instructions]
#
~
B
Operation
LH AH
I
S T N Z V C RMW
PUSHW
PUSHW
PUSHW
PUSHW
A
AH
PS
rlst
1
1
1
2
3
3
3
*3
(c)
(c)
(c)
*4
word (SP) ← (SP) – 2, ((SP)) ← (A) –
word (SP) ← (SP) – 2, ((SP)) ← (AH)
–
word (SP) ← (SP) – 2, ((SP)) ← (PS)
–
(PS) ← (PS) – 2n, ((SP)) ← (rlst)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
POPW
POPW
POPW
POPW
A
AH
PS
rlst
1
1
1
2
3
3
3
*2
(c)
(c)
(c)
*4
word (A) ← ((SP)), (SP) ← (SP) + 2
word (AH) ← ((SP)), (SP) ← (SP) + 2
word (PS) ← ((SP)), (SP) ← (SP) + 2
(rlst) ← ((SP)), (SP) ← (SP) + 2n
–
–
–
–
*
–
–
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
–
–
JCTX
@A
1
9
–
–
*
*
*
*
*
*
*
–
AND
OR
CCR, #imm8
CCR, #imm8
2
2
3
3
0
0
byte (CCR) ← (CCR) and imm8 –
byte (CCR) ← (CCR) or imm8 –
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
MOV
MOV
RP, #imm8
ILM, #imm8
2
2
2
2
0
0
byte (RP) ← imm8
byte (ILM) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVEA
MOVEA
MOVEA
MOVEA
RWi, ear
RWi, eam
A, ear
A, eam
0
0
0
0
word (RWi) ← ear
word (RWi) ← eam
word(A) ← ear
word (A) ← eam
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
2
2 + 2 + (a)
2
2
2 + 1 + (a)
6 × (c) Context switch instruction
2
3
3
3
0
0
word (SP) ← (SP) + ext (imm8) –
–
word (SP) ← (SP) + imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
MOV
A, brgl
2
brg2, A
2
brg2, #imm8 3
*1
1
2
0
0
0
byte (A) ← (brgl)
byte (brg2) ← (A)
byte (brg2) ← imm8
Z
–
–
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
NOP
ADB
DTB
PCB
SPB
NCC
CMR
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
No operation
Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no change in flag
Prefix for common register bank
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVW SPCU, #imm16
MOVW SPCL, #imm16
SETSPC
CLRSPC
4
4
2
2
2
2
2
2
0
0
0
0
word (SPCU) ← (imm16)
word (SPCL) ← (imm16)
Enables stack check operation.
Disables stack check operation.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
BTSCN A
BTSCNS A
BTSCND A
2
2
2
*5
*6
*7
0
0
0
Bit position of 1 in byte (A) from word (A)
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
ADDSP #imm8
ADDSP #imm16
Bit position (× 2) of 1 in byte (A) from word
(A)
Bit position (× 4) of 1 in byte (A) from word
(A)
Note: For (a) and (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB
: 2 states
DPR
: 3 states
*2: 3 + 4 × (number of POPs)
94
MB90246A Series
*3:
*4:
*5:
*6:
*7:
3 + 4 × (number of PUSHes)
(Number of POPs) × (c), or (number of PUSHes) × (c)
Set to 3 when AL is 0, 5 when AL is not 0.
Set to 4 when AL is 0, 6 when AL is not 0.
Set to 5 when AL is 0, 7 when AL is not 0.
Table 23
Bit Manipulation Instruction [21 Instructions]
LH AH
I
S T N Z V C RMW
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
2 × (b) bit (dir:bp) b ← (A)
2 × (b) bit (addr16:bp) b ← (A)
2 × (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
4
4
4
2 × (b) bit (dir:bp) b ← 1
2 × (b) bit (addr16:bp) b ← 1
2 × (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
3
4
3
4
4
4
2 × (b) bit (dir:bp) b ← 0
2 × (b) bit (addr16:bp) b ← 0
2 × (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*1
(b)
(b)
(b)
Branch if (dir:bp) b = 0
Branch if (addr16:bp) b = 0
Branch if (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*1
(b)
(b)
(b)
Branch if (dir:bp) b = 1
Branch if (addr16:bp) b = 1
Branch if (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
SBBS addr16:bp, rel
5
*2
2 × (b) Branch if (addr16:bp) b = 1, bit = 1
–
–
–
–
–
–
*
–
–
*
WBTS io:bp
3
*3
*4
Wait until (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
WBTC io:bp
3
*3
*4
Wait until (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
Mnemonic
#
~
B
MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp
3
4
3
3
3
3
(b)
(b)
(b)
MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A
3
4
3
4
4
4
SETB dir:bp
SETB addr16:bp
SETB io:bp
3
4
3
CLRB dir:bp
CLRB addr16:bp
CLRB io:bp
BBC
BBC
BBC
BBS
BBS
BBS
Operation
byte (A) ← (dir:bp) b
byte (A) ← (addr16:bp) b
byte (A) ← (io:bp) b
Note: For (b), refer to “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1:
*2:
*3:
*4:
Set to 5 when branch is executed, and 4 when branch is not executed.
7 if conditions are met, 6 when conditions are not met.
Indeterminate times
Until conditions are met
95
MB90246A Series
Table 24
Mnemonic
SWAP
SWAPW/XCHW AL, AH
EXT
EXTW
ZEXT
ZEXTW
Accumulator Manipulation Instruction (Byte, Word) [6 Instructions]
#
~
B
1
1
1
1
1
1
3
2
1
2
1
1
0
0
0
0
0
0
Operation
byte (A) 0 – 7 ↔ (A) 8 – 15
word (AH) ↔ (AL)
byte sign-extension
word sign-extension
byte zero-extension
word zero-extension
Table 25
Mnemonic
LH AH
I
S
T
N
Z
V
C RMW
–
–
X
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
I
S
T
N
Z
V
C RMW
–
*
–
X
–
Z
String Instruction [10 Instructions]
#
~
B
Operation
MOVS/MOVSI
2
*2
–
–
–
–
–
–
–
–
–
–
MOVSD
2
*2
*3 byte transfer @AH + ← @AL +,
Counter = RW0
*3 byte transfer @AH – ← @AL –,
Counter = RW0
–
–
–
–
–
–
–
–
–
–
SCEQ/SCEQI
2
*1
–
–
–
–
–
*
*
*
*
–
SCEQD
2
*1
*4 byte search (@AH +) – AL,
Counter = RW0
*4 byte search (@AH –) – AL,
Counter = RW0
–
–
–
–
–
*
*
*
*
–
FISL/FILSI
2 5m + 6 *5 byte fill @AH + ← AL,
Counter = RW0
–
–
–
–
–
*
*
–
–
–
MOVSW/MOVSWI
2
*2
–
–
–
–
–
–
–
–
–
–
MOVSWD
2
*2
*6 word transfer @AH + ← @AL +,
Counter = RW0
*6 word transfer @AH – ← @AL –,
Counter = RW0
–
–
–
–
–
–
–
–
–
–
SCWEQ/SCWEQI
2
*1
–
–
–
–
–
*
*
*
*
–
SCWEQD
2
*1
*7 word search (@AH +) – AL,
Counter = RW0
*7 word search (@AH –) – AL,
Counter = RW0
–
–
–
–
–
*
*
*
*
–
FILSW/FILSWI
2 5m + 6 *8 word fill @AH + ← AL,
Counter = RW0
–
–
–
–
–
*
*
–
–
–
LH AH
m: RW0 value (counter value)
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
96
–
–
–
–
–
–
3 when RW0 is 0, 2 + 6 × (RW0) when count out, and 6n + 4 when matched
4 when RW0 is 0, otherwise 2 + 6 × (RW0)
(b) × (RW0)
(b) × n
(b) × (RW0)
(c) × (RW0)
(c) × n
(c) × (RW0)
MB90246A Series
Table 26
Multiple Data Transfer Instructions [18 Instruction]
Mnemonic
MOVM @A, @RLi, #imm8
#
3
~
*1
MOVM @A, eam, #imm8
3+
*2
5
*1
MOVM addr16, @RLi, #imm8
MOVM addr16, @eam, #imm8 5 +
*2
MOVMW@A, @RLi, #imm8
3
*1
3+
*2
5
*1
MOVMW@A, eam, #imm8
MOVMWaddr16, @RLi, #imm8
MOVMWaddr16, @eam, #imm8 5 +
*2
MOVM @RLi, @A, #imm8
3
*1
MOVM @eam, A, #imm8
3+
*2
5
*1
MOVM @RLi, addr16, #imm8
MOVM @eam, addr16, #imm8 5 +
*2
MOVMW@RLi, @A, #imm8
3
*1
3+
*2
5
*1
MOVMW@eam, A, #imm8
MOVMW@RLi, addr16, #imm8
MOVMW@eam, addr16, #imm8 5 +
*2
MOVM bnk: addr16,
bnk: addr16, #imm8*5
7
*1
MOVMWbnk: addr16,
7
*1
bnk: addr16, #imm8*5
*1:
*2:
*3:
*4:
*5:
B
Operation
*3 Multiple data transfer
byte ((A)) ← ((RLi))
*3 Multiple data transfer
byte ((A)) ← (eam)
*3 Multiple data transfer
byte (addr16) ← ((RLi))
*3 Multiple data transfer
byte (addr16) ← (eam)
*4 Multiple data transfer
word ((A)) ← ((RLi))
*4 Multiple data transfer
word ((A)) ← (eam)
*4 Multiple data transfer
word (addr16) ←
((RLi))
*4 Multiple data transfer
word (addr16) ← (eam)
*3 Multiple data transfer
byte ((RLi)) ← ((A))
*3 Multiple data transfer
byte (eam) ← ((A))
*3 Multiple data transfer
byte ((RLi)) ← (addr16)
*3 Multiple data transfer
byte (eam) ← (addr16)
*4 Multiple data transfer
word ((RLi)) ← ((A))
*4 Multiple data transfer
word (eam) ← ((A))
*4 Multiple data transfer
word ((RLi)) ←
(addr16)
*4 Multiple data transfer
word (eam) ← (addr16)
*3 Multiple data transfer
byte (bnk: addr16) ←
(bnk: addr16)
*4 Multiple data transfer
word (bnk: addr16) ←
(bnk: addr16)
–
–
I
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
LH AH
S
–
T
–
N
–
Z
–
V
–
C RMW
–
–
256 when 5 + imm8 × 5, imm8 is 0.
256 when 5 + imm8 × 5 + (a), imm8 is 0.
(Number of transfer cycles) × (b) × 2
(Number of transfer cycles) × (c) × 2
The bank register specified by bnk is the same as that for the MOVS instruction.
97
MB90246A Series
■ ORDERING INFORMATION
Part number
MB90246APFV
98
Package
100-pin Plastic LQFP
(FPT-100P-M05)
Remarks
MB90246A Series
■ PACKAGE DIMENSIONS
100-pin Plastic LQFP
(FPT-100P-M05)
+0.20
16.00±0.20(.630±.008)SQ
75
1.50 −0.10 (Mounting height)
+.008
.059 −.004
51
14.00±0.10(.551±.004)SQ
76
50
12.00
(.472)
REF
15.00
(.591)
NOM
Details of "A" part
0.15(.006)
INDEX
100
0.15(.006)
26
0.15(.006)MAX
LEAD No.
"B"
25
1
0.40(.016)MAX
"A"
0.50(.0197)TYP
+0.08
0.18 −0.03
+.003
.007 −.001
+0.05
0.08(.003)
M
0.127 −0.02
+.002
.005 −.001
Details of "B" part
0.10±0.10
(STAND OFF)
(.004±.004)
0.10(.004)
C
1995 FUJITSU LIMITED F100007S-2C-3
0.50±0.20(.020±.008)
0~10˚
Dimensions in mm (inches)
99
MB90246A Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F98010
 FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.