HD66130T 320-channel Low-voltage Segment Driver for Dot-Matrix STN Liquid Crystal Display Description The HD66130T is a 320-channel segment driver for driving a dot-matrix STN liquid-crystal panel at a low voltage. The driver can also correspond to 240-channel output by switching mode. It operates at a low voltage: a liquid-crystal drive voltage of 5 V and a logic drive voltage of 3 V, and is used together with common driver HD66131T or HD66135T. The package, which adopts a flexible TCP, can be applied to various liquid crystal panels. Features • • • • • • • • • • • • • Display duty: Up to 1/240 Liquid crystal drive voltage: 2.6 to 5.5 V Number of liquid crystal drive circuits: 320 circuits Operating voltage: 2.5 to 5.5 V Number of data bits: 4 or 8 bits Shift clock speed: 8 MHz max/5V 6.5 MHz max/3V Together with the common drivers HD66131T , HD66135T Low power consumption Switching output mode: 320 output mode 240 output mode Display-off function Flexible TCP Automatic generation of chip-enable signals Standby function 1 HD66130T Y320 320 316 Y316 317 Y317 318 Y318 319 Y319 2 Y2 3 Y3 4 Y4 5 Y5 1 Y1 Pin Arrangement VML V0L V1L VCC MODE BS GND2 SHL EIO1 DISP D0 D1 D2 D3 D4 D5 D6 D7 CL2 CL1 M EIO2 GND1 V1R V0R VMR 346 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329 328 327 326 325 324 323 322 321 Top View Note: TCP dimensions are not defined. Internal Block Diagram Y1–Y 320 * V0L VML V1L V0L VML V1L Liquid crystal drive circuit Vcc Level shifter GND2 Level shifter GND1 CL1 M Timing generator circuit BS D0–D7 SHL MODE Latch circuit 2 Latch circuit 1 DISP Latch circuit 1 Data rearrangement circuit CL2 Shift register EIO1 EIO2 Note: Pins V0L, VML, and V1L are internally connected to pins V0R, VMR, and V1R, respectively. 2 HD66130T 1. Liquid crystal drive circuit Selects and outputs the liquid crystal drive level V0, VM, or V1 by DISP and a combination of data for latch circuit 2 and signal M. 2. Level shifter Converts logic signals to liquid crystal drive signals. 3. Latch circuit 2 320-bit latch circuit, which latches the data of latch circuits 1 at the fall of CL1 and outputs the data to the level shifter. 4. Latch circuit 1 4/8-bit parallel data latch circuit, which latches display data D0 to D7 according to signals transmitted from the shift register. 5. Shift register 80-bit shift register, which generates data-capture signals for latch circuits 1 at the fall of CL2. 6. Data rearrangement circuit Inverts the order of data output crosswise. 7. Timing generator circuit The timing generator circuit generates data latch pulses for latch circuit2 and changes pulse the LCD drive outputs to AC. HIFAS Family timing Comparision HD66130/131/134/135 Input signal Output signal HD66132/133 CL1 M Segment Common 3 HD66130T Pin Functions Class Power supply Pin Pin Symbol Number Name VCC GND1 GND2 343 324 340 VCC GND V0L, R 345, 322 V0L, R VML, R 346, 321 VML, R V1L, R 344, 323 V1L, R I/O Functions — VCC–GND: Power supply for logic. Input Liquid crystal drive level power supply V0 VM V1 Control signal CL1 327 Clock 1 Input Latch signal of display data: A liquid crystal drive signal corresponding to display data is output at the fall of CL1. CL2 328 Clock 2 Input Capture signal of display data: Display data is captured at the fall of CL2. M 326 M Input A.C. signal of liquid crystal drive output D0 to D7 336 to 329 DATA 0 Input to DATA 7 Display data Liquid crystal drive output Liquid crystal display 1 (Vcc level) Selected level 0 (GND level) Not-selected level ON OFF SHL 339 Shift Left Input Control signal for inverting the order of data output (see the following page) EIO1 338 Enable IO1 I/O SHL EI/O1 EI/O2 GND Enable input Enable output Vcc Enable output Enable input EIO2 325 Enable IO2 I/O DISP 337 Disp off Input Grounding DISP sets liquid crystal drive output Y1–Y320 to the VM level. BS 341 Bus Select Input Switches the number of input bits for the display data. Enable input: The enable input of the first IC is connected to the GND and another is connected to the enable output of the second IC. Enable output: Connected to the enable input of the second IC at cascade output. Vcc 8-bit input mode GND 4-bit input mode (Captures data from D0–D3. At this time, connect D4–D7 to the GND.) MODE 4 342 MODE Input Switches the number of input bits for the display data. Vcc 320 output mode GND 240 output mode (Y41–Y280 are valid output. The other 80 pins output the not-selected-level signals synchronized every time; release these pins.) HD66130T Pin Functions (cont) Class Pin Pin Symbol Number Name Liquid crystal Y1 to drive output Y320 1 to 320 Y1 to Y320 I/O Function Output Liquid crystal drive output: Selects and outputs level V0 or V1 according to the combination of the M signal and display data when DISP is connected to Vcc. D Output level 0 1 M 1 0 1 0 V0 V1 V1 V0 5 HD66130T Rearranging Output Data (SHL) The order for the output of captured data is inverted crosswise according to the SHL signal. At this time, the input/output pin of the enable signal can be switched. SHL = GND, BS = GND Y1 D3 Y2 D2 Y3 Y5 Y4 D1 D0 D3 Y6 Y7 D2 D1 Y8 D0 Y313 Y315 Y317 Y319 Y314 Y316 Y318 Y320 D3 D2 D1 D0 D3 First data D2 D1 D0 Last data Enable input: EIO1 Enable output: EIO2 SHL = Vcc, BS = GND Y1 D0 Y2 D1 Y3 Y5 Y4 D2 D3 D0 Y6 Y7 D1 D2 Y8 D3 Y313 Y315 Y317 Y319 Y314 Y316 Y318 Y320 D0 D1 D2 D3 D0 Last data D1 D2 D3 First data Enable input: EIO2 Enable output: EIO1 SHL = GND, BS = Vcc Y1 Y2 D7 D6 Y3 D5 Y4 Y5 D4 D3 Y6 D2 Y7 D1 Y8 D0 Y313 Y315 Y317 Y319 Y314 Y316 Y318 Y320 D7 D6 D5 First data D4 D3 D2 D1 D0 Last data Enable input: EIO1 Enable output: EIO2 SHL = Vcc, BS = Vcc Y1 Y2 D0 D1 Y3 D2 Y4 Y5 D3 D4 Y6 D5 Y7 D6 Y8 D7 Last data D0 D1 D2 D3 D4 D5 First data Enable input: EIO2 Enable output: EIO1 6 Y313 Y315 Y317 Y319 Y314 Y316 Y318 Y320 D6 D7 HD66130T Operation Timing (1) 4-bit capture mode (1 line, 640 dots) Line CL2 D0 1 2 79 80 d4 d8 d316 d320 d1 d5 d313 d317 81 82 159 160 161 to D3 CL1 EIO2 (No. 1) Data capture period for IC (No. 1) EIO2 (No. 2) Data capture period for IC (No. 2) Y1–Y320 BS = GND (4-bit capture mode) During the data standby state when the data capture operation enable signal is low (SHL = GND: EIO1), the next data capture clock (CL2) cancels the standby state. The 4-bit data is captured at the fall of CL2. When 316 bits are captured, the enable signal becomes the GND level (SHL = GND: EIO2). When 320 bits are captured, the operation automatically stops (the standby state is entered). The second IC is then activated when pin EIO2 is connected to pin EIO1 of the second IC. Data output changes at the fall of CL1. During SHL = GND, captured data d1 and d320 are output to Y1 and Y320, respectively. During SHL = Vcc, data d1 and d320 are output to Y320 and Y1, respectively. 7 HD66130T (2) 8-bit capture mode (1 line, 640 dots) Line CL2 D0 1 2 39 40 d8 d16 d312 d320 d1 d9 d305 d313 41 42 79 80 to D7 CL1 EIO2 (No. 1) Data capture period for IC (No. 1) EIO2 (No. 2) Data capture period for IC (No. 2) Y1–Y320 BS = Vcc (8-bit capture mode) The 8-bit display data is captured at the fall of CL2. Other basic operations are the same as those of the 4bit capture mode. 8 HD66130T VLL, R VML, R VHL, R VLCDL, R VEEL, R DIO1 DISP SHL MWS4–0 M GND CL Vcc MODE HD66131T VLCD VH (COM) Vcc V0 (SEG) VM V1 (SEG) GND VL (COM) VEE Power supply circuit Application Example X240 to X1 COM1 COM2 COM3 COM4 COM5 HD66130T HD66130T GND1,2 EIO2 M CL1 CL2 D0–D7 DISP EIO1 SHL BS MODE Vcc V1L, R V0L, R VML, R SEG1 SEG2 SEG3 SEG4 SEG5 Y320 to Y1 FLM CL1 M DISP D0– D7 CL2 Y320 to Y1 GND1,2 EIO2 M CL1 CL2 D0– D7 DISP EIO1 SHL BS MODE Vcc V1L, R V0L, R VML, R COM236 COM237 COM238 COM239 COM240 SEG636 SEG637 SEG638 SEG639 SEG640 LCD Panel 640 x 240 1/240 duty Controller Notes: 1. When designing the board, connect a capacitor near the IC to stabilize power supply. Use two capacitors of about 0.1 µF for each IC (between Vcc and GND, V0 and GND, VLCD and GND, and VEE and GND). 2. In addition, for the power supply circuit, connect a capacitor of several µF or several tens of µF between the liquid crystal power supply and GND. For set evaluation, confirm that there is no inversion of liquid crystal drive power supply and level power supply in the period between when the liquid crystal drive power supply is turned on and when it is turned off. 3. Configuring the LCD panel using the HD66130 when using the select COMMON driver. The select COMMON driver COMMON driver select HD66131 (240OUT) ● HD66133 (120OUT) × HD66135 (120OUT) ● 9 HD66130T Absolute Maximum Ratings Item Symbol Rating Unit Notes Power supply voltage for logic circuits VCC –0.3 to + 7.0 V 1, 4 Power supply voltage for LCD drive circuits V0 –0.3 to + 7.0 V 1, 4 Input voltage 1 VT1 –0.3 to VCC + 0.3 V 1, 2 Input voltage 2 VT2 –0.3 to V0 + 0.3 V 1, 3, 4 Operating temperature Topr –30 to +75 °C Storage temperature Tstg –55 to +110 °C Notes: 1. Potential from the GND 2. Applied to pins SHL, EIO1, EIO2, DISP, D0 to D7, CL1, CL2, M, BS, and MODE. 3. Applied to VML, VMR, V1L, and VMR. Operating the LSI in excess of the absolute maximum rating will result in permanent damage. Use the LSI observing electrical characteristic conditions in normal operation. Exceeding the conditions will cause malfunctions or will affect LSI reliability. 4. Conform to the following turn-on/off sequence of the power and signals. Otherwise, the LSI will malfunction or will be permanently damaged. In addition, LSI reliability will be affected. Vcc V0 2.7 V 2.7 V 0ms 0ms VM VM V1 V1 0ms 0ms 0ms 0ms DISP Input-signal clock data Signal-undefined period Initialization period (at least one frame) (0 ms: Minimum value) 10 HD66130T 4.1 Turning on the power 1) Turn on the power in the order of GND- VCC, GND-V0, and VM/V1. Then, ground the DISP pin. 2) The LCD forcibly outputs the VM level by the DISPOFF function. 3) Even if an input signal is disturbed immediately after VCC is applied, the DISPOFF function has priority. 4) Input the specific signal to initialize registers in the driver. The initialization period must be at least one frame. 5) The preparation of normal display is completed. Input the VCC level to the DISP pin to cancel the DISPOFF function. At this time, the level of pins V0, VM, and V1 must rise to the specific potential. 4.2 Turning off the power The procedure is basically the reverse for turning on the power. 1) Ground the DISP pin. 2) Turn off the liquid crystal power in the order of VM/V1 and GND-V0. 3) Ground VCC and an input signal. At this time, the level of pins V0, VM, and V1 must fall to 0 V. Since the DISPOFF function stops when VCC falls to 0 V, the LCD may output a level other than VM. Therefore, a display failure may occur when the power is turned off or on. 11 HD66130T Electrical Characteristics DC Characteristics 1 (VCC = 2.5 to 4.5V, V0–GND = 2.6 to 5.5V, Ta = –30 to +75°C) Item Symbol Pins Min Typ Max Input high voltage VIH CL1, CL2, SHL, M, EIO1, EIO2, 0.8 × V CC — Input low voltage VIL MODE, 0 DISP, D0 to D7, BS Output high voltage VOH EIO1, EIO2 Output low voltage VOL EIO1, EIO2 Vi–Yj on resistance RON Unit Test Condition VCC V — 0.2 × V CC V VCC –0.4 — — V I OH = –0.4 mA — — 0.4 V I OL = 0.4 mA Y1 to — Y320, V0L, R 0.7 2.0 kΩ I ON = 150 µA Y1 to — Y320, VML, R 2.0 3.0 kΩ Y1 to — Y320, V1L, R 0.7 2.0 kΩ Input leakage current 1 I IL1 –5.0 CL1, CL2, SHL, M, EIO1, EIO2, MODE, DISP, D0 to D7, BS 5.0 µA VIN = VCC to GND Input leakage current 2 I IL2 VML, –25 R, V1L, R 25 µA VIN = V0 to GND Current consumption 1 I CC VCC 150 300 µA VCC = 3.3 V V0 = 2.7 V Current consumption 2 IV0 V0L, R — 60 200 µA f CL2 = 3.5 MHz f CL1= 19.2 kHz Current consumption 3 I ST VCC 50 100 µA fM = 1.5 kHz 12 — — Notes 1 2 2, 3 HD66130T DC Characteristics 2 (VCC = 4.5 to 5.5V, V0–GND = 2.6 to 5.5V, Ta = –30 to +75°C) Item Symbol Pins Min Typ Max Input high voltage VIH CL1, CL2, SHL, M, EIO1, EIO2, 0.8 × V CC — Input low voltage VIL MODE, 0 DISP, D0 to D7, BS Output high voltage VOH EIO1, EIO2 Output low voltage VOL EIO1, EIO2 Vi–Yj on resistance RON Unit Test Condition VCC V — 0.2 × V CC V VCC –0.4 — — V I OH = –0.4 mA — — 0.4 V I OL = 0.4 mA Y1 to — Y320, V0L, R 0.7 2.0 kΩ I ON = 150 µA Y1 to — Y320, VML, R 2.0 3.0 kΩ Y1 to — Y320, V1L, R 0.7 2.0 kΩ Input leakage current 1 I IL1 –5.0 CL1, CL2, SHL, M, EIO1, EIO2, MODE, DISP, D0 to D7, BS 5.0 µA VIN = VCC to GND Input leakage current 2 I IL2 VML, –25 R, V1L, R 25 µA VIN = V0 to GND Current consumption 1 I CC VCC 230 450 µA VCC = 5.0 V V0 = 2.7 V Current consumption 2 IV0 V0L, R — 60 200 µA f CL2 = 3.5 MHz f CL1= 19.2 kHz Current consumption 3 I ST VCC 80 150 µA fM = 1.5 kHz — — Notes 1 2 2, 3 Notes: 1. Resistance between pins Y and V when a load current flows to one of the pins from Y1 to Y320. The following conditions are defined: V0–GND = 5.5 V VM = (V0 + V1)/2 13 HD66130T V1 = GND + 1.0 The voltage range of the liquid crystal drive level power supply is described. A voltage around the GND is applied to pin V1, and an intermediate voltage of about V0 and V1 is applied to pin VM. Use the V1 in the range of ∆V = 0.25 x V0, in which the impedance Ron of driver output is stable. V0 VM ∆V = 0.25 x V0 V1 GND Relationship between the driver output waveform and each level voltage 2. A current flowing in the input or output section is excluded. If an input signal is at an intermediate level for the CMOS, a through-current flows in the input circuit and power supply current increases. Therefore, VIH must be at the Vcc level and VIL must be at the GND level. 3. Current at standby 4. The voltage of each signal is shown below. Segment voltage Segment waveform Common waveform Common voltage VH (23.0 V) V0 (5.0 V) Vcc (3.3 V) Vcc (3.3 V) VM (3.0 V) VM (3.0 V) V1 (1.0 V) GND (0.0 V) GND (0.0 V) VL (–17.0 V) Normal display period 14 Display-off period Normal display period Display-off period HD66130T AC Characteristics 1 (VCC = 2.5 to 4.5V, V0–GND = 2.6 to 5.5V, Ta = –30 to +75°C) Item Symbol Pins Min Max Unit Clock cycle time t CYC CL2 152 — ns Clock high pulse width 1 t CWH2 CL2 65 — ns Clock low pulse width 1 t CWL2 CL2 65 — ns Clock high pulse width 2 t CWH1 CL1 65 — ns Clock setup time t SCL CL1, CL2 80 — ns Clock hold time t HCL CL1, CL2 80 — ns Clock rise time tr CL1, CL2 — 30 ns Clock fall time tf CL1, CL2 — 30 ns Data setup time t DS D0 to D7, CL2 50 — ns Data hold time t DH D0 to D7, CL2 50 — ns M setup time t MS M, CL1 20 — ns M hold time t MH M, CL1 20 — ns Output delay time 1 t pd1 CL1, Y1 to Y320 — 1000 ns AC Characteristics 2 (VCC = 4.5V to 5.5V, V0–GND = 2.6 to 5.5V, Ta = –30 to +75°C) Item Symbol Pins Min Max Unit Clock cycle time t CYC CL2 125 — ns Clock high pulse width 1 t CWH2 CL2 45 — ns Clock low pulse width 1 t CWL2 CL2 45 — ns Clock high pulse width 2 t CWH1 CL1 45 — ns Clock setup time t SCL CL1, CL2 80 — ns Clock hold time t HCL CL1, CL2 80 — ns Clock rise time tr CL1, CL2 — 20 ns Clock fall time tf CL1, CL2 — 20 ns Data setup time t DS D0 to D7, CL2 20 — ns Data hold time t DH D0 to D7, CL2 20 — ns M setup time t MS M, CL1 20 — ns M hold time t MH M, CL1 20 — ns Output delay time 1 t pd1 CL1, Y1 to Y320 — 1000 Notes: 1. A load must be 10 pF or less for EI/O connection between drivers. 2. For output delay time 1 and 2, connect the load circuit shown below. ns Test point 100 pF 15 HD66130T tr tCWH2 tf tCWL2 tCYC 0.8 Vcc CL2 0.2 Vcc tDS D0–7 tDH 0.8 Vcc 0.2 Vcc tCWH1 0.8 Vcc CL1 0.2 Vcc tSCL tHCL CL2 0.2 Vcc tMS tMH 0.8 Vcc M CL1 0.2 Vcc 0.2 Vcc tpd1 Y (n) 16 0.8 V0 0.2 V1