SHARP LH1560F

1 SPEC No. 1 E L 0 6 Xl 0 9
I S S U E: Aug. 10. 1995
To;
SPECIFICATIONS
Model
No.
LH1560F
%This specifications
containsapages
including
the cover and appendix.
If you have any objections,please
contact us before issuing purchasing order.
CUSTOMERSACCEPTANCE
DATE:
BY:
PRESENTED
Dept. General
REVIEWED BY:
LOGIC
TENRI
SHARP
Manager
PREPARED BY:
1
LH1560F
l Handle this document carefully
for it contains material
protected
by international
full or in part, of this material
is prohibited
copyright
law. Any reproduction,
without the express written
permission
of the company.
OWhen using the products covered herein,
please observe the conditions
written
herein
and the precautions
outlined
in the following
paragraphs.
In no event shall the
company be liable
for any damages resulting
from failure
to strictly
adhere to these
conditions
and precautions.
(1) The products covered herein are designed and manufactured
for the
application
areas.
When using the products covered herein for the
listed
in Paragraph
(2). even for the following
application
areas,
Never use the
to observe the precautions
given in Paragraph (2).
for the equipment
listed
in Paragraph (3).
l Of-fice electronics
*Instrumentation
and measuring equipment
*Machine tools
*Audiovisual
equipment
*Home appliances
*Communication
equipment other than for trunk lines
following
equipment
be sure
products
(2) Those contemplating
using the products covered herein for the following
equipment which demands high reliability,
should first
contact a sales
representative
of the company and then accept responsibility
for incorporating
into the design fail-safe
operation,
redundancy, and other appropriate
measures for ensuring
reliability
and safety of the equipment
and the overall
system.
*Control
and safety devices for airplanes,
trains,
automobiles,
and other
transportation
equipment
*Mainframe
computers
*Traffic
control
systems
*Gas leak detectors
and automatic
cutoff devices
*Rescue and security
equipment
*Other safety devices and safety equipment,etc.
(3) Do not use the products covered herein for the following
equipment
which
demands extremely
high performance
in terms of functionality,
reliability,
accuracy.
*Aerospace equipment
*Communications
equipment
for trunk lines
*Control
equipment
for the nuclear power industry
*Medical
equipment
related
to life support,
etc.
(4) Please direct
all queries and comments regarding
above three Paragraphs
to a sales representative
l Please direct
representative
all queries
regarding
of the company.
the products
covered
the interpretation
of the company.
herein
to a sales
of the
or
SHARP
LH1560F
1
Contents
Page
2
. . . . . . . . . . . . ..*..................................
1. Summary
................................................
2
...........................................
3
.....................
3
.......................................
5
........................................
6. Pin Descriptions
- -....................
7. Description
of Functional
Operations
5
2. Features
3. Block
Diagram
4. Functional
5. Pin
Operations
Configuration
8. precaution
9. Absolute
. . . . . . . . . . . . . . . . . . . . . . . . . . . ..-........-.......
Maximum
10.
Recommended
11.
Electrical
13.
of Typical
and Packing
8
17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Conditions
Characteristics
of System
14. Package
Ratings
Operating
12. Example
Example
of Each Block
. . . . . . . . . . . . . . . . . . . . . . . . 18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Configuration
Characteristic
Specification
. . . . . . . . . . . . . . . . . . . . . . . . . 25
.......................
l
***......*****.*.**...
26
27
SH4RP
LH1560F
2
1. Summary
The LH1560F is a 160 output
segment/common
driver
LSI suitable
for driving
large scale dot matrix
LC panels using as personal
computers/work
stations.
Through the use of SST (Super Slim TCP) technology,
it is ideal
for
substantially
decreasing
the size of the frame section
of the LC module.
The LH1560F is good both segment driver
and common driver,
and a low power
consuming,
high-precision
LC panel display
can be assembled.
In case of segment mode. the data input is selected
4bit parallel
input mode
and 8bit parallel
input mode by a mode(MD) pin.
In case of common mode, data input/output
pins are bidirectional,
four data
shift
directions
are pin-selectable.
c
2. Features
(Segment mode)
Shift
Clock frequency
: 14 MHz (Max.)
(VoD=+5 V+lO%)
8 MHz (Max.)
(VoD=+2.5 V-+4.5 V)
9 Adopts a data bus system
4-hit/8-bit
parallel
input modes are selectable
with a mode (MD) pin
Automatic
transfer
function
of an enable signal
Automatic
counting
function
which, in the chip select
mode, causes the
internal
clock to be stopped- by automatically
counting
160 of input data
l
l
l
l
(Common mode)
Shift
clock frequency
: 4.0 MHz (Max.)
Built-in
160-bits
bidirectional
shift
register
(divisible
into 80-bits
x2)
Available
in a single
mode (160-bits
shift
register)
or in a dual mode
(80-bits
shift
register
x2)
Single
mode
0 y,
+
YlSO
l
l
l
@
y160
0
Yl
@
YlSO
The above
+
.+
+
n
YI
YSO.
y6l
YEI
l
4 shift
YIJO
-)
YlSO
+
y1
directions
Dual
mode
”
are pin-selectable
(Both segment mode and sommon mode)
Supply voltage
for LC drive
: +15.0
to +42.0 V
Number of LC drive
outputs
: 160
Low output
impedance
Low power consumption
Supply voltage
for the logic
system : +2.5 to +5.5 V
COMS silicon
gate process(P-type
Silicon
Substrate)
Package
: 186pin TCP (Tape Carrier
Not designed
or rated as radiation
hardened
l
l
l
l
l
l
l
l
Package)
LH1560F
1. Block
3
Diagram
160 Bits 4-Level Driver
A
%60
I,
I
I
I
160 Bits Level Shifter
Control
160
f-l60
Bits
Lin-
r-*-I
I=LICC
"
L/R
I
S/C
Di, Di,
1. Functional
Block
ctive
Contra
;P Conversion
L Data Contro
bata Latch
:ontrol
Operations
Di,
DI,
VOO vss vss
of Each Block
Function
In case of segment mode, controls
the selection
or deselection
of the chip.
Following
a LP signal
input,
and after the chip select
signal
is
a select
signal
is generated
internally
until
160 bits of
input,
data have been read in.
Once data input
has been completed,
a select
signal
for cascade
connection
is output.
and the chip is deselected.
In case of common mode, controls
the input/output
data of bidirectional
pins.
In case of segment mode, keep input data which are 2 clocks
of
XCK at 4-bit
parallel
mode into latch circuit,
or keep input
data which are 1 clock of XCK at 8-bit
parallel
mode into latch
circuit.after
that they are put on the internal
data bus 8 bits
at a time.
the state of the data latch
In case of segment mode, selects
which reads in the data bus signals.
The shift
direction
is
for every 16 bits of data read
controlled
by the control
logic,
signal
shifts
one bit based on the state of
in, the selection
the control
circuit.
LH1560F
latched
cotrol
Shift
Registe
state of each LC driver
logic and the data latch
4
output
control.
pin
is controlled
by the
160 bits of data are
the data latch are simultaneously
latched
on the falling
and
output
to
the
level
shifter
block.
the LP signal,
se of common mode
edge of
control
logic waits for the selection
signal
output
from the
active
control
block.
Once the selection
signal
has been output,
operation
of the data
latch and data transmission
are controlled,160
bits of data are
read in, and the chip is deselected.
In case of common mode, controls
the direction
of data shift.
SHARP
5. Pin
LH1560F
Configuration
I .
6. Pin
Descriptions
6-l.
Pin Designations
Pin No.
1
Symbol
1 to 160 1
Y,-Ylcn
161,
162,
163,
165
166
167
168
169
Chip Surface
to
176
177
178
179
180
181
182
164,
) I/O 1
Designation
1 0 1 LC drive outnut
186
VO~, V,,R
Power supply for LC drive
Power supply for LC drive
185
V,~L.
VlZR
Power supply for LC drive
184
Vd3L, v43R
I
Display
data shift
direction
selection
L/R
V
Power supply for logic
system(+2.5
to +5.5
V)
s"/;
I
Segment mode/common mode selection
EI02
I/O
Input/output
for chip select
or data of shift
register
175
DIO-D18
I
Display
data
input for segment mode
I
Display
data input for Segment mode/
DI7
Dual mode data input
XCK
Display
data shift
clock input
for segment mode
.I
DISPOFF
I
Control
input for deselect
output
level
LP
I
Latch pulse input/shift
clock input for shift
register
EIO,
I/O
Input/output
for chip select
or’data
of shift
register
FR
I
AC-converting
signal
input
for LC drive waveform
MD
I
Mode selection
input
Vss
183
Ground( 0 V)
5
LH1560F
6-2.
Input/Output
6
Circuits
Input
Signal
[Applicable
pins]
L/R,S/C.DIo-DIB,
DISPOFF.LP,FR.MD
Fig.1
Input
Circuit(l)
Input
[Applicable
D17 ,XCK
Fig.2
Input
Circuit(2)
Signal
pins]
LH1560F
Input
Signal
Output
Signal
Control
Signal
[Applicable
EIO, .EIO:!
Fig.3
Control
Signal
Input/Output
Circuit
3
Control
V43
Signal
4
Vss
[Applicable
Yl
Fig.4
p ins]
LC Drive
Output
Circuit
to
Y160
pins]
a
LH1560F
7. Description
of Functional
Operations
7-l.
Pin Functions
(Segment mode)
the bias
-To further
voltage
used is set
reduce the difference
pins Y, and Yteo,
mode,
DISPOFF
FR
MD
between
externally
input
data
by a resistor
the output
connect
into
divider.
waveforms of LC
ViR and Vi,.
the 4 pins
DI,,-D13.
ic voltage
level
to LC
drive voltage
level.and
controls
LC drive circuit.
*When set to VSS level
“L”. the LC drive output
pins (Y1-Yleo)
are
set to level Vss .
*While
set to “L”,the
contents
of the line latch are reset.but
read
the display
data in the data latch regardless
of condition
of
DISPOFF. When the DISPOFF function
is canceled.the
driver
outputs
deselect
level
(V,, or V,,),then
outputs
the contents
of the date
latch on the next falling
edge of the LP. That time,if
DISPOFF
removal
time can not keep regulation
what is shown AC
characteristics
(Page 2l).can
not output
the reading
data correctly.
AC signal
input for LC driving
waveform
*The input signal
is level-shifted
from logic voltage
level
to LC
drive voltage
level,and
controls
LC drive circuit.
l Normally.inputs
a frame inversion
signal.
*The LC driver
output
pin’s
output
voltage
level can be set using
the line latch output
signal
and the FR signal.
Table of truth values
is shown in 7-2-l.
Mode selection
pin
*When set to Vss level
“L”, 4-bit
parallel
input mode is set.
*When set to VDo level
“HI’, g-bit
parallel
input mqde is set.
*The relationship
between the display
data and driver
output
pins is
shown in 7-2-2.
SHARP
EIO,
EIOp
yI-ylso
LHl560F
*When set to VDD level
‘H”.segment
mode is set.
Input/Output
pin for chip selection
*When L/R input is at VSS level “L”, EIO, is set for output,
and EIO:
is set for input.
*When L/R input is at Voo level
“H”, EIO, is set for input,
and EIOz
is set for
output.
*During
output.
set to “H” while LP*E
is “H” and after
160-bits
of
data have been read, set to “L” for one cycle (from falling
edge to
falling
edge of XCK). after which it returns
to “H”.
*During
input.
after
the LP signal
is input,
the chip is selected
while EI is set to “L”. After
160-bits
of data have been read, the
chip is deselected.
LC driver
output
pins
*Corresponding
directly
to each bit of the data latch,
one level
or
VSS>
is
selected
and
output.
(Vo. VIZ? v43*
Table of truth values is shown in 7-2-l.
the bias voltage
used is set by a resistor
divider.
V~~R.V,~~
*Normally.
V43L *Ensure
that voltages
are set such that VSS<V43<V,z<Vo.
v43R*
*To further
reduce the difference
between the output
waveforms of LC
driver
output
pins Y, and YIBo, externally
connect ViR and V,L
(i=O.
12, 43).
EIO,
Bidirectional
shift
register
shift
data input/output
pin
*Output
pin when L/R is at VSS level
“L”. input pin when L/R is at
VDo level
“H”.
*When EIO, is used as input pin, it will
be pull-doen.
I
-When EIO, is used as output
pin,it
won’t be pull-down.
EIOz
Bidirectional
shift
register
shift
data input/output
pin
*Input
pin when L/R is at VSS level
“L”. output
pin when L/R is at
VDD level
“H”.
*When EIOz is used as input pin, it will
be pull-down.
*When EIOp is used as output pin, it won’t be pull-down.
LP
Bidirectional
shift
register
shift
clock pulse input pin
*Data is shifted
on the falling
edge of the clock pulse.
Bidirectional
shift
register
shift
direction
selection
pin
L/R
*Data is shifted
from Ylso to Y, when set to VSS level
“L”. and data
is shifted
from Y, to Ytso when set to VDo level
“H”.
r
9
LH1560F
DISPOFF
FR
ND
DI7
s/c
DI,,-DIG
XCK
YI-Ylso
Control
input pin for output
deselect
level
*The input
signal
is level-shifted
from logic
voltage
level
to LC
drive voltage
level.and
controls
LC drive circuit.
*When set to Vss level
“L”, the LC driver
output
pins (Yi-Ylso)
are
set to level
Vss.
*While
set to “L”,the
contents
of the shift
resister
are reset not
reading
data. When the DISPOFF function
is canceled,
the driver
outputs
deselect
level
(VIZ or Vd3), and the shift
data is reading
on the falling
edge of the LP. That time,if
DISPOFF removal
time
can not keep regulation
what is shown AC characteristics
(Page 24).
the shift
data is not reading
correctly.
AC signal
input for LC driving
waveform
*The input signal
is level-shifted
from logic
voltage
level
to LC
drive voltage
level.and
controls
LC drive circuit.
.Normally.
input a frame inversion
signal.
*The LC driver
output
pin’s
output voltage
level
can be set using
the shift
register
output
signal
and the,FR signal.
Table of truth
values
is shown in 7-2-l.
Mode selection
pin
*When set Vss level
“L”, Single
Mode operation
is selected,
when set
level
“H”,
Dual
Mode
operation
is
selected.
to voo
Dual Mode data input pin
*According
to the data shift
direction
of the data shift
register,
data can be input
starting
from the 81st bit.
When the chip is used as Dual Mode, D17 will
be pull-down.
When the chip is used as Single
Mode, DI, won’t pull-down.
Segment mode/common
mode selection
pin
*When set to Vss level
“L”, common mode is set.
Not used
*Connect
DIO-D16 to Vss or Voo. Avoiding
floating.
Not used
l XCK is pull-down
in common mode, so connect to Vss or open.
LC driver
output
pins
*Corresponding
directly
to each bit of the shift
register,
one level
)is
selected
and
output.
(Vo,
Viz.
V43,
or
Vss
Table of truth
values
is shown in 7-2-l.
LH1560F
7-2.
7-2-l.
Functional
Truth
(Segment
Operations
Table
Mode)
(Common Mode)
(Note]There
are two kinds of power supply (logic
level voltage,
LC drive
voltage)
for LCD driver,
please supply regular
voltage
which assigned
by specification
for each power pin.
That time “Don’t
careV should be fixed to ‘H” or “L”, avoiding
floating.
11
LH1560F
7-2-2.
Relationship
(Segment
(a) 4-bit
L
H
(b)
I
I
the Display
Data and Driver
Output
pins
Mode)
Parallel
Input-Output
a-bit
I
between
12
Parallel
I
node
I
DIo
YISO
YISB
y152
*-
Y 12
y
6
y
4
DII
Y159
Y155
Y,5,
-.
Y,,
y
7
y
3
D12
Ylse
Y154
y150
..
ylo
DI3
y157
y153
yl49
-.
Y
g
I lJl7
I
I
1 y B
)
I
rsn
. .
I
..
1 rl4l
rldn
Here,
[Note]
L:Vs5(0
“Don’t
L/R
y
1
1’48
1 r14g
y14
Y22
. .
y142
y150
Y 15
y23
. .
y143
y151
y 8
Yl6
y2
. .
Y 144
yl52
DIo
yieo
Y 152
y144
-*
y2
DII
Y159
y151
Y 143
--
Y 23
Y 16
Y 15
DI6
y
DI7
7
4
4
(Common Mode)
MD
y 2
5
1
Mode
DIs
I
y 6
y
Data Transl
V). H:VDD(+2.5V
to +5.5 V). x:Don’t
Care
care” should be fixed to “H” or “L”, avoiding
floating.
Yl56
1 Y 157
1
Y 156
Y 159
Y 160
y
6
Y
7
SHARP
13
LHl560F
7-2-3.
Connection
Examples
of Plural
Segment
Drivers
(a) Case of L/R=‘L”
last
top data
i/’.;
(data
taking
data
flow)
ii,.’
:;
YISO BY,
XCK
LP
MD
FR
DIo-Dr.7
vss
(b) Case of L/R=“H”
VDO
1
I
IDIo-DI,
FR
MD -/..
LP
XCK
I
_.._.......
i-l
. . .. . __..
_.__._.._
._..._.....
n
a
4
I
g
-0s
27”
g7
vss
8
/
I
w-2
-
I
L/R
EIO,
Y1 -y,eo
..f.,
‘j’ (data
top data
EIOz
n
=
ISE
L/R
> EIOl
Y* -----+Y*so
taking
x
-p:naY
,-cz.s
2:‘:
“5:
L/R
EI& - ___________
+
EI(),
EIOz
YI -----+YlSO
,./:
flow)
last
data
LH1560F
7-2-4.
Timing
Chart
of 4-Device
cascade
Connection
of Segment
Drivers
FR
l-l
l-l
LP
J-ulnrL
....--.nJlnl-L
.-..-.-..
J-uln-n
....-..
JUULI-L..
....-nnnrt
XCK
DIo-DI7
._......._.....
K
EI
(device
II
device
A
I/
device
B
II
device
C
device
D
>I
H
L
A)
EO
(device A)
EO
(device B)
EO
(device C)
(*I
n: 4-bit
&bit
parallel
para llel
mode 40
mode 20
LH1560F
7-2-5.
Conection
Examples
for
i
Fig.1
vss&os,
_-
Common Drivers
!
FR
FR
DISPOFF
VDD
V
Plural
15
Single
Mode (Shifting
I
toward left)
=
I
I
_
I 1
T
Fig.2
Single
Mode (Sifting
-I I I
toward right)
LH1560F
Last1 First2
First1
+,
Last2
p-Lid-&
T
DIl
-
VDD
Y160
rLs
Yl
23 EIO,
I
I
1 1
Vss
DISPOFF
FR
Fig. 3 Dual hfode (Shifting
EIO,i=
1
First
toward left)
EIOz
Last1 First2
Fig.4
Dual Mode (Shifting
La&2
toward right)
I
SHARP
LHl560F
17
8. Precaution
OPrecaution
when connecting
or disconnecting
the power
This LSI has a high-voltage
LC driver,
so it may be permanently
damaged by
a high current
which may flow if a voltage
is supplied
to the LC driver
power supply while the logic
system power supply is floating.
The detail
is as follows.
*When connecting
the power supply,
connect the LC drive
power after
connecting
the logic
system power. Furthermore.
when disconnecting
the
the logic
system power after disconnecting
the LC drive
power, disconnect
power.
*We recommend-you
connecting
the serial
resistor(50-100
Q) or fuse to the
LC drive
power V0 of the system as a current
limitter.
And set up the
suitable
value of the resistor
in consideration
of LC display
grade.
And when connecting
the logic power supply,
the logic
condition
of this LSI
inside
is insecurity.
Therefore
connect
the LC drive
power supply
after
resetting
logic condition
of this LSI inside
on DISPOFF function.
After
that,
cancel
the m
function
after
the LC drive
power supply
has become
stable.
Furthermore.
when disconnecting
the power, set the LC drive
output
pins
to level
Vss on DISPOFF ‘function.
After
that,
disconnect
the logic
system
power after
disconnecting
the LC drive power.
When connecting
the power supply,
show the following
recommend sequence.
VDD
vo
V-I
\
SHARP
LH1560F
9. Absolute
Maximum
I IInput
Ratings
ISymbol/
Parameter
I
I
Condi t
voltage
IDIo-,
10. Recommended
L
[Note]Ensure
ihat
18
Operating
I
voltages
.XCK.LP
I
Conditions
are
set
such that
Vss<V43<V12
SHARP
LHl560F
11. Electrical
11-l.
19
Characteristics
DC Characteristics
(Segment
[Note]
*l VDo=+5.0
*2 VDo=+5.0
The input
*3 vDo=+5.0
The input
*4 VoD=+5.0
The input
Mode)
(Vss=O v, VDD= +2.5
V, V0=+42.0 V,
V. V,,=+42.0 V.
data is turned
v. V,,=+42.0 V.
data is turned
V. V0=+42.0 V.
data is turned
V to +5.5
V, V,,=+15.0
V,=Vss
fxcK=14 MHz. No-load,
over by data taking
fxcK=14 MHz. No-load.
over by data taking
fxcK=14 MHz, fLr=41.6
over by data taking
to +42.0
V, Ta=-20
EI=Voo
clock(4-bit
Parallel
input
EI=Vss
clock(4-bit
parallel
input
kHz. fFR=80 Hz, No-load
clock(4-bit
parallel-input
to +85 t)
mode)
mode)
mode)
LH1560F
(Common Mode)
(Vss=O V, Voo=+2.5
IInput
^
. . -
^
V to +5.5
20
V. V ,,=+15.0
to +42.0
V. Ta=-20
to +85 “c)
leakage
^
^
l
I LIL
Input
Icurrent
pull-down
Output
I Ip D
I -
resistance
Ro N
current
1 IS - l-0
(Stand-by
}W
v,=vss
VI=VDD
DIo-, ,XCK,LP.L/R
FR.HD.S/C.EIO,
EIOz ,DISPOFF
XCK.EIO, , I3102
nT
0.7
1.0
4 c
D
*1
vDD=+5.0
*2
VDD
=+5.0
case of
V, V,,=+42. TiV, Vo=+42.0 V. fLp=41.6
kHz,
l/480 duty operation.
No-load
fFR=80
Hz
-10.0
PA
100.0
VA
1.0
1.5
el n
kS
LH1560F
11-2.
AC Characteristics
(Segment
Hode 1)
(vss=O V, VoD=+4.5
Parameter
pulse width
“L” pulse width
Data setup time
Data hold time
Latch pulse YH” pulse width
Shift
clock rise to
Latch pulse rjse. time
Shift
clock fall
to
Latch pulse fall
time
Latch pulse rise to
IShift
clock rise time
Latch pulse fall
to
Shift
pulse fall
time
Input signal
rise time *2
Input signal
fall
time *2
Enable setup time
DISPOFF removal
time
DISPOFF yL” nulse width
lOutnut delay time (1)
Output delay time (2)
Output delay time (3)
V to +5.5 V, V,,=+15.0 to +42.0
Symbol
, Co1edition
1 Min.
t,,t,SlO
ns 1 71
twclc
twrau
23
1 twcKI.
or-1 231
10
tos
20
tDH
23
tWLpH
V, Ta=-20 to +a5 “cl
) Typ. ) Max. 1 IJq
1
ns
1
I ns
I
irns
ns
ns
ns
0
ns
tLD
tSL
25
ns
tLS
25
ns
I
I
tLII
I
I
25
I
I
t,
tf
ts
1
I
tSD
tWDL
I tD
1 t pdl.
1 t vd3
I
ns
ns
ns
ns
ns
I
us
50
50
1 c~=15
t
pd.2
1
c~=15
1 CL=15
DF
21
100
1.2
1
1
I
1
PF
pF
I
1
I
[Note]
*l Take
the cascade connection
into consideration.
is maximum in the case of high
*2 (tCK-tNCKII -tWCKL)/2
speed
operation.
40
1.2
1.2
I
I ns I
1
I
ps
!.ls
LHl560F
(Segment
Mode 2)
(Vs s =0 V, v00=+2.5
Data setup time
Data hold time
Latch pulse “H” pulse
Shift
clock rise to
Latch pulse rise time
Shift
clock fall
to
Latch pulse fall -time
Latch pulse rise to
Shift
clock rise time
Latch pulse fall
to
Shift
pulse fall
time
[Noie]
*l Take
*2
V to +4.5
V. V0=+15.0
to +42.0
30
tos
t DH
width
22
I
tWLPH
40
51
V. Ta=-20
1
I
II
II ns
~~~ I
I ns
ns
ns
9
0
tLD
to +85 “c)
tSL
51
ns
tLS
51
ns
t L II
I
w
I
Ins/
I
the cascade
(tCK-tWCKII-t*CKL
connection
into consideration.
)/2 is maximum in the case of high
speed operation.
1
(Timing
characteristics
of Segment
Mode)
LP
LP
EO
(*) n :4-bit
parallel
parallel
a-bit
mode 40
mode 20
FR
<
>
LH1560F
(Common Mode)
vss =O v, vDo=+2.5
to +5.5
24
V. v0=+15.0
to +42.0
Data setup time
Data hold time
Input signal
rise time
Input signal
fall
time
DISPOFF removal
time
DISPOFF yL” pulse width
Output delay time(l)
Output delay time(2)
OutDut delay time(3)
I
(Timing
V-.+4.5
tWDL
t DL
t udl* tpd2
tads
CL=15 pF
CL=15 pF
c~=15
DF
tWLP
>
<
7.
LP
F
4
tr
_
tWLPH
t-t
_
EI02
01,)
tDL
<
z
EIO,
tWDL
d
DISPOFF
FR
LP
<
t.as
>
Yl-YIGO
3:
[L/R=“L”]
I
US
200
1.2
1.2
of Common Mode)
G
ns
ns
ns
ns
I nsl
501
nsl
50
ns
ns
I
30
100
1.2
tSD
Characteristics
V
30
50
tsu
t&l
tr
tr
to +a5 t)
1 2501
15 I
,
VoD=+2.5
V, Ta=-20
ns
us
us
SHARP
LH1560F
12 . Example
of System
25
Configuration
SEGs4c
SEGssr
FR
.Lp
-DISP
OFF
-XCK
-@a
!j $
SEC2
SEC,
::7-v
. . .... . .._.........~......................................................~...~....
___.__..._.._...
z E
Y,-YISO
I I
Y,-Y160
I I
YI-Ylso
I I
k
i
II
EIO,
YF
C
f:R
DIo-DI7
EI02-j
LHl560F
13. Example
of Typical
Characteristic
Parameter
Typical
Fundamental
Rating
Propagation
Delay Time
Ta=+25
Conditions
C, VSS=O V, VDo=+5.0
Min.
V
Typ.
10
Max.
Unit
ns
14. PACKAGE AND PACKING
LH 1560F
SPECIFICATION
27
1
1. Package Outline Specification
Refer to drawing No. SPN3321-00
2. Markings
The meanings of the device code printed on each tape carrier package are as follows.
(1) Date code
(example)
: ---4 4 3
a> b)
a) denotes the last figure of Anno
b) denotes the week (of production)
c) denotes the number of times of
0
c)
Domini (of production)
alteration
3. Packing Specifications
ntt-stattc treate
nti-static treate
(2) Packing Form
* Specification of label
a) Tape carrier package(TCP)is wound on a reel
with separators 1 and 2 and the ends of them
are fixed with adhesive tape.
b) A label indicating production name, lot no.
TYPE
RODUCTION
NAME
and quantity is stuck on one side of the reel.
c) The reel and silica gel is put in a laminated
aluminium bag. Nitrogen gas is enclosed in
2UANTITY 1 QUANTITY
1
the bag and the bag is sealed. The same
label(b) is affixed to the bag. The bag is put
LQT(DATE)/ SHIPPING DATE 1
in a carton and the same label(b) is affixed
to one side of the carton.
4. Miscellaneous
(1) The length of the tape carrier is 34-46 meters maximum per reel, and depends
on shipping quantity.
(2) Before unpacking, prepare a work bench equipped with anti-static devices.
Also, the operater shoud ware anti-static wrist bands.
(3) The device, once unpacked, should be stored in a nitrogen gas, room temperature
atomosphere and used within 1 week.
4
DESIGN
(NOTE)
/’
4’
,’
,’
,<----__
-’