TC94A23F Toshiba CMOS Digital Integrated Circuit Silicon Monolithic TC94A23F Single-chip CD Processor with Built-in Controller TC94A23F is a single-chip CD processor for digital servo. It incorporates a 4-bit microcontroller. The controller features an LCD/LED driver, 4-channel 6-bit AD converter, 2/3-line serial interface, buzzer, interrupt function, and 8-bit timer/counter. The CPU can select one of three crystal oscillator operating clocks (16.9344 MHz, 4.5 MHz, and 75 kHz), facilitating interface with the CD processor. The CD processor incorporates sync separation protection and interpolation, EFM decoder, error correction, digital equalizer for servo, and servo controller. The CD processor also incorporates a 1-bit DA converter. In combination with RF amp TA2153FN or TA2109F, TC94A23F can very simply configure an Weight: 1.6 g (typ.) adjustment-free CD player. Thus, the IC is suitable for CD systems for automobiles and radio-cassette players. Features · · Single-chip CD processor with built-in CMOS LCE/LED driver and 4-bit microcontroller Operating voltage: At CD on: VDD = 4.5 to 5.5 V (typ. 5.0 V) · Current dissipation: At CD off: VDD = 3.0 to 5.5 V (only CPU on) At CD on: IDD = 50 mA (typ.) At CD off: IDD = 2 mA (with 4.5 MHz crystal oscillator, only CPU on) At CD off: IDD = 0.3 mA (with 75 kHz crystal oscillator, only CPU on) · · Operating temperature range: Ta = -40~85°C Package: QFP100-P-1420-0.65A (0.65-mm pitch, 2.7-mm thick) · One-time PROM version: TC94AP09F 1 2002-02-06 TC94A23F 4-bit Microcontroller · · · · · · · · · · · · · · · Program memory (ROM): 16-bit ´ 8k-step Data memory (RAM): 4-bit ´ 512-word Instruction execution time: 1.89/1.78/40 ms (all one-word instructions) Crystal oscillator frequency: 16.9344 MHz/4.5 MHz/75 kHz Stack level: 8 AD converter: 6-bit ´ 4-channel LCD driver: 1/4 duty, 1/2 or 1/3 bias method, 72 segments max LED driver: 4-digit ´ 14-segment (max), also used as LCD driver switched by software I/O port: CMOS I/O port: 16 N-channel open drain I/O port: 4 (max) Output-only port: 4 (max), also used as CD processor pins Input-only port: 4 Timer/counter: 8 bit (INTR, instruction cycle, 100/1 kHz selectable as timer clock) 10, 100, or 500 Hz: internal port 2 Hz: Flip-flop port Serial interface: Supports 2/3-line method (data length: 4 or 8 bits) Buzzer: Four types: 0.75, 1, 1.5, and 3 kHz Four modes: Continuous, Single-Shot, 10 Hz Intermittent, and 10 Hz Intermittent at 1 Hz Interval) Interrupt: 1 external, 3 internal (CD sub-sync, serial interface, 8-bit timer) Back-up mode: three types Clock Stop (crystal oscillator off) Hardware Wait (crystal oscillator on but CPU in operation) Software Wait (CPU in intermittent operation) Reset function: Power-on reset, built-in supply voltage detector (detection voltage = 2.5 V typ.) CD Processor · · · · · · · · · · · · · · · · · · · · · Reliable sync pattern detection, sync signal protection and interpolation Built-in EFM decoder and sub code decoder High-correction capability using cross interleave read Solomon code (CIRC) logical equation C1 correction: dual C2 correction: quadruple Supports variable speeds. Jitter absorption capability of ±6 frames Built-in 16 KB RAM Built-in digital output circuit Built-in L/R independent digital attenuators Bilingual audio output (Note) Sub code Q data are read-timing free and can be output in sync with audio data. (Note) Built-in data slice and analog PLL (adjustment-free VCO used) circuit Auto adjustment of loop gain, offset, and balance at focus servo and tracking servo RF gain auto adjustment circuit Built-in digital equalizer for phase compensation Supports different pickups using built-in digital equalizer coefficient RAM. Built-in focus and tracking servo control circuit Search control supports all modes and realizes high-speed, stable search. Lens kick and feed kick use speed control method. Built-in AFC circuit and APC circuit for disc motor CLV servo. Built-in defect/shock detector Built-in 8 times oversampling digital filter and 1-bit DA converter. Note: Output pins for sub code Q data and audio data are also used as LCD driver pins. The function of the pins can be switched by program. 2 2002-02-06 TC94A23F VSS VDD SEL 2VREF DMO FMO TEBC RFGC VREF TRO FOO TEZI TEI SBAD FEI RFRP RFZI RFCT AVDD RFI SLCO AVSS VCOF PVREF LPFO LPFN M XVSS XI XO XVDD Pin Connections M * 3 * 3 * 3 * R * 3 * 3 * 3 * 3 * R * A * A * A * A * A * A * A * A * A * 3 * A * A * 3 * A * R * A * A 80 DVSR * M 75 70 65 60 55 51 50 3 * TMAX CD processor input/output 81 3 * PDO RO * DVRR * R R * P2VREF DVDD * M M * VSS 85 M * V DD 45 LO * * SBOK DVSL * M TESTM IN2/(VPP) * SBSY M Controller test input * DOUT M M * OT22 (COFS) 90 Reset input RST M HOLD M Hold input INTR M Interrupt input MXO M M * OT21 (SPDA) TC94A23F (QPF100 pin) 40 M * OT20 (SPCK) M * OT19 ( HSO ) CD test input M TESTC M IN1 (BCKin) M P2-3 (DATAin) OSC MXI M MVSS M MVDD M 35 M P2-2 (LRCKin) COM1 (OT1) M M P2-1 ( HSO in) COM2 (OT2) M M P2-0 (EMPHin) COM3 (OT3) M M P4-3 (SCK/SCL) COM4 (OT4) M 100 95 Power supply to controller LCD driver/LED driver output port (LCD: 4 ´ 18 = 72 segments max, LED: 18 segments) M M M M M M M M M M M M M P1-3 P3-0 P3-1 (ADin1) P3-2 (ADin2) P3-3 (ADin3) P4-0 (ADin4/BUZR) P4-1 (SI2) S10 (OT14/ZDET) M P1-2 S9 (OT13) M P1-1 S8 (OT12) M P1-0 S7 (OT11) P4-2 (SI0/SI1/SDA) 30 M MVSS S6 (OT10) 25 M MVDD S5 (OT9) 20 M P8-3 (OT18/IPF) S4 (OT8) 15 M P8-2 (OT17/MBOV) M P8-1 (S16/AOUT) M P8-0 (S15/BCK) M S14 (OT18/LRCK) M S13 (OT17/SFSY) M I/O ports (16) S12 (OT16/DATA) M 31 M S11 (OT15/CLCK) M S3 (OT7) 10 M S2 (OT6) 5 M S1 (OT5) 1 M Power supply to controller CD function pins switched DVRL * R CD function pins switched together Note: Note: Symbols used for the pins above indicate the following pin functions. * : CD processor-dedicated pin M : Power supply pin 3 : CD processor tri-state output pin A : CD processor analog input/output pin R : Reference input pin M : Controller-dedicated pin When the CD is off, the power supply pins for the controller (MVDD) and the power pins supply for the CD oscillator (XVDD) are on and the CD processor-dedicated power supply pins (indicated by asterisk *) are off. 3 2002-02-06 TC94A23F AVSS AVDD RFCI RFZI RFRP FEI SBAD TEI TEZI FOO TRO VREF RFGC TEBC FMO DMO 2VREF SEL Block Diagram VREF Clock gene. XVSS X’tal OSC PWM XI XO DA VREF CD clock Data RFI slicer SLCO PLL TMAX XVDD ZDET DVSR SERVO control RO TMAX AD PDO VREF LPF 1 bit DAC DVRR DVDD P2VREF VCOF DVRL LO ROM Digital equalizer RAM Automatic adjustment circuit VCO PVREF CLV servo LPFO Synchronous guarantee EFM decode DVSL Sub code decoder LPFN VDD Audio out 16 k SRAM Digital out VSS P2-0~P2-3 IN1 Address SBOK CD Reset Correction circuit SBSY DOUT OT22 (COFS) MXO X’tal OSC MPX Reset Micon interface MXI OT21 (SPDA) P1-3 Port1 OT19-22 SBSY CPU clock OT20 (SPCK) CLCK, DATA, SFSY, LRCK, BCK, MBOV, IPF P1-0 OT19 ( HSO ) Timer HOLD Data Reg (16 bit) SBSY G-Reg. Interrupt INTR Cont. Serial R/W Buf. TESTM TESTC ROM (16 ´ 8192 Step) IN1 (BCKin) RAM Interface ALU (4 ´ 512 word) IN2 P4-3 (SCK/SCL) P4-2 (SI0/SI1/SDA) Port4 P2-0 (EMPHin) Program P4-0 (ADin4/BUZR) Instruction Counter Port2 P4-1 (SI2) Decoder F/F Reset Stack Reg. Conv. (8Level) P2-2 (LRCKin) P2-3 (DATAin) BUZR AD P2-1 ( HSO in) RST Power on Reset P3-3 (ADin3) P3-2 (ADin2) Port3 P3-1 (ADin1) Bias ZDET, CLCK, DATA, SFSY, LRCK, BCK, MBOV, IPF MVDD P3-0 4 MVSS P8-3 (S18/IPF) P8-2 (S17/MBOV) P8-1 (S16/AOUT) P8-0 (S15/BCK) S14 (OT18/LRCK) S13 (OT17/SFSY) S12 (OT16/DATA) Port8 S11 (OT15/CLCK) S10 (OT14/ZDET) S2 (OT6) S1 (OT5) COM4 (OT4) COM3 (OT3) COM2 (OT2) COM1 (OT1) LCD Driver/Output Port 2002-02-06 TC94A23F Pin Function Pin Number Symbol Pin Name Function and Operation Remarks Common signal output pins for the LCD panel. 97 COM1/OT1 98 COM2/OT2 99 COM3/OT3 100 COM4/OT4 Those pins configure matrix with S1 to S18 and display up to 72 segments. The LCD can be driven by the 1/2 or 1/3 bias method. When the 1/2 bias method is set, three levels, MVDD, 1/2MVDD, and GND, are output at 2-ms intervals at a 62.5 Hz cycle. When the 1/3 bias method is set, four levels, MVDD, 1/3MVDD, 2/3MVDD, and GND, are LCD common output output at 1-ms intervals at a 125 Hz cycle /output port (when either the 4.5 MHz or 75 kHz crystal oscillator is used). MVDD MVDD Bias voltage After system reset or clock stop execution is released, the non-selected waveform (bias voltage) is output. The DISP OFF bit is set to 0 and the common signal is output. These pins can be switched to an output port (Note 1) or LED driver pins by program. They are usually used for digit output to drive the LEDs. 5 2002-02-06 TC94A23F Pin Number Symbol Pin Name Function and Operation Remarks Segment signal output pins for the LCD panel. Those pins configure a matrix with COM1 to COM4 and display up to 72 segments. 1~9 10 S1/OT4 ~ S9/OT13 S10/OT14 /ZDET 11 S11/OT15 /CLCK 12 S12/OT16 /DATA 13 S13/OT17 /SFSY 14 S14/OT18 /LRCK MVDD MVDD Bias voltage When the 1/2 bias method is set, two levels, LCD segment output MV DD and GND, are output. When the 1/3 /output port bias method is set four levels, MVDD, 1/3MVDD, 2/3MVDD, and GND, are output. The S1 to S14 pins can be switched to an output port (Note 1) by program. Port 8 and S15 to S18 pins can be switched pin by pin to an I/O port and segment output pins. When the pins are set to an I/O port, output is N-channel open drain. The S10 to S14 and P8-0 to P8-3 pins can be switched to CD signal input/output pins by program. Setting the CD10 bit to 1 switches the pins to the LRCK, BCK, and AOUT pins as the CD pins in batches. The other pins can be individually switched according to the S14/S15/S16 segment data. LCD segment output CLCK: Inputs/outputs sub code P to W data reading clock. /output port /CD signal DATA: Outputs sub code P to W data. MVDD SFSY: Outputs frame sync signal for playback. LRCK: Outputs channel clock (44.1 kHz). When L channel, outputs Low. When R channel, outputs High. The polarity can be inverted by command. BCK: Outputs bit clock (1.4112 MHz). MVDD AOUT: Outputs audio data. 15 P8-0/S15 /BCK MBOV: Outputs buffer-memory-overflow signal. When buffer memory overflows, outputs H. IPF: 16 P8-1/S16 /AOUT 17 P8-2/S17 /MBOV 18 P8-3/S18 /IPF MVDD Outputs interpolation pointing flag. If AOUT output is C2 error detection/correction, outputs High to indicate correction is impossible. Input instruction Bias voltage I/O port ZDET: Outputs 1-bit DAC zero detection flag. /LCD segment output Pins set as an output port are used for /CD signal segment output for the LED driver. The output port can increment OT1 to OT18 by instruction, facilitating access to data in external RAM and ROM. (Note 1) After a system reset, pins also used as output ports are set to LCD output; pins also used as I/O ports are set to I/O port input. 6 2002-02-06 TC94A23F Pin Number Symbol Pin Name Function and Operation Remarks MVDD MVDD 4-bit CMOS I/O port. Input/output can be set for each bit by program. 21~24 P1-0~P1-3 I/O port 1 The pins can be set to be pulled-up or pulled-down by program. Thus, they can be used as key input pins. When the pins are set to I/O port input, Clock Stop mode and Wait mode can be released, according to the change in input to the pins. RIN1 MVDD 5-bit CMOS I/O port. Input/output can be set for each bit by program. 25 26~28 P3-0 P3-1/ADin1 ~ P3-3/ADin3 I/O port 3 I/O port 3 /A/D analog voltage input P3-1 and P4-0 pins are also used as built-in 6-bit 4-channel A/D converter analog input pins. The P4-0 pin is also used as the buzzer output pin. 29 P4-0/ADin4 /BUZR I/O port 4 /A/D analog voltage input/buzzer output MVDD The built-in A/D converter uses successive approximation. The conversion time is 6 instruction cycles (280 ms) when the 75 kHz crystal oscillator is used; 198 ms when the 4.5 MHz crystal oscillator is used; 180 ms when the 16.9344 MHz crystal oscillator is used. A/D analog input can be set for each pin by program. The internal power supply (MVDD) is used as the reference voltage. To A/D converter Input instruction One of four frequencies: 0.75, 1, 1.5, and 3 kHz, can be selected for buzzer output. The buzzer is output at the selected frequency in one of four modes: Continuous, single-shot, 10 Hz intermittent, and 10 Hz intermittent at 1 Hz interval. Settings for the A/D converter and buzzer, and their control can be performed by program. 33 P2-0/EMPHin MVDD 34 P2-1/ HSO in I/O port 2 /1-bit DAC input I/O port 2 is a 4-bit CMOS I/O port. 35 P2-2/LRCKin IN1 and IN2 are a 2-bit general-purpose input port. 36 P2-3/DATAin Input/output can be set for each bit of I/O port 2 by program. 37 I/O port 2 and the IN1 pins can be switched to 1-bit DAC input pins by the CD command to support shock-proofing. In this case, the I/O port must be set to input. IN1/BCKin General-purpose input port/1-bit DAC input (VPP input) 89 MVDD MVDD With the OTP version, the IN2 pin is also used as the program power supply pin. IN2/ (VPP) 7 2002-02-06 TC94A23F Pin Number Symbol Pin Name Function and Operation Remarks 3-bit CMOS I/O port. Input/output can be set for each bit by program. 30 31 32 P4-1/S12 P4-2 /SI0/SI1/SDA P4-3 /SCK/SCL I/O port 4/serial data These pins are also used as serial interface input (SIO) circuit input/output pins. /serial data input/output /serial clock input/output SIO is a serial interface supporting 2-line and 3-line methods. Starting from the MSB or LSB, 4 or 8-bit serial data are output to the SO/SDA pin, or data on the SI1 and SI2 pins are input to the device at the clock edge on the SCK/SCL pin. As the serial operating clock (SCK/SCL), an internal (450/225/150/75 kHz) or external clock can be selected. Rising or falling shift can also be selected. The clock and data output can be N-channel open drain. These selections facilitate controlling the LSI and communications between the controllers. When SIO interrupts are enabled, an interrupt is generated as soon as execution of the SIO completes, and the program jumps to address 4. This is effective for performing serial communications at high speed. MVDD Input instruction + SI0ON All SIO inputs incorporate a Schmidt circuit. SIO and its control can be set by program. 38 Test mode control input 88 MVDD Input pins for controlling Test mode. TESTC When the pins are at High level, the device is in Test mode; at Low level, in normal operation. Normally, set the pins to Low level or NC (pull-down resistors are incorporated). TESTM RIN2 4-bit general-purpose output port. After system reset, the pins are set to a Low-level output port. The pins can be switched to CD control output pins by program. Setting OT19 to OT22 to 0 switches all four pins to CD control output pins. Setting OT19 to OT22 and CDIO to 1 enables the pins to be switched as follows according to the segment data contents of the S15 and S16 pins: OT19/ HSO OT20/SPCK 39~42 OT21/SPDA OT22/COFS Output port/CD control signal output MVDD HSO : Outputs playback speed mode. Normal speed: High Double speed: Low SPCK: Outputs clock for reading processor status signal (176.4 kHz). APCK: Outputs clock for reading processor status signal. SPDA: Outputs processor status signal. COFS: Outputs frame clock for correction (7.35 kHz). 8 2002-02-06 TC94A23F Pin Number Symbol 43 DOUT 44 SBSY 45 SBOK Pin Name Function and Operation Remarks Digital output in. VDD Sub code block sync output pin. When sub code sync is detected, outputs High at the S1 position. Sub code Q data CRCC result output pin. When the result is OK, outputs High. 46, 75 47, 76 48 VDD VSS P2VREF Power supply pins for CD digital block. Normally, 5 V is applied. VDD When CD is not used (CD off), the power supply can be set to off except to the controller, enabling only the controller to operate. At this time, 1 must be set in the CDoff bit. If pins from 11 to 18 and 39 to 42 are set as CD control signal input/output pins, setting the CDoff bit to 1 switches all the pins to an output port. MVSS ¾ 2VREF pin for PLL block P2VREF 49 PDO Outputs phase error signal between the EFM CD processor control and PLCK signals. input/output PVREF TMAX detection result output pin. Selected by command bit TMPS. 50 TMAX P2VREF Longer than the specified cycle: Outputs P2VREF. Shorter than the specified cycle: Outputs Low level (VSS). Within the specified cycle: at high impedance 51 LPFN Inverted input pin for low-pass filter amp. AVDD PVREF 52 LPFO Output pin for low-pass filter amp. 53 PVREF VREF pin for PLL block LPFN LPFO PVREF VCO VCOF 54 VCOF VCO filter pin 55 AVSS Ground pin for analog block 9 ¾ 2002-02-06 TC94A23F Pin Number Symbol 56 SLCO Pin Name Function and Operation Remarks Zin1 DAC output pin for generating data slice level VREF RFI 57 RFI RF signal input pin 58 AVDD Power supply pin for analog block 59 RFCT RFRP signal center level input pin AVDD SLCO DAC ¾ AVDD RFZI 60 RFZI RFRP zero-cross signal input pin 61 RFRP RF ripple signal input pin RFCT 1 kW typ. 32 kW typ. AVDD RFRP 62 FEI 63 SBAD 64 TEI CD processor control Focus error signal input pin input/output Sub beam addition signal input pin Tracking error input pin. FEI SBAD TEI The pin is read at tracking servo on. AVDD TEZI 65 TEZI Tracking error/zero-cross signal input pin Zin2 VREF 66 FOO 1 kW typ. 32 kW typ. Focus equalizer output pin AVDD Rout3 67 TRO Tracking equalizer output pin 68 VREF Analog reference voltage power supply pin 10 2VREF~ AVSS ¾ 2002-02-06 TC94A23F Pin Number Symbol Pin Name Function and Operation Remarks Control signal output pin for adjusting RF amplitude. 69 RFGC Outputs three-level PWM signal (PWM carrier = 88.2 kHz). P2VREF Tracking balance control signal output pin. 70 TEBC 71 FMO Rout3 Outputs three-level PWM signal (PWM carrier = 88.2 kHz). Focus equalizer output pin. Outputs three-level PWM signal (PWM carrier = 88.2 kHz). VREF Disc equalizer output pin. 72 DMO 73 2VREF CD processor control Outputs three-level PWM signal input/output (PWM carrier = 88.2 kHz for DSP block). Analog reference voltage power supply pin (2 ´ VREF) ¾ VDD APC circuit on/off signal output pin. 74 SEL 77 XVSS At laser on, high impedance at UHS = High; H level output at UHS = High. Power supply pins for CD crystal oscillator. 80 XVDD To control the CD processor power supply and the controller power supply individually, connect the MVDD and MVSS pins to the power supply lines used by the VDD and VSS pins. ¾ CD crystal oscillator input/output pins. Connect a 16.9344 MHz crystal oscillator. The clock is used as the CD system clock and controller system clock. 78 XI After system reset, this clock is supplied as CD processor crystal the controller system clock and starts the CPU. oscillator pins Rout1 XO The crystal oscillator can be halted by program. If the 4.5 MHz or 75 kHz oscillator is selected as the controller system clock, the oscillator is halted by program when the CD processor is off. 79 XO During execution of the CKSTP instruction, oscillation halts. (Note) RfXT1 XVDD XI XVSS When switching the controller system clock from the controller oscillator to the CD crystal oscillator, make sure that the CD crystal oscillator is in stable state. 11 2002-02-06 TC94A23F Pin Number Symbol 81 DVSR Pin Name Function and Operation Remarks R-channel D/A converter block ground pin DVDD 82 RO 83 DVRR 84 DVDD 85 DVRL 86 LO R-channel data forward rotation output pin DVRR/DVRL R-channel reference voltage pin CD processor control D/A converter block power supply pin input/output DVDD RO/LO L-channel reference voltage pin L-channel data forward rotation output pin DVSL/DVSR 87 DVSL VSS L-channel D/A converter block ground pin Device system reset signal input pin. 90 RST Reset input While the RST is at Low level, reset is applied. When the RST is at High level, the CD block is in operation, and the controller program starts from address 0. MVDD Normally, when 2.7 V or higher voltage is supplied to the MVDD when at 0 V, system reset is applied (power-on reset). Fix the pin to High level. Input pin used to request or release hold state. Normally, the pin is used for inputting the CD mode selection signal or battery detection signal. Halt states are Clock Stop mode (crystal oscillator stops oscillation) and Wait mode (CPU stops). The modes are entered using the CKSTP and WAIT instructions. By program, Clock Stop mode can be entered by detection of Low level on the HOLD pin or by forced execution. Clock Stop mode can be released by detection of High level on the HOLD pin or change in the HOLD pin input. 91 HOLD Hold mode control input MVDD Executing the CKSTP instruction stops the clock generator and the CPU, entering memory backup state. During memory backup state, current dissipation becomes low (1 mA or below). The display output and CMOS output port automatically become Low level. The N-channel open drain output becomes off. Regardless of the HOLD pin input state, Wait mode is executed and current dissipation becomes low. Crystal oscillator only on or CPU operation suspended can be programmed. When the crystal oscillator only is on, all displays are at Low level. The other pins are in Hold state. When CPU operation is suspended, all states are held except that the CPU is suspended. Wait mode is released by a change of the HOLD pin input. (Note) To use Backup mode, turn off the VDD pin (power supply for CD), and enter Backup mode. 12 2002-02-06 TC94A23F Pin Number Symbol Pin Name Function and Operation Remarks External interrupt input pin. 92 INTR External interrupt input When interrupts are enabled and a pulse of 1.11 to 3.33 ms or more (13.3 to 40 ms when the 75 kHz clock is used) is input to this pin, an interrupt is generated and the program jumps to address 1. Input logic and rising/falling edge can be individually selected for interrupt inputs. The internal 8-bit timer clock can be selected for interrupt inputs. Interrupts can be generated (address 3) by pulse count or the count value. Interrupt inputs are Schmidt inputs. The pin can be used as an input port for inputs such as remote control signals. Crystal oscillator pins for the controller. 93 MXO The oscillator clock is used as a time base for the clock function as well as the system clock for the controller. After system reset, the CPU starts operation using the 16.9344 MHz CD oscillator (connected to the XI and XO pins). The oscillator is switched to the controller oscillator by program. Either a 4.5 MHz reference oscillator or a 75 kHz oscillator is connected to the MXO and MXI pins. The oscillators are switched by a bit used to select a frequency of 4.5 MHz or 75 kHz. The oscillators incorporate a feedback resistor. Crystal oscillator pins Switching frequencies automatically switches the feedback resistor of the crystal oscillator. for controller 75 kHz: Rout2 = 2 KW, RfXT2 = 10 MW typ. 4.5 MHz: Rout2 = 2 KW, RfXT2 = 1 MW typ. Rout2 MXO RfXT2 MVDD MXI If the operating clock is the CD crystal oscillator, fix the MXI pin to GND. 94 MXI During execution of the CKSTP instruction, oscillation halts. Selection and control of crystal oscillators are done by program. (Note) When the 75 kHz crystal oscillator is used, externally add/connect a 100 kW output resistor. Power supply pins for the controller block. Normally, VDD = 4.5 to 5.5 V. 19, 96 MVDD In backup state (when executing the CKSTP instruction), current dissipation becomes low (1 mA or below), dropping the power supply voltage to 2.0 V. MVDD If 2.7 V or more is applied to these pins when at 0 V, a system reset is applied to the device and the program starts from address 0 (power-on reset). Power supply pins for controller block The CD processor incorporates a power supply detector, which detects the power supply voltage of 2.5 V. (Note) 20, 95 MVSS At power-on reset operation, allow 10 to 100 ms while the device power supply voltage rises. When not using the power supply detector function, set the test port pins (TEST#0 to 3) to all 1s so that the CD processor enters Halt state. Setting to Halt state reduces current dissipation by 150 mA (typ.). 13 MVSS 2002-02-06 TC94A23F Maximum Ratings (Ta = 25°C, VDD = MVDD = DVDD = AVDD, MVDD = XVDD) Characteristic Power supply voltage Symbol VDD MVDD Rating Unit -0.3~6.0 (MVDD > = VDD) V (VDD power supply pin) VIN1 -0.3~VDD + 0.3 (MVDD power supply pin) VIN2 -0.3~MVDD + 0.3 Power dissipation PD 1400 mW Operating temperature Topr -40~85 °C Storage temperature Tstg -65~150 °C Input voltage V 14 2002-02-06 TC94A23F Electrical characteristics (unless otherwise specified, Ta = 25°C, VDD = MVDD = XVDD = DVDD = AVDD = 5 V, 2VREF = P2VREF = 4.2 V, VREF = PVREF = 2.1 V) VDD (power supply pins for CD processor block: VDD, XVDD, DVDD, AVDD) Characteristic Operating power supply voltage range Operating power supply current Crystal oscillator standby current Crystal oscillator frequency Symbol Test Circuit VDD ¾ MVDD = XVDD > = VDD = DVDD = AVDD IDD ¾ XIDD Test Condition Min Typ. Max Unit 4.5 ~ 5.5 V (VDD, DVDD, AVDD) operating at 16.9344 MHz ¾ 50 60 ¾ (XVDD) 16.9344 MHz crystal oscillator connected ¾ 2.0 ¾ XSTBY ¾ (XVDD) 16.9344 MHz crystal oscillator off ¾ 0.01 ¾ mA fXT ¾ Ci = Co = 15 pF ¾ 16.9344 ¾ MHz Min Typ. Max Unit 4.5 ~ 5.5 4.5 ~ 5.5 * mA (Note 1)* MVDD (power supply pins for CPU block: MVDD, XVDD) (Note 2) Characteristic Symbol Test Circuit MVDD1 Operating power supply voltage range MVDD2 ¾ MVDD3 Memory hold voltage range Operating power supply current (Note 3) Memory hold current CPU and CD in operation MVDD = XVDD > = VDD = DVDD = AVDD * CPU in operation (CD off, 4.5 MHz /16.9344 MHz crystal oscillator used) * CPU in operation (CD off, 75 kHz crystal oscillator used) * Crystal oscillator stopped (executing CKSTP instruction) * ~ 5.5 2.0 ~ 5.5 XI = 16.9344 MHz crystal oscillator connected ¾ 3.0 5.0 MXI = 4.5 MHz crystal oscillator connected ¾ 1.4 2.5 ¾ 0.3 1.0 ¾ MIDD1 ¾ MIDD2 ¾ MIDD3 ¾ MXI = 75 kHz crystal oscillator connected ¾ XI = 16.9344 MHz crystal oscillator connected MIDD4 CPU in operation V 3.0 MVHD mA ¾ 1.5 ¾ ¾ 0.25 ¾ ¾ 0.1 ¾ ¾ 0.1 1.0 mA MIDD5 ¾ MIDD6 ¾ Standby mode MXI = 4.5 MHz crystal (crystal oscillator oscillator connected only in operation) MXI = 75 kHz crystal oscillator connected MIHD ¾ Crystal oscillator stopped (executing CKSTP instruction) fMXT1 ¾ 4.5 MHz crystal oscillator set (Note 1)* ¾ 4.5 ¾ MHz fMXT2 ¾ 75 kHz crystal oscillator set, MVDD = 2.7~5.5 V (Note 1)* ¾ 75 ¾ kHz tst ¾ Crystal oscillator fmxt = 75 kHz ¾ ¾ 1.0 s Crystal oscillator frequency Crystal oscillator start time Test Condition Note 1: Design and set constants according to the crystal oscillator to be connected. Note 2: The power supply/memory hold current is the value obtained by summing the XVDD and MVDD pin currents. Note 3: The values are those when the power supply detector function is operating. Setting the function reduces current dissipation by 150 mA (typ.). (Except in Standby mode) An asterisk (*) indicates the values are guaranteed when VDD = MVDD = XVDD = DVDD = AVDD = 4.5 to 5.5 V, and Ta = -40 to 85°C. 15 2002-02-06 TC94A23F LCD common output/output port (COM1/OT1 to COM4/OT4) Characteristic Test Circuit IOH1 ¾ IOH2 Min Typ. Max Unit VOH = 4.5 V (LCD output) -200 -600 ¾ mA ¾ VOH = 4.5 V (OT output) -15 -30 ¾ mA IOL1 ¾ VOL = 0.5 V (LCD output) 200 600 ¾ mA IOL5 ¾ VOL = 0.5 V (OT output) 4.0 10 ¾ mA 1/2 level VBS2 ¾ No load (LCD output, 1/2 bias method set) 2.3 2.5 2.7 1/3 level VBS1 ¾ 1.47 1.67 1.87 VBS3 ¾ 3.13 3.33 3.53 High level Output current Low level Bias voltage Symbol 2/3 level Test Condition V No load (LCD output, 1/3 bias method set) Segment output, output ports, I/O ports, and CD function output (S1/OT4 to S9/OT13, S10/OT14/ZDET to S14/OT18/LRCK, P8-0/S14/BCK to P8-3/S18/IPF, OT19) Characteristic Symbol Test Circuit IOH1 ¾ IOH4 Min Typ. Max Unit VOH = 4.5 V (LCD output) -200 -600 ¾ mA ¾ VOH = 4.5 V (OT output, CD output, excluding P8-0 to P8-3 pins) -1.5 -4.0 ¾ mA IOL1 ¾ VOL = 0.5 V (LCD output) 200 600 ¾ mA IOL5 ¾ VOL = 0.5 V (OT output, CD output) 4.0 10 ¾ mA ILI ¾ VIH = 5.0 V, VIL = 0 V (P8-0~P8-3) ¾ ¾ ±1.0 mA High level VIH ¾ (P8-0~P8-3, CLCK) MVDD ´ 0.8 ~ MVDD Low level VIL ¾ (P8-0~P8-3, CLCK) 0 ~ MVDD ´ 0.2 1/3 level VBS1 ¾ 1.47 1.67 1.87 VBS3 ¾ 3.13 3.33 3.53 Symbol Test Circuit Min Typ. Max IOH3 ¾ VOH = 4.5 V -0.8 -2.0 ¾ IOL3 ¾ VOL = 0.5 V (excluding P4-1, P4-2, P4-3 pins) 1.0 3.0 ¾ IOL5 ¾ VOL = 0.5 V (P4-1, P4-2, P4-3 pins) 4.0 10 ¾ ILI ¾ VIH = 5.0 V, VIL = 0 V ¾ ¾ ±1.0 High level VIH ¾ ¾ MVDD ´ 0.8 ~ MVDD Low level VIL ¾ ¾ 0 ~ MVDD ´ 0.2 RIN1 ¾ 25 50 120 kW High level Output current Low level Input leakage current Test Condition Input voltage Bias voltage 1/2 level V No load (LCD output, 1/3 bias method set) V I/O port (P1-0~P4-3) Characteristic High level Output current Low level Input leakage current Test Condition Input voltage Input pull-up/down resistance (P1-0 to P1-3 pins) pull-down/up set Unit mA mA V HOLD , INTR input port, RST RST input, 1-bit DAC data input (EMPHin/ HSO in/LRCKin/DATAin/BCKin) Input port (IN1/IN2) Characteristic Input leakage current High level Symbol Test Circuit ILI ¾ VIH ¾ Test Condition VIH = 5.0 V, VIL = 0 V ¾ Input voltage Low level VIL ¾ ¾ 16 Min Typ. Max Unit ¾ ¾ ±1.0 mA MVDD ´ 0.8 ~ MVDD ~ MVDD ´ 0.2 0 V 2002-02-06 TC94A23F A/D converter (ADin1 to ADin4) Symbol Test Circuit VAD ¾ VRES ¾ Total conversion error ¾ ¾ Analog input leakage ILI ¾ Characteristic Analog input voltage range Resolution Test Condition Min Typ. Max Unit 0 ~ MVDD V ¾ ¾ 6 ¾ bit ¾ ¾ ±0.5 ±1.0 LSB ¾ ¾ ±1.0 mA ADin1~ADin4 VIH = 5.0 V, VIL = 0 V (ADin1~ADin4) DOUT, SBSY, SBOK, SEL, OT19/ HSO , OT20/SPCK, OT21/SPDA, OT22/COFS output Symbol Test Circuit High level IOH4 ¾ Low level IOL4 ¾ Characteristic Output current Test Condition Min Typ. Max VOH = 4.5 V -1.5 -4.0 ¾ VOL = 0.5 V 1.5 4.0 ¾ Unit mA PDO, TMAX, RFGC, TEBC, FMO, DMO, TRO, FOO output Symbol Test Circuit Test Condition Min Typ. Max High level IOH6 ¾ VOH = 3.8 V, P2VREF = 4.2 V (PDO, TMAX) ¾ -2.0 ¾ Low level IOL4 ¾ VOL = 0.5 V, P2VREF = 4.2 V (PDO, TMAX) ¾ 6.0 ¾ Output resistance Rout3 ¾ (RFGC, TEBC, FMO, DMO, TRO, FOO) ¾ 3.3 ¾ kW VREF output voltage Voref ¾ (RFGC, TEBC, FMO, DMO, PDD) VREF = PVREF = 2.1 V ¾ 2.1 ¾ V Unit Characteristic Output current Unit mA Transfer delay time (AOUT, SPDA, DATA, SBSY, SBOK) Symbol Test Circuit Test Condition Min Typ. Max High level tpLH ¾ ¾ ¾ 10 ¾ Low level tpHL ¾ ¾ ¾ 10 ¾ Symbol Test Circuit Test Condition Min Typ. Max THD + N ¾ ¾ -85 -78 S/N ratio S/N ¾ 90 98 ¾ Dynamic range DR ¾ 1 kHz sine wave, based on -60dB input 85 90 ¾ Crosstalk CT ¾ 1 kHz sine wave, full-scale input ¾ -90 -85 DACout ¾ 1 kHz sine wave, full-scale input 1200 1250 1300 Characteristic Transfer delay time ns 1-bit DA converter Characteristic Total harmony distortion Analog output level 1 kHz sine wave, full-scale input ¾ 17 Unit dB mVrms 2002-02-06 TC94A23F Others Symbol Test Circuit Input pull-down resistance RIN2 ¾ XI amp feedback resistance RfXT1 XO output resistance Rout1 MXI amp feedback resistance RfXT2 MXO output resistance Rout2 Characteristic Input resistance Zin1 Zin2 Min Typ. Max Unit (TESTC, TESTM) ¾ 10 ¾ kW ¾ (XI-XO) 1.0 2.0 4.0 MW ¾ (XO) ¾ 0.5 ¾ kW ¾ When 4.5 MHz crystal set, (MXI-MXO) 0.5 1.0 2.5 ¾ When 75 kHz crystal set, (MXI-MXO) ¾ 10 ¾ ¾ (MXO) ¾ 2.0 ¾ ¾ 10 ¾ ¾ 5.0 ¾ ¾ 2.5 ¾ ¾ 1.25 ¾ ¾ 10 ¾ ¾ ¾ Test Condition Set resistance by (RFI) CD command (TEZI) 18 MW kW kW 2002-02-06 TC94A23F Package Dimensions Weight: 1.6 g (typ.) 19 2002-02-06 TC94A23F RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 20 2002-02-06