HD74HC108 Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock) Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Each flip-flop has independent J, K, and preset inputs and Q and Q outputs. Two flip-flops are controlled by a common clear and a common clock. Preset and clear are independent of the clock and accomplished by a low logic level on the corresponding input. Features • • • • • High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C) HD74HC108 Function Table Inputs Output Preset Clear Clock J K Q Q L H X X X H L H L X X X L L L H H*1 X X H* H L L No change H H L H L H H H H L H L H H H H Toggle H H L X X No change H H H X X No change H H X X No change Note: X H 1 1. Q and Q will remain HIGH as long as preset and Clear are Low, but Q and Q are unpredictable, if Preset and Clear go HIGH simultaneously. Pin Arrangement 1K 1 1Q 2 1Q 3 1J 4 2Q 5 Q 2Q 6 Q GND 7 J Q Q K PR CK CLR CLR PR J CK K (Top View) 2 14 VCC 13 1PR 12 CLR 11 2J 10 2PR 9 CK 8 2K HD74HC108 DC Characteristics Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Input voltage VIH 2.0 1.5 — — 1.5 — V 4.5 3.15 — — 3.15 — 6.0 4.2 — — 4.2 — 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 6.0 — — 1.8 — 1.8 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 — — 4.13 — I OH = –4 mA 6.0 5.68 — — 5.63 — I OH = –5.2 mA 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — — 0.26 — 0.33 I OL = 4 mA 6.0 — — 0.26 — 0.33 I OL = 5.2 mA VIL Output voltage VOH VOL Test Conditions V V V Vin = VIH or VIL I OH = –20 µA Vin = VIH or VIL I OL = 20 µA Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply current I CC 6.0 — — 2.0 20 µA Vin = VCC or GND, Iout = 0 µA — 3 HD74HC108 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Maximum clock f max 2.0 — — 6 — 5 MHz 4.5 — — 30 — 24 6.0 — — 35 — 28 Propagation delay t PLH 2.0 — — 150 — 190 time 4.5 — 20 30 — 38 6.0 — — 26 — 33 2.0 — — 140 — 175 4.5 — 18 28 — 35 6.0 — — 24 — 30 2.0 — — 140 — 175 4.5 — 16 28 — 35 6.0 — — 24 — 30 2.0 80 — — 100 — 4.5 16 7 — 20 — 6.0 14 — — 17 — 2.0 100 — — 125 — 4.5 20 2 — 25 — 6.0 17 — — 21 — 2.0 5 — — 5 — 4.5 5 –1 — 5 — 6.0 5 — — 5 — 2.0 100 — — 125 — 4.5 20 –2 — 25 — 6.0 17 — — 21 — frequency Pulse width Setup time Hold time Removal time t PHL tw t su th t rem Output rise/fall t TLH 2.0 — — 75 — 95 time t THL 4.5 — 5 15 — 19 6.0 — — 13 — 16 — — 5 10 — 10 Input capacitance 4 Cin Test Conditions ns Clock to Q or Q ns Clear to Q or Q ns Preset to Q or Q ns ns ns ns ns pF Unit: mm 19.20 20.32 Max 8 6.30 7.40 Max 14 1.30 7 2.54 ± 0.25 0.48 ± 0.10 0.51 Min 2.39 Max 2.54 Min 5.06 Max 1 7.62 + 0.10 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 8 5.5 14 1 0.10 ± 0.10 1.42 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7 + 0.20 7.80 – 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DA — Conforms 0.23 g Unit: mm 8.65 9.05 Max 8 1 7 *0.20 ± 0.05 0.635 Max 1.75 Max 3.95 14 + 0.10 6.10 – 0.30 1.08 *0.40 ± 0.06 0.11 0.14 +– 0.04 0° – 8° 1.27 0.67 0.60 +– 0.20 0.15 0.25 M *Pd plating Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DN Conforms Conforms 0.13 g Unit: mm 4.40 5.00 5.30 Max 14 8 1 7 0.65 0.20 ± 0.06 1.0 0.13 M 6.40 ± 0.20 0.10 *Dimension including the plating thickness Base material dimension *0.17 ± 0.05 0.15 ± 0.04 1.10 Max 0.83 Max 0.07 +0.03 –0.04 *0.22+0.08 –0.07 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-14D — — 0.05 g Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. 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Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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