HD74HC273 Octal D-type Flip-Flops (with Clear) Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state. Features • • • • • High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs Outputs Clear Clock D Q L X X L H H H H L L X No change X No change H H L HD74HC273 Pin Arrangement Clear 1 1Q 2 20 VCC Q Q Clear 1D 3 2D 4 D CK CK D D CK CK D Clear 2Q 5 3Q 6 3D 7 4D 8 Q Q Q Q CK CK D D CK CK 16 7Q 15 6Q D 14 6D 13 5D Clear Q Q GND 10 12 5Q 11 Clock (Top view) 2 17 7D Clear D Clear 9 18 8D Clear Clear 4Q 19 8Q Clear HD74HC273 Logic Diagram Clock 1D CK D CL Q 1Q Q 2Q Q 3Q Q 4Q Q 5Q Q 6Q Q 7Q Q 8Q Clear CK 2D D CL CK 3D D CL CK 4D D CL CK 5D D CL CK 6D D CL CK 7D D CL CK 8D D CL 3 HD74HC273 DC Characteristics Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Input voltage VIH 2.0 1.5 — — 1.5 — V 4.5 3.15 — — 3.15 — 6.0 4.2 — — 4.2 — 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 6.0 — — 1.8 — 1.8 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 — — 4.13 — I OH = –4 mA 6.0 5.68 — — 5.63 — I OH = –5.2 mA 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — — 0.26 — 0.33 I OL = 4 mA 6.0 — — 0.26 — 0.33 I OL = 5.2 mA VIL Output voltage VOH VOL Test Conditions V V V Vin = VIH or VIL I OH = –20 µA Vin = VIH or VIL I OL = 20 µA Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply current I CC 6.0 — — 4.0 40 µA Vin = VCC or GND, Iout = 0 µA 4 — HD74HC273 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Maximum clock f max 2.0 — — 6 — 5 MHz 4.5 — — 30 — 24 6.0 — — 35 — 28 Propagation delay t PHL 2.0 — — 145 — 180 time 4.5 — 18 29 — 36 6.0 — — 25 — 31 2.0 — — 145 — 180 4.5 — 18 29 — 36 6.0 — — 25 — 31 2.0 — — 145 — 180 4.5 — 15 29 — 36 6.0 — — 25 — 31 2.0 100 — — 125 — 4.5 20 2 — 25 — 6.0 17 — — 21 — 2.0 5 — — 5 — 4.5 5 0 — 5 — 6.0 5 — — 5 — 2.0 100 — — 125 — 4.5 20 –1 — 25 — 6.0 17 — — 21 — 2.0 80 — — 100 — 4.5 16 8 — 20 — 6.0 14 — — 17 — frequency t PLH t PHL Setup time Hold time Removal time Pulse width t su th t rem tw Output rise/fall t TLH 2.0 — — 75 — 95 time t THL 4.5 — 5 15 — 19 6.0 — — 13 — 16 — — 5 10 — 10 Input capacitance Cin ns Test Conditions Clock to Q ns ns Clear to Q ns Data to clock ns Clock to data ns Clear to clock ns Clock, clear ns pF 5 Unit: mm 24.50 25.40 Max 6.30 11 1 7.00 Max 20 10 1.30 2.54 ± 0.25 0.48 ± 0.10 0.51 Min 1.27 Max 2.54 Min 5.08 Max 0.89 7.62 + 0.11 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-20N — Conforms 1.26 g Unit: mm 12.6 13 Max 11 1 10 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 20 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-20DA — Conforms 0.31 g Unit: mm 12.8 13.2 Max 11 1 10 0.20 ± 0.10 0.935 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 *0.27 ± 0.05 0.25 ± 0.04 2.65 Max 7.50 20 0.25 10.40 +– 0.40 1.45 0° – 8° 0.57 0.70 +– 0.30 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-20DB Conforms — 0.52 g Unit: mm 6.50 6.80 Max 11 1 10 4.40 20 0.65 *0.22+0.08 –0.07 0.20 ± 0.06 1.0 0.13 M 6.40 ± 0.20 *Dimension including the plating thickness Base material dimension 0.07 +0.03 –0.04 0.10 *0.17 ± 0.05 0.15 ± 0.04 1.10 Max 0.65 Max 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-20DA — — 0.07 g Cautions 1. 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