HT1623 RAM Mapping 48´8 LCD Controller for I/O mC Features · · · · · · · · · · Operating voltage: 2.7V~5.2V Built-in RC oscillator External 32.768kHz crystal or 32kHz frequency source input 1/4 bias, 1/8 duty, frame frequency is 64Hz Max. 48´8 patterns, 8 commons, 48 segments Built-in internal resistor type bias generator 3-wire serial interface 8 kinds of time base/WDT selection Time base or WDT overflow output Built-in LCD display RAM · · · · · · · · R/W address auto increment Two selection buzzer frequencies (2kHz/4kHz) Power down command reduces power consumption Software configuration feature Data mode and Command mode instructions Three data accessing modes VLCD pin to adjust LCD operating voltage Cascade application General Description configuration feature of the HT1623 make it suitable for multiple LCD applications including LCD modules and display subsystems. Only three lines are required for the interface between the host controller and the HT1623. The HT162X series have many kinds of products that match various applications. HT1623 is a peripheral device specially designed for I/O type mC used to expand the display capability. The max. display segment of the device are 384 patterns (48´8). It also supports serial interface, buzzer sound, watchdog timer or time base timer functions. The H T 1 6 2 3 i s a m em or y m a p p i n g a n d multi-function LCD controller. The software Selection Table HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270 COM 4 4 8 8 8 8 16 16 16 SEG 32 32 32 32 48 64 48 64 64 Ö Ö Ö Ö Ö Ö Ö Ö Ö Built-in Osc. Crystal Osc. Ö Ö Ö 1 Ö April 21, 2000 HT1623 Block Diagram O S C O D is p la y R A M O S C I C S C o n tro l a n d T im in g C ir c u it R D W R C O M 0 C O M 7 L C D D r iv e r / B ia s C ir c u it D A T A S E G 0 S E G 4 7 V D D V S S V L C D B Z W a tc h d o g T im e r a n d T im e B a s e G e n e r a to r T o n e F re q u e n c y G e n e ra to r B Z IR Q Pin Assignment S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G N C N C N C 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 N C C S R D W R D A T A V S S O S C I O S C O V D D V L C D IR Q B Z B Z T 1 T 2 T 3 C O M 0 C O M 1 N C N C N C N C N C N C N C N C N C N C C O M 2 C O M 3 C O M 4 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 N C 2 7 9 N C 3 7 8 4 7 7 5 7 6 1 6 7 5 7 7 4 8 7 3 9 7 2 1 0 7 1 1 1 7 0 1 2 6 9 1 3 6 8 H T 1 6 2 3 1 0 0 Q F P 1 4 1 5 1 6 6 7 6 6 6 5 1 7 6 4 1 8 6 3 1 9 6 2 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 N C N C N C N C N C S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E G 3 1 G 3 0 G 2 9 G 2 8 G 2 7 G 2 6 G 2 5 G 2 4 G 2 3 G 2 2 G 2 1 G 2 0 G 1 9 G 1 8 G 1 7 G 1 6 G 1 5 G 1 4 G 1 3 N C N C N C N C N C N C N C N C S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G C O M C O M C O M 1 2 1 1 7 1 0 9 8 7 6 5 4 3 2 1 0 6 5 2 April 21, 2000 HT1623 Pad Assignment S E G 4 1 S E G 4 0 S E G 3 9 S E G 3 8 S E G 3 7 S E G 3 6 S E G 3 5 S E G 3 4 S E G 3 3 S E G 3 2 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 6 7 8 V L C D 9 IR Q 1 0 B Z 7 0 5 V S S V D D 7 1 4 O S C I O S C O S E G 4 2 D A T A S E G 4 3 3 S E G 4 4 W R S E G 4 5 2 S E G 4 6 R D S E G 4 7 1 C S (0 ,0 ) 1 1 B Z 1 2 T 1 1 3 T 2 1 4 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 S E G 0 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 Chip size: 177 ´ 171 (mil) S E G 2 7 5 0 S E G 2 6 4 9 S E G 2 5 4 8 S E G 2 4 4 7 S E G 2 3 4 6 S E G 2 2 4 5 S E G 2 1 4 4 S E G 2 0 4 3 4 2 S E G 1 9 S E G 1 8 4 1 S E G 1 7 4 0 S E G 1 6 3 9 S E G 1 5 3 8 S E G 1 4 3 7 S E G 1 3 3 2 3 3 3 4 3 5 3 6 S E G 1 2 2 3 S E G 2 8 5 1 S E G 1 1 2 2 S E G 2 9 5 2 S E G 1 0 2 1 S E G 3 0 5 3 S E G 9 2 0 S E G 3 1 S E G 8 1 9 S E G 1 1 8 C O M 7 1 7 C O M 2 C O M 6 C O M 1 C O M 5 1 6 C O M 4 1 5 C O M 3 T 3 C O M 0 5 5 5 4 2 * The IC substrate should be connected to VDD in the PCB layout artwork. 3 April 21, 2000 HT1623 Pad Coordinates Unit: mil Pad No. X Y Pad No. X Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 -82.45 -82.45 -82.45 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -82.88 -72.50 -65.88 -59.24 -52.62 -45.73 -33.32 -26.69 -14.28 -7.65 4.76 11.39 23.80 30.43 42.84 49.47 61.88 68.51 80.92 79.35 67.02 60.39 46.71 32.30 25.20 18.57 11.94 5.31 -4.84 -16.66 -29.92 -41.74 -48.37 -54.99 -61.63 -68.25 -78.96 -79.99 -79.99 -79.99 -79.99 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 27.03 20.40 13.77 7.14 0.51 -6.12 -12.75 -19.38 -26.01 -32.64 -39.27 -45.90 -52.53 -59.16 -65.79 -72.42 -52.44 -35.23 -28.60 -21.97 -15.34 -8.71 -2.08 4.55 11.18 17.81 24.44 31.07 37.70 44.33 50.96 57.59 64.22 70.85 77.48 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 4 April 21, 2000 HT1623 Pad Description Pad No. 1 Pad Name CS I/O Description I Chip selection input with pull-high resistor. When the CS is logic high, the data and command read from or written to the HT1623 are disabled. The serial interface circuit is also reset But if the CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1623 are all enabled. 2 RD I READ clock input with pull-high resistor. Data in the RAM of the HT1623 are clocked out on the rising edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next falling edge to latch the clocked out data. 3 WR I WRITE clock input with pull-high resistor. Data on the DATA line are latched into the HT1623 on the rising edge of the WR signal. 4 DATA I/O Serial data input/output with pull-high resistor 5 VSS ¾ Negative power supply, ground 6 OSCI I 7 OSCO O The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads can be left open. 8 VDD ¾ Positive power supply 9 VLCD I LCD operating voltage input pad. 10 IRQ O Time base or watchdog timer overflow flag, NMOS open drain output 11, 12 BZ, BZ O 2kHz or 4kHz tone frequency output pair 13~15 T1~T3 I Not connected 16~23 COM0~COM7 O LCD common outputs 24~71 SEG0~SEG47 O LCD segment outputs Absolute Maximum Ratings Supply Voltage..............................-0.3V to 5.5V Storage Temperature.................-50°C to 125°C Input Voltage ................VSS-0.3V to VDD+0.3V Operating Temperature ..............-25°C to 75°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. 5 April 21, 2000 HT1623 D.C. Characteristics Symbol Parameter VDD Operating Voltage IDD1 Operating Current IDD2 Operating Current IDD11 Operating Current IDD22 Operating Current ISTB Standby Current VIL Input Low Voltage VIH Input High Voltage IOL1 BZ, BZ, IRQ IOH1 BZ, BZ IOL1 DATA IOH1 DATA IOL2 LCD Common Sink Current IOH2 LCD Common Source Current Ta=25°C Test Conditions Min. Typ. Max. Unit VDD Conditions ¾ ¾ 2.7 ¾ 5.2 V 3V No load/LCD ON On-chip RC oscillator ¾ 155 310 mA ¾ 260 420 mA No load/LCD ON Crystal oscillator ¾ 150 310 mA ¾ 250 420 mA No load/LCD OFF On-chip RC oscillator ¾ 8 30 mA ¾ 20 60 mA No load/LCD OFF Crystal oscillator ¾ ¾ 20 mA ¾ ¾ 35 mA No load Power down mode ¾ 1 10 mA ¾ 2 20 mA 0 ¾ 0.6 V 0 ¾ 1.0 V 2.4 ¾ 3 V 4.0 ¾ 5 V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V DATA, WR, CS, RD DATA, WR, CS, RD 3V VOL=0.3V 0.9 1.8 ¾ mA 5V VOL=0.5V 1.7 3 ¾ mA 3V VOH=2.7V -0.9 -1.8 ¾ mA 5V VOH=4.5V -1.7 -3 ¾ mA 3V VOL=0.3V 0.9 1.8 ¾ mA 5V VOL=0.5V 1.7 3 ¾ mA 3V VOH=2.7V -0.9 -1.8 ¾ mA 5V VOH=4.5V -1.7 -3 ¾ mA 3V VOL=0.3V 80 160 ¾ mA 5V VOL=0.5V 180 360 ¾ mA 3V VOH=2.7V -40 -80 ¾ mA 5V VOH=4.5V -90 -180 ¾ mA 6 April 21, 2000 HT1623 Symbol Parameter IOL3 LCD Segment Sink Current IOH3 LCD Segment Source Current RPH Pull-high Resistor Test Conditions VDD Conditions Min. Typ. Max. Unit 3V VOL=0.3V 50 100 ¾ mA 5V VOL=0.5V 120 240 ¾ mA 3V VOH=2.7V -30 -60 ¾ mA 5V VOH=4.5V -70 -140 ¾ mA 100 200 300 kW 50 100 150 kW 3V 5V DATA, WR, CS, RD A.C. Characteristics Symbol Parameter fSYS1 System Clock fSYS2 System Clock fLCD1 LCD Frame Frequency fLCD2 LCD Frame Frequency tCOM LCD Common Period fCLK1 Serial Data Clock (WR Pin) fCLK2 Serial Data Clock (RD Pin) tCS Serial Interface Reset Pulse Width (Figure 3) tCLK WR, RD Input Pulse Width (Figure 1) Ta=25°C Test Conditions Min. Typ. 22 32 40 kHz 24 32 40 kHz ¾ 32 ¾ kHz ¾ 32 ¾ kHz 44 64 80 Hz 48 64 80 Hz ¾ 64 ¾ Hz ¾ 64 ¾ Hz ¾ n/fLCD ¾ sec ¾ ¾ 150 kHz ¾ ¾ 300 kHz ¾ ¾ 75 kHz ¾ ¾ 150 kHz ¾ 250 ¾ ns Write mode 3.34 ¾ ¾ Read mode 6.67 ¾ ¾ Write mode 1.67 ¾ ¾ Read mode 3.34 ¾ ¾ Conditions VDD 3V 5V 3V 5V 3V 5V 3V 5V ¾ 3V 5V 3V 5V ¾ 3V 5V On-chip RC oscillator External clock source On-chip RC oscillator External clock source n: Number of COM Duty cycle 50% Duty cycle 50% CS 7 Max. Unit ms ms April 21, 2000 HT1623 Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit tr, tf Rise/Fall Time Serial Data 3V Clock Width (Figure 1) 5V ¾ ¾ 120 ¾ ns tsu Setup Time DATA to WR, RD 3V Clock Width (Figure 2) 5V ¾ ¾ 120 ¾ ns th Hold Time DATA to WR, RD 3V Clock Width (Figure 2) 5V ¾ ¾ 120 ¾ ns tsu1 Setup Time for CS to WR, RD 3V Clock Width (Figure 3) 5V ¾ ¾ 100 ¾ ns th1 Hold Time for CS to WR, RD 3V Clock Width (Figure 3) 5V ¾ ¾ 100 ¾ ns V A L ID D A T A tf W R , R D C lo c k tr 9 0 % 5 0 % 1 0 % tC - V D D L K W R , R D C lo c k Figure 1 5 0 % ts W R , R D C lo c k th u 1 5 0 % F IR S T C lo c k 1 S - V G N D th u V 5 0 % D D - G N D D D G N D - V L A S T C lo c k D D Figure 2 tC C S V 5 0 % ts G N D tC L K D B D D G N D Figure 3 8 April 21, 2000 HT1623 Functional Description Display memory - RAM structure Time base and watchdog timer - WDT The static display RAM is organized into 96´4 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessedbytheREAD,WRITEand READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns. The time base generator and WDT share the same divided (/256) counter. TIMER DIS/EN/CLR, WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ pin will remain at logic low level until the CLR WDT or the IRQ DIS command is issued. C O M 7 C O M 6 C O M 5 C O M 3 C O M 4 C O M 2 C O M 1 C O M 0 S E G 0 1 0 S E G 1 3 2 S E G 2 5 4 S E G 3 7 6 S E G 4 7 9 5 9 4 D 3 D 2 D 1 A d d r D 0 D 3 D a ta D 2 D 1 D 0 A d d r e s s 7 B its (A 6 , A 5 , ...., A 0 ) A d d r D a ta D a ta 4 B its (D 3 , D 2 , D 1 , D 0 ) RAM mapping T im e B a s e C lo c k S o u r c e T IM E R /2 5 6 V C L R T im e r W D T /4 W D T E N /D IS D D Q D IR Q C K C L R IR Q E N /D IS E N /D IS R W D T Timer and WDT configurations 9 April 21, 2000 HT1623 The following are the data mode ID and the command mode ID: If an external clock is selected as the source of system frequency, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is removed. Operation Buzzer tone output A simple tone generator is implemented in the HT1623. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone. ID READ Data 110 WRITE Data 101 READ-MODIFY-WRITE Data 101 COMMAND Command 1 0 0 If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to ²1² and the previous operation mode will be reset also. The CS pin returns to ²0², a new operation mode ID should be issued first. Command format The HT1623 can be configured by the software setting. There are two mode commands to configure the HT1623 resource and to transfer the LCD display data. Name Mode Command Code Function TONE OFF 0000-1000-X Turn-off tone output TONE 4K 010X-XXXX-X Turn-on tone output, tone frequency is 4kHz TONE 2K 0110-XXXX-X Turn-on tone output, tone frequency is 2kHz 10 April 21, 2000 HT1623 Timing Diagrams READ mode (command code : 1 1 0) C S W R R D D A T A 1 0 1 A 5 A 6 A 4 A 3 A 2 A 1 A 0 D 0 M e m o ry A d d re s s 1 (M A 1 ) D 2 D 1 D 3 1 0 1 A 6 D a ta (M A 1 ) A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D a ta (M A 2 ) M e m o ry A d d re s s 2 (M A 2 ) READ mdoe (successive address reading) C S W R R D D A T A 1 1 0 A 6 A 5 A 4 A 3 A 2 A 1 M e m o ry A d d re s s (M A ) A 0 D 0 D 1 D 2 D a ta (M A ) 11 D 3 D 0 D 1 D 2 D a ta (M A + 1 ) D 3 D 0 D 1 D 2 D a ta (M A + 2 ) D 3 D 0 D 1 D 2 D 3 D 0 D a ta (M A + 3 ) April 21, 2000 HT1623 WRITE mode (command code : 1 0 1) C S W R D A T A 1 1 0 A 5 A 6 A 4 A 3 A 2 A 1 A 0 M e m o ry A d d re s s 1 (M A 1 ) D 0 D 1 D 2 D 3 1 1 0 A 5 A 6 D a ta (M A 1 ) A 3 A 4 A 2 A 1 A 0 D 0 M e m o ry A d d re s s 2 (M A 2 ) D 2 D 1 D 3 D a ta (M A 2 ) WRITE mode (successive address writing) C S W R D A T A 1 0 1 A 6 A 5 A 4 A 3 A 2 A 1 M e m o ry A d d re s s (M A ) A 0 D 0 D 1 D 2 D a ta (M A ) 12 D 3 D 0 D 1 D 2 D a ta (M A + 1 ) D 3 D 0 D 1 D 2 D a ta (M A + 2 ) D 3 D 0 D 1 D 2 D 3 D 0 D a ta (M A + 3 ) April 21, 2000 HT1623 READ-MODIFY-WRITE mode (command code : 1 0 1) C S W R R D D A T A 1 1 0 A 5 A 6 A 4 A 3 A 2 A 1 A 0 D 0 M e m o ry A d d re s s 1 (M A 1 ) D 2 D 1 D 3 D 0 D a ta (M A 1 ) D 1 D 2 D 3 1 0 1 D a ta (M A 1 ) A 6 A 5 A 4 A 3 A 2 A 1 A 0 M e m o ry A d d re s s 2 (M A 2 ) D 0 D 1 D 2 D 3 D a ta (M A 2 ) READ-MODIFY-WRITE mode (successive address accessing) C S W R R D D A T A 1 0 1 A 6 A 5 A 4 A 3 A 2 A 1 M e m o ry A d d re s s (M A ) A 0 D 0 D 1 D 2 D 3 D a ta (M A ) D 0 D 1 D 2 D a ta (M A ) 13 D 3 D 0 D 1 D 2 D a ta (M A + 1 ) D 3 D 0 D 1 D 2 D a ta (M A + 1 ) D 3 D 0 D 1 D 2 D 3 D 0 D a ta (M A + 2 ) April 21, 2000 HT1623 Command mode (command code : 1 0 0) C S W R D A T A 1 0 0 C 8 C 7 C 6 C 5 C 4 C 3 C o m m a n d 1 C 2 C 1 C 0 C 8 C o m m a n d ... C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 C o m m a n d i C o m m a n d o r D a ta M o d e Mode (data and command mode) C S W R D A T A C o m m a n d o r D a ta M o d e A d d re s s a n d D a ta C o m m a n d o r D a ta M o d e A d d re s s a n d D a ta C o m m a n d o r D a ta M o d e A d d re s s a n d D a ta R D 14 April 21, 2000 HT1623 Application Circuits V D D C S * *V R R D V L C D W R D A T A m C *R H T 1 6 2 3 B Z P ie z o IR Q B Z O S C I C lo c k O u t O S C O E x te r n a l C lo c k 1 ( 3 2 k H z ) E x te r n a l C lo c k 2 ( 3 2 k H z ) C O M 0 ~ C O M 7 S E G 0 ~ S E G 4 7 1 /4 B ia s , 1 /8 D u ty O n - c h ip O S C L C D P a n e l C ry s ta l 3 2 7 6 8 H z *Note: The connection of IRQ and RD pin can be selected depending on the requirement of the mC. The voltage applied to VLCD pin must be lower than VDD. Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW±20%. Adjust R (external pull-high resistance) to fit user¢s time base clock. 15 April 21, 2000 HT1623 Command Summary Name ID Command Code D/C Function Def. READ 1 1 0 A6A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM WRITE 1 0 1 A6A5A4A3A2A1A0D0D1D2D3 D Write data to the RAM READMODIFYWRITE 1 0 1 A6A5A4A3A2A1A0D0D1D2D3 D Read and Write data to the RAM SYS DIS 1 0 0 0000-0000-X C Turn off both system oscillator and LCD bias generator SYS EN 1 0 0 0000-0001-X C Turn on system oscillator LCD OFF 1 0 0 0000-0010-X C Turn off LCD display LCD ON 1 0 0 0000-0011-X C Turn on LCD display TIMER DIS 1 0 0 0000-0100-X C Disable time base output WDT DIS 1 0 0 0000-0101-X C Disable WDT time-out flag output Yes TIMER EN 1 0 0 0000-0110-X C Enable time base output WDT EN 1 0 0 0000-0111-X C Enable WDT time-out flag output TONE OFF 1 0 0 0000-1000-X C Turn off tone outputs CLR TIMER 1 0 0 0000-1101-X C Clear the contents of the time base generator CLR WDT 1 0 0 0000-1111-X C Clear the contents of the WDT stage RC 32K 1 0 0 0001-10XX-X C System clock source, on-chip RC oscillator EXT (XTAL) 32K 1 0 0 0001-11XX-X C System clock source, external 32kHz clock source or crystal oscillator 32.768kHz TONE 4K 1 0 0 010X-XXXX-X C Tone frequency output: 4kHz TONE 2K 1 0 0 0110-XXXX-X C Tone frequency output: 2kHz IRQ DIS 1 0 0 100X-0XXX-X C Disable IRQ output IRQ EN 1 0 0 100X-1XXX-X C Enable IRQ output F1 1 0 0 101X-0000-X C Time base clock output: 1Hz The WDT time-out flag after: 4s F2 1 0 0 101X-0001-X C Time base clock output: 2Hz The WDT time-out flag after: 2s F4 1 0 0 101X-0010-X C Time base clock output: 4Hz The WDT time-out flag after: 1s 16 Yes Yes Yes Yes Yes Yes April 21, 2000 HT1623 Name ID Command Code D/C Function Def. F8 1 0 0 101X-0011-X C Time base clock output: 8Hz The WDT time-out flag after: 1/2 s F16 1 0 0 101X-0100-X C Time base clock output: 16Hz The WDT time-out flag after: 1/4 s F32 1 0 0 101X-0101-X C Time base clock output: 32Hz The WDT time-out flag after: 1/8 s F64 1 0 0 101X-0110-X C Time base clock output: 64Hz The WDT time-out flag after: 1/16 s F128 1 0 0 101X-0111-X C Time base clock output: 128Hz Yes The WDT time-out flag after: 1/32 s TEST 1 0 0 1110-0000-X C Test mode, user don¢t use. NORMAL 1 0 0 1110-0011-X C Normal mode Yes Note: X : Don¢t care A6~A0 : RAM address D3~D0 : RAM data D/C : Data/Command mode Def. : Power on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from an on-chip 32kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1623 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1623. 17 April 21, 2000 HT1623 Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright Ó 2000 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. 18 April 21, 2000