RAM Mapping 32 X 4 LCD Controller for I/O uC *********************************************************************************************************** General Descriptions The SS1621 is a 128-pattern (32x4), memory mapping, and multi-function LCD driver. The S/W configuration feature of the SS1621 makes it suitable for multiple LCD applications including LCD modules and display subsystems. Only three or four lines are required for the interface between the host controller and the SS1621. The SS1621 contains a power down command to reduce power consumption. Features • • • • • • • • • • • • • • • • • • • Operating voltage: 2.4V~5.2V. Built-in 256kHz RC oscillator. External 32.768kHz crystal or 256kHz frequency source input. Selection of 1/2 or 1/3 bias, and selection of 1/2 or 1/3 or 1/4 duty LCD applications. Internal time base frequency sources. Two selectable buzzer frequencies (2kHz/4kHz). Built-in time base generator and WDT. Time base or WDT overflow output. Power down command reduces power Consumption. 8 kinds of time base/WDT clock sources. 32x4 LCD driver. Built-in 32x4 bit display RAM. 3-wire serial interface. Internal LCD driving frequency source. Software configuration feature. Data mode and command mode instructions. R/W address auto increment. Three data accessing modes. VLCD pin for adjusting LCD operating voltage. p. 1 Last update: 2008-06-03 16:06 SS1621 Block Diagram BZ BZ Tone Generator Watchdog Timer & Time Base Generator VDD GND IRQ VLCD COM0 CS LCD Driver & Bias Circuit WR RD DATA Control Logic & Timing Generator COM3 SEG0 SEG31 OSCI OSCO Display Memory Note: CS: Chip selection BZ, BZ: Tone outputs WR, RD, DATA: Serial interface IRQ: Time base or WDT overflow output COM0~COM3, SEG0~SEG31: LCD outputs p. 2 Last update: 2008-06-03 04:36 SS1621 Pin Assignment SS1621B-48SSOP SS1621D-28SKDIP SS1621BL -48LQFP SS1621B -48LQFP p. 3 Last update: 2008-06-03 04:36 SS1621 PIN Description PIN Name I/O Function I Chip selection input with pull-high resistor When the CS is logic high, the data and command read from or written to the SS1621 are disabled. The serial interface circuit is also reset. But if CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the SS1621 are all enabled. I READ clock input with pull-high resistor Data in the RAM of the SS1621 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the DATA line. The host controller can use the next rising edge to latch the clocked out data. WR I WRITE clock input with pull-high resistor Data on the DATA line are latched into the SS1621 on the rising edge of the WR signal. DATA I/O Serial data input/output with pull-high resistor GND — Negative power supply, ground OSCO O OSCI I The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if and on-chip RC oscillator is selected instead, the OSCI and OSCO pads can be left open. VLCD I VDD — Positive power supply IRQ O Time base or WDT overflow flag, NMOS open drain output BZ, BZ O 2kHz or 4kHz tone frequency output pair COM0~COM3 O LCD common outputs SEG0~SEG31 O LCD segment outputs CS RD LCD power input p. 4 Last update: 2008-06-03 04:36 SS1621 Absolute Maximum Ratings Supply Voltage…………...…..…-0.3V ~ 5.5V Input Voltage……… VSS - 0.3V ~ VDD + 0.3V Storage Temperature……………-50°C ~ 125°C Operating Temperature…………..-25°C ~ 75°C Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter VDD Operating Voltage IDD1 Operating Current IDD2 Operating Current IDD3 Operating Current ISTB Standby Current VIL Input Low Voltage VIH Input High Voltage IOL1 DATA, BZ, BZ, IRQ IOH1 DATA, BZ, BZ IOL2 LCD Common Sink Current IOH2 LCD Common Source Current IOL3 LCD Segment Sink Current IOH3 LCD Segment Source Current RPH Pull-high Resistor VDD — 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V Test Conditions Conditions — No load/LCD ON On-chip RC oscillator No load/LCD ON Crystal oscillator No load/LCD ON External clock source No load Power down mode DATA, WR, CS, RD DATA, WR, CS, RD VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5 V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5 V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5 V DATA, WR, CS, RD p. 5 Min. Typ. Max. Unit 2.4 — — — — — — — — 0 0 2.4 4.0 0.5 1.3 -0.4 -0.9 80 150 -80 -120 60 120 -40 -70 40 30 — 150 300 60 120 100 200 0.1 0.3 — — — — 1.2 2.6 -0.8 -1.8 150 250 -120 -200 120 200 -70 -100 80 60 5.2 300 600 120 240 200 400 5 10 0.6 1.0 3.0 5.0 — — — — — — — — — — — — 150 100 V µA µA µA µA µA µA µA µA V V V V mA mA mA mA µA µA µA µA µA µA µA µA kΩ kΩ Last update: 2008-06-03 04:36 SS1621 A.C. Characteristics Sym. Test Conditions Parameter Min. Typ. Max. Unit — 256 — kHz — 256 — kHz — 32.768 — kHz — 32.768 — kHz — 256 — kHz — 256 — kHz On-chip RC oscillator — FSYS1/1024 — Hz Crystal oscillator — FSYS2/128 — Hz External clock source — FSYS3/1024 — Hz n: Number of COM — n/fLCD — s — 150 kHz — 300 kHz — 75 kHz — 150 kHz Conditions VDD fSYS1 System Clock fSYS2 System Clock fSYS3 System Clock fLCD LCD Clock 3V 5V 3V 5V 3V 5V — tCOM LCD Common Period fCLK1 Serial Data Clock (WR Pin) fCLK2 Serial Data Clock ( RD Pin) 3V 5V 3V 5V fTONE Tone Frequency tCS tCLK Serial Interface Reset Pulse Width (Figure 3) WR, RD Input Pulse Width (Figure 1) Rise/Fall Time Serial Data Clock tr, tf Width (Figure 1) tsu th tsu1 th1 3V 5V 3V 5V 3V On-chip RC oscillator Crystal oscillator External clock source Duty cycle 50% Duty cycle 50% On-chip RC oscillator — 2.0 or 4.0 — kHz CS — 250 — ns Write mode 3.34 — — Read mode 6.67 — — Write mode 1.67 — — Read mode 3.34 — — — — 120 — ns — — 120 — ns — — 120 — ns — — 100 — ns — — 100 — ns μs μs 5V Setup Time for DATA to WR, RD Clock Width (Figure 2) 3V Hold Time for DATA to WR, RD Clock Width (Figure 2) 3V Setup Time for CS to WR, RD Clock Width (Figure 3) 3V Hold Time for CS to WR, RD Clock Width (Figure 3) 3V 5V 5V 5V 5V p. 6 Last update: 2008-06-03 04:36 SS1621 tf WR, RD Clock tf VDD 90% 50% 10% VALID DATA VDD DB 50% GND tCLK GND tCLK tSU Figure 1 th VDD WR, RD Clock 50% GND Figure 2 tCS VDD CS 50% GND th1 tsu1 VDD WR, RD Clock 50% FIRST Clock GND LAST Clock Figure 3 Functional Description Display memory – RAM The static display memory (RAM) is organized into 32x4 bits and stores the displayed data. The contents of the RAM are directly mapped to the contents of the LCD COM3 COM2 COM1 COM0 SEG0 0 SEG1 1 SEG2 2 SEG3 3 SEG31 Address 6 bits (A5, A4, …, A0) 31 D3 D2 D1 D0 Data Addr Data 4 bits (D3, D2, D1, D0) RAM mapping driver. Data in the RAM can be accessed by OSCI OSCO the READ, WRITE, and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD pattern: System oscillator The SS1621 system clock is used to generate the time base/Watchdog Timer (WDT) clock frequency, LCD driving clock, and tone frequency. The source of the clock may be from an on-chip RC oscillator (256kHz), a crystal oscillator (32.768kHz), or an external 256kHz clock by the S/W setting. The configuration of the system oscillator is as shown. After the SYS DIS command is executed, the system clock will stop and the LCD bias generator will turn off. That command is, however, available only for the Crystal Oscillator 32768Hz External Clock Source 256kHz System Clock 1/8 On-chip RC Oscillator 256kHz System oscillator configuration p. 7 Last update: 2008-06-03 04:36 SS1621 on-chip RC oscillator or for the crystal oscillator. Once the system clock stops, the LCD display will become blank, and the time base/WDT lose its function as well. The LCD OFF command is used to turn the LCD bias generator off. After the LCD bias generator switches off by issuing the LCD OFF command, using the SYS DIS command reduces power consumption, serving as a system power down command. But if the external clock source is chosen as the system clock, using the SYS DIS command can neither turn the oscillator off nor carry out the power down mode. The crystal oscillator option can be applied to connect an external frequency source of 32kHz to the OSCI pin. In this case, the system fails to enter the power down mode, similar to the case in the external 256kHz clock source operation. At the initial system power on, the SS1621 is at the SYS DIS state. Time base and Watchdog Timer (WDT) The time base generator is comprised by an 8-stage count-up ripple counter and is designed to generate an accurate time base. The watch dog timer (WDT), on the other hand, is composed of and 8-stage time base generator along with a 2-stage count-up counter, and is designed to break the host controller or other subsystems from abnormal states such as unknown or unwanted jump, execution errors, etc. The WDT time-out will result in the setting of and internal WDT time-out flag. The outputs of the time base generator and of the WDT time-out flag can be connected to the IRQ output by a command option. There are totally eight frequency sources available for the time base generator and the WDT clock. The frequency is calculated by the following equation. f WDT = 32kHz 2n Where the value of n ranges from 0 to 7 by command options. The 32kHz in the above equation indicates that the source of the system frequency is derived from a crystal oscillator of 32.768kHz, an on-chip oscillator (256kHz), or an external frequency of 256kHz. If an on-chip oscillator (256kHz) or an external 256kHz frequency is chosen as the source of the system frequency, the frequency source is by default prescaled to 32kHz by a 3-stage prescaler. Employing both the time base generator and the WDT related commands, one should be careful since the time base generator and WDT share the same 8-stage counter. For example, invoking the WDT DIS command disables the time base generator whereas executing the WDT EN command not only enables the time base generator but activates the WDT time-out flag output (connect the WDT time-out flag to the IRQ pin). After the TIMER EN command is transferred, the WDT is disconnected from the IRQ pin, and the output of the time base generator is connected to the IRQ pin. The WDT can be cleared by executing the CLR WDT command, and the contents of the base time generator is cleared by executing the CLR WDT or the CLR TIMER command. The CLR WDT or the CLR TIMER command should be executed prior to the WDT EN or the TIMER EN command respectively. Before executing the IRQ EN command the CLR WDT or CLR TIMER command should be executed first. The CLR TIMER command has to be executed before switching from the WDT mode to the time base mode. Once the WDT time-out occurs, the IRQ pin will stay at a logic low level until the CLR WDT or the IRQ DIS command is issued. After the IRQ output is disabled the IRQ pin will remain at the floating state. The IRQ output can be enabled or disabled by executing the IRQ EN or the IRQ DIS command, respectively. The IRQ EN makes the output of the time base p. 8 Last update: 2008-06-03 04:36 SS1621 Name LCD OFF LCD ON Command Code 1 0 0 0 0 0 0 0 0 1 0 X 1 0 0 0 0 0 0 0 0 1 1 X BIAS & COM 1 0 0 0 0 1 0 a b X c X generator or of the WDT time-out flag appear on the IRQ pin. The configuration of the time base generator along with the WDT are as shown. In the case of on-chip RC oscillator or crystal oscillator, the power down mode can reduce power consumption since the oscillator can be turned on or off by the corresponding system commands. At the power down mode the time base/WDT loses all its functions. On the other hand, if an external clock is selected as the source of sys tem frequency the SYS DIS command turns out invalid and the power down mode fails to be carried out. That is, after the external clock source is selected, the SS1621 will continue working until system power fails or the external clock source is removed. After the system power on, the IRQ will be disabled. Tone output A simple tone generator is implemented in the SS1621. The tone generator can output a pair of differential driving signals on the BZ and BZ, which are used to generate a single tone. By executing the TONE4K and TONE2K commands there are two tone frequency outputs selectable. The TONE4K and TONE2K commands set the tone frequency to 4kHz and 2kHz, respectively. The tone output can be turned on or off by invoking the TONE ON or the TONE OFF command. The tone outputs, namely BZ and BZ, area pair of differential driving outputs used to drive a piezo buzzer. Once the system is disabled or the tone output is inhibited, the BZ and the BZ output will remain at low level. Function Turn off LCD outputs Turn on LCD outputs c=0:1/2 bias option c=1:1/3 bias option ab=00:2 commons option ab=01:3 commons option ab=10:4 commons option LCD driver The SS1621 is a 128 (32x4) patterns LCD driver. It can be configured as 1/2 or 1/3 bias and 2 or 3 or 4 commons of LCD driver by the S/W configuration. This feature makes the SS1621 suitable for multiply LCD applications. The LCD driving clock is derived from the system clock. The value of the driving clock is always 256Hz even when it is at a 32.768kHz crystal oscillator frequency, or an external frequency. The LCD corresponding commands are summarized in the table. The bold form of 100, namely 100, indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The LCD OFF command turns the LCD display off by disabling the LCD bias generator. The LCD ON command, on the other hand, turns the LCD display on by enabling the LCD bias generator. The BIAS and COM are the LCD panel related commands. Using the LCD related commands; the SS1621 can be compatible with most types of LCD panels. Command format The SS1621 can be configured by the S/W setting. There are two mode commands to configure the SS1621 resources and to transfer the LCD display data. The configuration mode of the SS1621 is called command mode, and its command mode IC is 100. The command mode consists of system configuration command, a system frequency selection command, a LCD configuration command, a tone frequency selection command, a p. 9 Last update: 2008-06-03 04:36 SS1621 timer/WDT setting command, and an operating command. The data mode, on the other hand, includes READ, WRITE, and READ-MODIFY-WRITE operations. The following are the data mode Ids and the command mode ID: Operation READ WRITE READ-MODIFY-WRITE COMMAND Mode Data Data Data Command ID 110 101 101 100 The mode command should be issued before the data or command is transferred. If successive commands have been issued, the command mode ID, namely 100, can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to “1” and the previous operation mode will be reset also. Once the CS pin returns to “0” a new operation mode ID should be issued first. Interfacing Only four lines are required to interface with the SS1621. The CS line is used to initialize the serial interface circuit and to terminate the communication between the host controller and the SS1621. If the CS pin is set to 1, the data and command issued between the host controller and the SS1621 are first disabled and then initialized. Before issuing a mode command or mode switching, a high level pulse is required to initialize the serial interface of the SS1621. The DATA line is the serial data input/output line. Data to be read or written or commands to be written have to be passed through the DATA line. The RD line is the READ clock input. Data in the RAM are clocked out on the falling edge of the RD signal, and the clocked out data will then appear on the DATA line. It is recommended that the host controller read in correct data during the interval between the rising edge and the next falling edge of the RD signal. The WR line is the WRITE clock input. The data, address, and command on the DATA line are all clocked into the SS1621 on the rising edge of the WR signal. There is an optional IRQ line to be used as an interface between the host controller and the SS1621. The IRQ pin can be selected as a timer output or a WDT overflow flag output by the S/W setting. The host controller can perform the time base or the WDT function by being connected with the IRQ pin of the SS1621. p. 10 Last update: 2008-06-03 04:36 SS1621 Timing Diagrams READ mode (command code: 1 1 0 ) CS WR RD DATA 1 1 0 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 Memory Address 1 (MA1) Data (MA1) 1 1 1 1 0 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 Memory Address 2 (MA2) Data (MA2) CS WR RD DATA 0 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 Memory Address (MA) Data (MA) Data (MA+1) Data (MA+2) Data (MA+3) READ mode (successive address reading) WRITE mode (command code: 1 0 1 ) WRITE mode (successive address writing) CS WR DATA 1 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 Memory Address (MA) Data (MA) Data (MA+1) Data (MA+2) Data (MA+3) 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 Memory Address 1 (MA1) Data (MA1) CS WR DATA 1 1 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 Memory Address 2 (MA2) Data (MA2) p. 11 Last update: 2008-06-03 04:36 SS1621 READ-MODIFY-WRITE mode (command code: 1 0 1 ) CS WR RD DATA 1 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 1 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 Memory Address 1 (MA1) Data (MA1) Data (MA1) Memory Address 2 (MA2) Data (MA2) Data (MA2) READ-MODIFY-WRITE mode (successive address accessing) CS WR RD 1 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 DATA Memory Address (MA) Data (MA) Data (MA) Data (MA+1) Data (MA+1) Data (MA+2) Data (MA+2) Command mode (command code: 1 0 0 ) CS WR DATA 1 0 0 C8 C7 C6 C5 C4 C3 C2 C1 C0 Command 1 C8 C7 C6 C5 C4 C3 C2 C1 C0 Command… Command i Command or Data Mode Mode (data and command mode) CS WR DATA Command Address & Data or Data Mode Command Address & Data or Data Mode Command Address & Data or Data Mode RD Note: It is recommended that the host controller should read in the data from the DATA line between the rising edge of the RD line and the falling edge of the next RD line. p. 12 Last update: 2008-06-03 04:36 SS1621 Application Circuits Host controller with a SS1621 display system CS * VDD RD * WR μC DATA * VLCD SS1621 R BZ Piezo IRQ BZ OSCI Clock Out External Clock 1 External Clock 2 On-chip OSC VR OSCO COM0 ~ COM3 SEG0 ~ SEG31 1/2 or 1/3 Bias; 1/2, 1/3 or 1/4 Duty LCD PANEL Crystal 32768Hz Note: The connection of IRQ and RD pin can be selected depending on the requirement of the μC. The voltage applied to VLCD pin must be lower than VDD. Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kΩ+20% Adjust R (external pull-high resistance) to fit user’s time base clock. p. 13 Last update: 2008-06-03 04:36 SS1621 Command Summary Name ID Command Code D/C Function Def. READ 1 1 0 A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM WRITE 1 0 1 A5A4A3A2A1A0D0D1D2D3 D Write data to the RAM READ-MODIFY-WRITE 1 0 1 A5A4A3A2A1A0D0D1D2D3 D READ and WRITE to the RAM SYS DIS 1 0 0 0000-0000-X C SYS EN 1 0 0 0000-0001-X C Turn on system oscillator LEC OFF 1 0 0 0000-0010-X C Turn off LCD bias generator LCD ON 1 0 0 0000-0011-X C Turn on LCD bias generator TIMER DIS 1 0 0 0000-0100-X C Disable time base output WDT DIS 1 0 0 0000-0101-X C Disable WDT time-out flag output TIMER EN 1 0 0 0000-0110-X C Enable time base output WDT EN 1 0 0 0000-0111-X C Enable WDT time-out flag output TONE OFF 1 0 0 0000-1000-X C Turn off tone outputs TONE ON 1 0 0 0000-1001-X C Turn on tone outputs CLR TIMER 1 0 0 0000-11XX-X C CLR WDT 1 0 0 0000-111X-X C Clear the contents of WDT stage XTAL 32K 1 0 0 0001-01XX-X C System clock source, crystal oscillator RC 256K 1 0 0 0001-10XX-X C System clock source, external clock Yes source EXT 256K 1 0 0 0001-11XX-X C System clock source, external clock source 1 0 0 0010-abX0-X LCD 1/2 bias option ab=00:2 commons option C ab=01:3 commons option ab=10:4 commons option BLAS 1/3 1 0 0 0010-abX1-X LCD 1/3 bias option ab=00:2 commons option C ab=01:3 commons option ab=10:4 commons option TONE 4K 1 0 0 010X-XXXX-X C Tone frequency, 4kHz TONE 2K 1 0 0 011X-XXXX-X C Tone frequency, 2kHz IRQ DIS 1 0 0 100X-0XXX-X C Disable IRQ output IRQ EN 1 0 0 100X-1XXX-X C Enable IRQ output F1 1 0 0 101X-X000-X Time base/WDT clock C Output: 1Hz The WDT time-out flag after: 4s F2 1 0 0 101X-X001-X BLAS 1/2 Turn off system oscillator and LCD Yes bias generator Yes Yes Clear the contents of time base generator Yes C Time base/WDT clock Output: 2Hz p. 14 Last update: 2008-06-03 04:36 SS1621 Name ID Command Code D/C Function Def. The WDT time-out flag after: 2s 1 0 0 101X-X010-X Time base/WDT clock C Output: 4Hz The WDT time-out flag after: 1s F8 1 0 0 101X-X011-X Time base/WDT clock C Output: 8Hz The WDT time-out flag after: 1/2s F16 1 0 0 101X-X100-X Time base/WDT clock C Output: 16Hz The WDT time-out flag after: 1/4s 1 0 0 101X-X101-X Time base/WDT clock C Output: 32Hz The WDT time-out flag after: 1/8s F64 1 0 0 101X-X110-X Time base/WDT clock C Output: 64Hz The WDT time-out flag after: 1/16s F128 1 0 0 101X-X111-X Time base/WDT clock C Output: 128Hz Yes The WDT time-out flag after: 1/32s TEST 1 0 0 1110-0000-X C NORMAL 1 0 0 1110-0011-X C F4 F32 Yes Note: X: Don’t care A5~A0: RAM addresses D3~D0: RAM data D/C: Data/command mode Def.: Power on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0 , are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from an on-chip 256kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 256kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the SS1621 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the SS1621. p. 15 Last update: 2008-06-03 04:36