HT1621 RAM Mapping 32´4 LCD Controller for I/O mC Features · · · · · · · · · Operating voltage : 2.4V~5.2V Built-in 256kHz RC oscillator External 32.768kHz crystal or 256kHz frequency source input Selection of 1/2 or 1/3 bias, and selection of 1/2 or 1/3 or 1/4 duty LCD applications Internal time base frequency sources Two selectable buzzer frequencies (2kHz/4kHz) Power down command reduces power consumption Built-in time base generator and WDT Time base or WDT overflow output · · · · · · · · · · 8 kinds of time base/WDT clock sources 32´4 LCD driver Built-in 32´4 bit display RAM 3-wire serial interface Internal LCD driving frequency source Software configuration feature Data mode and command mode instructions R/W address auto increment Three data accessing modes VLCD pin for adjusting LCD operating voltage General Description systems. Only three or four lines are required for the interface between the host controller and the HT1621. The HT1621 contains a power down command to reduce power consumption. The HT1621 is a 128 pattern (32´4), memory mapping, and multi-function LCD driver. The S/W configuration feature of the HT1621 makes it suitable for multiple LCD applications including LCD modules and display sub- Selection Table HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 COM 4 4 8 8 8 8 16 SEG 32 32 32 32 48 64 48 Ö Ö Ö Ö Ö Ö Ö Ö Built-in Osc. Crystal Osc. Ö Ö Ö 1 January 10, 2001 HT1621 Block Diagram D is p la y R A M O S C O O S C I C S R D W R C o n a n T im C ir c tro l d in g u it C O M 0 L C D D r iv e r / B ia s C ir c u it C O M 3 S E G 0 D A T A V D D S E G 3 1 V S S V L C D B Z B Z T o n e F re q u e n c y G e n e ra to r W a tc h d o g T im e r a n d T im e B a s e G e n e r a to r IR Q Note: CS: Chip selection BZ, BZ: Tone outputs WR, RD, DATA: Serial interface COM0~COM3, SEG0~SEG31: LCD outputs IRQ: Time base or WDT overflow output 2 January 10, 2001 HT1621 Pin Assignment S E G 7 1 4 8 S E G 8 S E G 7 1 4 8 S E G 8 S E G 6 2 4 7 S E G 9 S E G 6 2 4 7 S E G 9 S E G 5 3 4 6 S E G 1 0 S E G 5 3 4 6 S E G 1 0 S E G 4 4 4 5 S E G 1 1 S E G 4 4 4 5 S E G 1 1 S E G 3 5 4 4 S E G 1 2 S E G 3 5 4 4 S E G 1 2 S E G 2 6 4 3 S E G 1 3 S E G 2 6 4 3 S E G 1 3 S E G 1 7 4 2 S E G 1 4 S E G 1 7 4 2 S E G 1 4 S E G 0 8 4 1 S E G 1 5 S E G 0 8 4 1 S E G 1 5 C S 9 4 0 S E G 1 6 C S 9 4 0 S E G 1 6 R D 1 0 3 9 S E G 1 7 R D 1 0 3 9 S E G 1 7 W R 1 1 3 8 S E G 1 8 W R 1 1 3 8 S E G 1 8 S E G 5 1 2 8 S E G 7 D A T A 1 2 3 7 S E G 1 9 D A T A 1 2 3 7 S E G 1 9 S E G 3 2 2 7 S E G 9 V S S 1 3 3 6 S E G 2 0 V S S 1 3 3 6 S E G 2 0 S E G 1 3 2 6 S E G 1 1 O S C O 1 4 3 5 S E G 2 1 O S C O 1 4 3 5 S E G 2 1 C S 4 2 5 S E G 1 3 N C 1 5 3 4 S E G 2 2 O S C I 1 5 3 4 S E G 2 2 R D 5 2 4 S E G 1 5 O S C I 1 6 3 3 S E G 2 3 V L C D 1 6 3 3 S E G 2 3 W R 6 2 3 S E G 1 7 V D D /V L C D 1 7 3 2 S E G 2 4 V D D 1 7 3 2 S E G 2 4 D A T A 7 2 2 S E G 1 9 IR Q 1 8 3 1 S E G 2 5 IR Q 1 8 3 1 S E G 2 5 V S S 8 2 1 S E G 2 1 B Z 1 9 3 0 S E G 2 6 B Z 1 9 3 0 S E G 2 6 V L C D 9 2 0 S E G 2 3 B Z 2 0 2 9 S E G 2 7 B Z 2 0 2 9 S E G 2 7 V D D 1 0 1 9 S E G 2 5 C O M 0 2 1 2 8 S E G 2 8 C O M 0 2 1 2 8 S E G 2 8 IR Q 1 1 1 8 S E G 2 7 C O M 1 2 2 2 7 S E G 2 9 C O M 1 2 2 2 7 S E G 2 9 B Z 1 2 1 7 S E G 2 9 C O M 2 2 3 2 6 S E G 3 0 C O M 2 2 3 2 6 S E G 3 0 C O M 0 1 3 1 6 S E G 3 1 C O M 3 2 4 2 5 S E G 3 1 C O M 3 2 4 2 5 S E G 3 1 C O M 1 1 4 1 5 C O M 2 H T 1 6 2 1 4 8 S S O P H T 1 6 2 1 B 4 8 S S O P /D IP 3 H T 1 6 2 1 D 2 8 S K D IP January 10, 2001 HT1621 Pad Assignment C S S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 S E G 8 S E G 9 S E G 1 0 S E G 1 1 S E G 1 2 S E G 1 3 S E G 1 4 S E G 1 5 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 2 R D W R 1 3 3 2 S E G 1 6 3 1 S E G 1 7 3 0 S E G 1 8 2 9 S E G 1 9 D A T A 4 V S S 5 2 8 S E G 2 0 O S C O 6 2 7 S E G 2 1 2 6 S E G 2 2 2 5 S E G 2 3 2 4 S E G 2 4 2 3 S E G 2 5 (0 ,0 ) O S C I 7 V L C D 8 V D D 9 1 6 1 7 1 8 1 9 S E G 3 0 S E G 2 9 B Z 1 5 S E G 3 1 B Z 1 4 C O M 3 IR Q 1 3 C O M 2 1 2 C O M 1 1 1 C O M 0 1 0 Chip size: 127 ´ 129 (mil) 2 2 S E G 2 6 2 1 S E G 2 7 2 0 S E G 2 8 2 * The IC substrate should be connected to VDD in the PCB layout artwork. 4 January 10, 2001 HT1621 Pad Coordinates Unit:mil Pad No. X Y Pad No. X Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 -55.04 -58.52 -58.52 -58.52 -58.52 -58.52 -58.52 -58.52 -58.52 -58.52 -44.07 -31.58 -20.70 -13.98 -7.05 -0.34 6.33 12.96 19.59 58.14 58.14 58.14 58.14 58.14 59.46 22.18 15.56 5.36 -4.51 -11.14 -34.76 -41.90 -49.13 -59.08 -59.08 -59.08 -59.08 -59.08 -59.08 -59.08 -59.08 -59.08 -59.08 -58.44 -51.81 -45.18 -38.55 -31.92 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 58.14 58.14 58.14 58.14 58.14 58.14 58.14 58.14 55.55 48.92 42.29 35.66 29.03 22.40 15.77 9.14 2.42 -4.21 -10.84 -17.47 -24.10 -30.73 -38.17 -45.39 -25.29 -18.66 -11.94 -5.31 1.32 7.95 14.58 21.21 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 5 January 10, 2001 HT1621 Pad Description Pad No. 1 Pad Name CS I/O Function I Chip selection input with pull-high resistor When the CS is logic high, the data and command read from or written to the HT1621 are disabled. The serial interface circuit is also reset. But if CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1621 are all enabled. 2 RD I READ clock input with pull-high resistor Data in the RAM of the HT1621 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the DATA line. The host controller can use the next rising edge to latch the clocked out data. 3 WR I WRITE clock input with pull-high resistor Data on the DATA line are latched into the HT1621 on the rising edge of the WR signal. 4 DATA I/O Serial data input/output with pull-high resistor 5 VSS ¾ Negative power supply, ground 7 OSCI I 6 OSCO O The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads can be left open. 8 VLCD I LCD power input 9 VDD ¾ Positive power supply 10 IRQ O Time base or WDT overflow flag, NMOS open drain output 11, 12 BZ, BZ O 2kHz or 4kHz tone frequency output pair 13~16 COM0~COM3 O LCD common outputs 48~17 SEG0~SEG31 O LCD segment outputs Absolute Maximum Ratings o o Supply Voltage .................................-0.3V~5.5V Storage Temperature....................-50 C~125 C Input Voltage ....................VSS-0.3V~VDD+0.3V Operating Temperature..................-25 C~75 C o o Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. 6 January 10, 2001 HT1621 D.C. Characteristics Symbol Parameter VDD Operating Voltage IDD1 Operating Current IDD2 Operating Current IDD3 Operating Current ISTB Standby Current VIL Input Low Voltage VIH Input High Voltage IOL1 DATA, BZ, BZ, IRQ IOH1 DATA, BZ, BZ IOL2 LCD Common Sink Current IOH2 LCD Common Source Current IOL3 LCD Segment Sink Current IOH3 LCD Segment Source Current RPH Pull-high Resistor Ta=25°C Test Conditions Min. Typ. Max. Unit 2.4 ¾ 5.2 V No load/LCD ON On-chip RC oscillator ¾ 150 300 mA ¾ 300 600 mA No load/LCD ON Crystal oscillator ¾ 60 120 mA ¾ 120 240 mA No load/LCD ON External clock source ¾ 100 200 mA ¾ 200 400 mA No load Power down mode ¾ 0.1 5 mA ¾ 0.3 10 mA 0 ¾ 0.6 V 0 ¾ 1.0 V 2.4 ¾ 3.0 V 4.0 ¾ 5.0 V VDD Conditions ¾ ¾ 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V DATA, WR, CS, RD DATA, WR, CS, RD 3V VOL=0.3V 0.5 1.2 ¾ mA 5V VOL=0.5V 1.3 2.6 ¾ mA 3V VOH=2.7V -0.4 -0.8 ¾ mA 5V VOH=4.5V -0.9 -1.8 ¾ mA 3V VOL=0.3V 80 150 ¾ mA 5V VOL=0.5V 150 250 ¾ mA 3V VOH=2.7V -80 -120 ¾ mA 5V VOH=4.5V -120 -200 ¾ mA 3V VOL=0.3V 60 120 ¾ mA 5V VOL=0.5V 120 200 ¾ mA 3V VOH=2.7V -40 -70 ¾ mA 5V VOH=4.5V -70 -100 ¾ mA 40 80 150 kW 30 60 100 kW 3V 5V DATA, WR, CS, RD 7 January 10, 2001 HT1621 A.C. Characteristics Symbol fSYS1 fSYS2 fSYS3 fLCD Parameter System Clock System Clock System Clock LCD Clock tCOM LCD Common Period fCLK1 Serial Data Clock (WR pin) fCLK2 Serial Data Clock (RD pin) fTONE Tone Frequency tCS tCLK Serial Interface Reset Pulse Width (Figure 3) WR, RD Input Pulse Width (Figure 1) Ta=25°C Test Conditions Min. Typ. 3V On-chip RC oscillator ¾ 256 ¾ kHz 5V ¾ 256 ¾ kHz ¾ 32.768 ¾ kHz VDD 3V 5V 3V 5V Conditions Crystal oscillator External clock source Max. Unit ¾ 32.768 ¾ kHz ¾ 256 ¾ kHz ¾ 256 ¾ kHz ¾ On-chip RC oscillator ¾ fSYS1/1024 ¾ Hz ¾ Crystal oscillator ¾ fSYS2/128 ¾ Hz ¾ External clock source ¾ fSYS3/1024 ¾ Hz ¾ n: Number of COM ¾ n/fLCD ¾ s ¾ ¾ 150 kHz ¾ ¾ 300 kHz ¾ ¾ 75 kHz ¾ ¾ 150 kHz 3V 5V 3V 5V Duty cycle 50% Duty cycle 50% ¾ On-chip RC oscillator ¾ 2.0 or 4.0 ¾ kHz ¾ CS ¾ 250 ¾ ns Write mode 3.34 ¾ ¾ Read mode 6.67 ¾ ¾ Write mode 1.67 ¾ ¾ Read mode 3.34 ¾ ¾ 3V 5V ms ms tr, tf Rise/Fall Time Serial Data 3V Clock Width (Figure 1) 5V ¾ ¾ 120 ¾ ns tsu Setup Time for DATA to WR, 3V RD Clock Width (Figure 2) 5V ¾ ¾ 120 ¾ ns th Hold Time for DATA to WR, 3V RD Clock Width (Figure 2) 5V ¾ ¾ 120 ¾ ns tsu1 Setup Time for CS to WR, RD 3V Clock Width (Figure 3) 5V ¾ ¾ 100 ¾ ns th1 Hold Time for CS to WR, RD 3V Clock Width (Figure 3) 5V ¾ ¾ 100 ¾ ns 8 January 10, 2001 HT1621 V A L ID D A T A tf tr 9 0 % 5 0 % 1 0 % W R , R D C lo c k tC V tC L K D B D D W R , R D C lo c k Figure 1 tC tsu W R , R D C lo c k th 1 S V V D D G N D D D G N D 1 V 5 0 % F IR S T C lo c k 5 0 % Figure 2 5 0 % C S D D G N D th tsu G N D L K V 5 0 % D D G N D L A S T C lo c k Figure 3 Functional Description Display memory - RAM System oscillator The static display memory (RAM) is organized into 32´4 bits and stores the displayed data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE, and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD pattern: The HT1621 system clock is used to generate the time base/Watchdog Timer (WDT) clock frequency, LCD driving clock, and tone frequency. The source of the clock may be from an on-chip RC oscillator (256kHz), a crystal oscillator (32.768kHz), or an external 256kHz clock by the S/W setting. The configuration of the system oscillator is as shown. After the SYS DIS command is executed, the system clock will stop and the LCD bias generator will turn off. That command is, however, available only for the on-chip RC oscillator or for the crystal oscillator. Once the system clock stops, the LCD display will become blank, and the time base/WDT lose its function as well. C O M 3 C O M 2 C O M 1 C O M 0 S E G 0 0 S E G 1 1 S E G 2 2 S E G 3 3 S E G 3 1 3 1 D 3 D 2 D 1 D 0 A d d r e s s 6 b its (A 5 , A 4 , ..., A 0 ) The LCD OFF command is used to turn the LCD bias generator off. After the LCD bias generator switches off by issuing the LCD OFF command, using the SYS DIS command reduces power consumption, serving as a system power down command. But if the external clock source is chosen as the system clock, using the SYS DIS command can neither turn the oscillator off nor carry out the power down mode. The crystal oscillator option can be applied to connect an external frequency source of 32kHz to the OSCI pin. In this case, the system fails to A d d r D a ta D a ta 4 b its (D 3 , D 2 , D 1 , D 0 ) RAM mapping 9 January 10, 2001 HT1621 enter the power down mode, similar to the case in the external 256kHz clock source operation. At the initial system power on, the HT1621 is at the SYS DIS state. where the value of n ranges from 0 to 7 by command options. The 32kHz in the above equation indicates that the source of the system frequency is derived from a crystal oscillator of 32.768kHz, an on-chip oscillator (256kHz), or an external frequency of 256kHz. Time base and Watchdog Timer (WDT) The time base generator is comprised by an 8-stage count-up ripple counter and is designed to generate an accurate time base. The watch dog timer (WDT), on the other hand, is composed of an 8-stage time base generator along with a 2-stage count-up counter, and is designed to break the host controller or other subsystems from abnormal states such as unknown or unwanted jump, execution errors, etc. The WDT time-out will result in the setting of an internal WDT time-out flag. The outputs of the time base generator and of the WDT time-out flag can be connected to the IRQ output by a command option. There are totally eight frequency sources available for the time base generator and the WDT clock. The frequency is calculated by the following equation. fWDT = If an on-chip oscillator (256kHz) or an external 256kHz frequency is chosen as the source of the system frequency, the frequency source is by default prescaled to 32kHz by a 3-stage prescaler. Employing both the time base generator and the WDT related commands, one should be careful since the time base generator and WDT share the same 8-stage counter. For example, invoking the WDT DIS command disables the time base generator whereas executing the WDT EN command not only enables the time base generator but activates the WDT time-out flag output (connect the WDT time-out flag to the IRQ pin). After the TIMER EN command is transferred, the WDT is disconnected from the IRQ pin, and the output of the time base generator is connected to the IRQ pin. The WDT can be cleared by executing the CLR WDT command, and the contents of the time base generator is cleared by executing the CLR WDT or the CLR 32kHz 2n C r y s ta l O s c illa to r 3 2 7 6 8 H z O S C I O S C O E x te r n a l C lo c k S o u r c e 2 5 6 k H z S y s te m C lo c k 1 /8 O n - c h ip R C O s c illa to r 2 5 6 k H z System oscillator configuration S y s te m C lo c k f= 3 2 k H z T im e r /W D T C lo c k S o u r c e s /2 n n = 0 ~ 7 T IM E R E N /D IS /2 5 6 V W D T /4 IR Q W D T E N /D IS D D Q D C K C L R IR Q E N /D IS R W D T Timer and WDT configurations 10 January 10, 2001 HT1621 Name Command Code Function LCD OFF 10000000010X Turn off LCD outputs LCD ON 10000000011X Turn on LCD outputs 1000010abXcX c=0: 1/2 bias option c=1: 1/3 bias option ab=00: 2 commons option ab=01: 3 commons option ab=10: 4 commons option BIAS & COM Tone output TIMER command. The CLR WDT or the CLR TIMER command should be executed prior to the WDT EN or the TIMER EN command respectively. Before executing the IRQ EN command the CLR WDT or CLR TIMER command should be executed first. The CLR TIMER command has to be executed before switching from the WDT mode to the time base mode. Once the WDT time-out occurs, the IRQ pin will stay at a logic low level until the CLR WDT or the IRQ DIS command is issued. After the IRQ output is disabled the IRQ pin will remain at the floating state. The IRQ output can be enabled or disabled by executing the IRQ EN or the IRQ DIS command, respectively. The IRQ EN makes the output of the time base generator or of the WDT time-out flag appear on the IRQ pin. The configuration of the time base generator along with the WDT are as shown. In the case of on-chip RC oscillator or crystal oscillator, the power down mode can reduce power consumption since the oscillator can be turned on or off by the corresponding system commands. At the power down mode the time base/WDT loses all its functions. A simple tone generator is implemented in the HT1621. The tone generator can output a pair of differential driving signals on the BZ and BZ, which are used to generate a single tone. By executing the TONE4K and TONE2K commands there are two tone frequency outputs selectable. The TONE4K and TONE2K commands set the tone frequency to 4kHz and 2kHz, respectively. The tone output can be turned on or off by invoking the TONE ON or the TONE OFF command. The tone outputs, namely BZ and BZ, are a pair of differential driving outputs used to drive a piezo buzzer. Once the system is disabled or the tone output is inhibited, the BZ and the BZ outputs will remain at low level. LCD driver The HT1621 is a 128 (32´4) pattern LCD driver. It can be configured as 1/2 or 1/3 bias and 2 or 3 or 4 commons of LCD driver by the S/W configuration. This feature makes the HT1621 suitable for multiply LCD applications. The LCD driving clock is derived from the system clock. The value of the driving clock is always 256Hz even when it is at a 32.768kHz crystal oscillator frequency, an on-chip RC oscillator frequency, or an external frequency. The LCD corresponding commands are summarized in the table. On the other hand, if an external clock is selected as the source of system frequency the SYS DIS command turns out invalid and the power down mode fails to be carried out. That is, after the external clock source is selected, the HT1621 will continue working until system power fails or the external clock source is removed. After the system power on, the IRQ will be disabled. The bold form of 1 0 0, namely 1 0 0, indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command, will be omitted. The LCD 11 January 10, 2001 HT1621 the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to "1" and the previous operation mode will be reset also. Once the CS pin returns to "0" a new operation mode ID should be issued first. OFF command turns the LCD display off by disabling the LCD bias generator. The LCD ON command, on the other hand, turns the LCD display on by enabling the LCD bias generator. The BIAS and COM are the LCD panel related commands. Using the LCD related commands, the HT1621 can be compatible with most types of LCD panels. Interfacing Only four lines are required to interface with the HT1621. The CS line is used to initialize the serial interface circuit and to terminate the communication between the host controller and the HT1621. If the CS pin is set to 1, the data and command issued between the host controller and the HT1621 are first disabled and then initialized. Before issuing a mode command or mode switching, a high level pulse is required to initialize the serial interface of the HT1621. The DATA line is the serial data input/output line. Data to be read or written or commands to be written have to be passed through the DATA line. The RD line is the READ clock input. Data in the RAM are clocked out on the falling edge of the RD signal, and the clocked out data will then appear on the DATA line. It is recommended that the host controller read in correct data during the interval between the rising edge and the next falling edge of the RD signal. The WR line is the WRITE clock input. The data, address, and command on the DATA line are all clocked into the HT1621 on the rising edge of the WR signal. There is an optional IRQ line to be used as an interface between the host controller and the HT1621. The IRQ pin can be selected as a timer output or a WDT overflow flag output by the S/W setting. The host controller can perform the time base or the WDT function by being connected with the IRQ pin of the HT1621. Command format The HT1621 can be configured by the S/W setting. There are two mode commands to configure the HT1621 resources and to transfer the LCD display data. The configuration mode of the HT1621 is called command mode, and its command mode ID is 1 0 0. The command mode consists of a system configuration command, a system frequency selection command, a LCD configuration command, a tone frequency selection command, a timer/WDT setting command, and an operating command. The data mode, on the other hand, includes READ, WRITE, and READ-MODIFY-WRITE operations. The following are the data mode IDs and the command mode ID: Operation Mode ID READ Data 110 WRITE Data 101 READ-MODIFY-WRITE Data 101 COMMAND Command 1 0 0 The mode command should be issued before the data or command is transferred. If successive commands have been issued, the command mode ID, namely 1 0 0, can be omitted. While 12 January 10, 2001 HT1621 Timing Diagrams READ mode (command code : 1 1 0) C S W R R D D A T A 1 0 1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 M e m o ry A d d re s s 1 (M A 1 ) D a ta (M A 1 ) 1 1 0 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 M e m o r y A d d r e s s 2 ( M A 2 )D a t a ( M A 2 ) READ mode (successive address reading) C S W R R D D A T A 1 1 0 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 ) M e m o ry A d d re s s (M A ) D a ta (M A ) 13 January 10, 2001 HT1621 WRITE mode (command code : 1 0 1) C S W R D A T A 1 1 0 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 M e m o r y A d d r e s s 1 ( M A 1 )D a t a ( M A 1 ) 1 0 1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 M e m o r y A d d r e s s 2 ( M A 2 )D a t a ( M A 2 ) WRITE mode (successive address writing) C S W R D A T A 1 0 1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 ) M e m o ry A d d re s s (M A ) D a ta (M A ) 14 January 10, 2001 HT1621 READ-MODIFY-WRITE mode (command code : 1 0 1) C S W R R D D A T A 1 1 0 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 M e m o r y A d d r e s s 1 ( M A 1 )D a t a ( M A 1 ) D a ta (M A 1 ) 1 0 1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 M e m o r y A d d r e s s 2 ( M A 2 )D a t a ( M A 2 ) READ-MODIFY-WRITE mode (successive address accessing) C S W R R D D A T A 1 0 1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 M e m o ry A d d re s s (M A ) D a ta (M A ) D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 1 ) D a ta (M A + 2 ) 15 January 10, 2001 HT1621 Command mode (command code : 1 0 0) C S W R D A T A 1 0 0 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 C o m m a n d 1 C o m m a n d ... C o m m a n d i C o m m a n d o r D a ta M o d e Mode (data and command mode) C S W R D A T A C o m m a n d o r D a ta M o d e A d d re s s & D a ta C o m m a n d o r D a ta M o d e A d d re s s a n d D a ta C o m m a n d o r D a ta M o d e A d d re s s a n d D a ta R D Note: It is recommended that the host controller should read in the data from the DATA line between the rising edge of the RD line and the falling edge of the next RD line. 16 January 10, 2001 HT1621 Application Circuits Host controller with an HT1621 display system C S * V D D R D W R m C * D A T A V R V L C D H T 1 6 2 1 B B Z R P ie z o IR Q B Z O S C I C lo c k O u t * O S C O C O M 0 ~ C O M 3 S E G 0 ~ S E G 3 1 E x te r n a l C o lc k 1 E x te r n a l C o lc k 2 1 /2 o r 1 /3 B ia s ; 1 /2 , 1 /3 o r 1 /4 D u ty O n - c h ip O S C L C D P a n e l C ry s ta l 3 2 7 6 8 H z Note: The connection of IRQ and RD pin can be selected depending on the requirement of the mC. The voltage applied to VLCD pin must be lower than VDD. Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW±20%. Adjust R (external pull-high resistance) to fit user s time base clock. 17 January 10, 2001 HT1621 Command Summary Name ID Command Code D/C Function Def. READ 1 1 0 A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM WRITE 1 0 1 A5A4A3A2A1A0D0D1D2D3 D Write data to the RAM READMODIFYWRITE 1 0 1 A5A4A3A2A1A0D0D1D2D3 D READ and WRITE to the RAM SYS DIS 1 0 0 0000-0000-X C Turn off both system oscillator and LCD bias generator SYS EN 1 0 0 0000-0001-X C Turn on system oscillator LCD OFF 1 0 0 0000-0010-X C Turn off LCD bias generator LCD ON 1 0 0 0000-0011-X C Turn on LCD bias generator TIMER DIS 1 0 0 0000-0100-X C Disable time base output Disable WDT time-out flag output WDT DIS 1 0 0 0000-0101-X C TIMER EN 1 0 0 0000-0110-X C Enable time base output WDT EN 1 0 0 0000-0111-X C Enable WDT time-out flag output TONE OFF 1 0 0 0000-1000-X C Turn off tone outputs TONE ON 1 0 0 0000-1001-X C Turn on tone outputs CLR TIMER 1 0 0 0000-11XX-X C Clear the contents of time base generator CLR WDT 1 0 0 0000-111X-X C Clear the contents of WDT stage XTAL 32K 1 0 0 0001-01XX-X C System clock source, crystal oscillator RC 256K 1 0 0 0001-10XX-X C System clock source, on-chip RC oscillator EXT 256K 1 0 0 0001-11XX-X C System clock source, external clock source C LCD 1/2 bias option ab=00: 2 commons option ab=01: 3 commons option ab=10: 4 commons option BIAS 1/2 1 0 0 0010-abX0-X BIAS 1/3 1 0 0 0010-abX1-X C LCD 1/3 bias option ab=00: 2 commons option ab=01: 3 commons option ab=10: 4 commons option TONE 4K 1 0 0 010X-XXXX-X C Tone frequency, 4kHz TONE 2K 1 0 0 011X-XXXX-X C Tone frequency, 2kHz IRQ DIS 1 0 0 100X-0XXX-X C Disable IRQ output 18 Yes Yes Yes Yes Yes January 10, 2001 HT1621 Name ID IRQ EN Command Code D/C 1 0 0 100X-1XXX-X Function C Enable IRQ output Def. F1 100 101X-X000-X C Time base/WDT clock output:1Hz The WDT time-out flag after: 4s F2 1 0 0 101X-X001-X C Time base/WDT clock output:2Hz The WDT time-out flag after: 2s F4 100 101X-X010-X C Time base/WDT clock output:4Hz The WDT time-out flag after: 1s F8 1 0 0 101X-X011-X C Time base/WDT clock output:8Hz The WDT time-out flag after: 1/2 s F16 1 0 0 101X-X100-X C Time base/WDT clock output:16Hz The WDT time-out flag after: 1/4 s F32 1 0 0 101X-X101-X C Time base/WDT clock output:32Hz The WDT time-out flag after: 1/8 s F64 1 0 0 101X-X110-X C Time base/WDT clock output:64Hz The WDT time-out flag after: 1/16 s F128 1 0 0 101X-X111-X C Time base/WDT clock output:128Hz Yes The WDT time-out flag after: 1/32 s TEST 1 0 0 1110-0000-X C Test mode, user don't use. NORMAL 1 0 0 1110-0011-X C Normal mode Yes , Note: X : Don t care A5~A0 : RAM addresses D3~D0 : RAM data D/C : Data/command mode Def. : Power on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from an on-chip 256kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 256kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1621 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1621. 19 January 10, 2001 HT1621 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holtek Semiconductor (Shanghai) Ltd. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 Holmate Technology Corp. 48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539 Tel: 510-252-9880 Fax: 510-252-9885 Copyright Ó 2001 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. 20 January 10, 2001