www.fairchildsemi.com FAN6550 2A DDR Bus Termination Regulator Features Description • • • • • • • • • • • • The FAN6550 switching regulator is designed to convert voltage supplies ranging from 2.3V to 4V into a desired output voltage or termination voltage for DDR SDRAM memory. The FAN6550 can be implemented to produce regulated output voltages in two different modes. In the default mode, when the VREF pin is open, the FAN6550 output voltage is 50% of the voltage applied to VCCQ. The FAN6550 can also be used to produce various user-defined voltages by forcing a voltage on the VREFIN pin. In this case, the output voltage follows the input VREFIN voltage. The switching regulator is capable of sourcing or sinking up to 2A of current while regulating an output VTT voltage to within 3% or less. Transient output currents of ±3A can also be accommodated. Can source and sink up to 2A continous, 3A peak No heatsink required Integrated Power MOSFETs Generates termination voltages for DDR SDRAM VREF input available for external voltage divider Separate voltages for VCCQ and PVDD Buffered VREF output VOUT of ±3% or less at 2A Minimum external components 0°C to 70°C operating range Shutdown for standby or suspend mode operation Thermal Shutdown ≈ 130ºC The FAN6550 can also be used in conjunction with series termination resisitors to provide an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs. Block Diagram 15 VCCQ 16 AVCC 14 1 VREFOUT 9 VDD 12 VDD SHDN 2 PVDD1 7 PVDD2 VL1 (VOUT) OSCILLATOR/ RAMP GENERATOR 3 – 200kΩ S + VREF BUFFER Q 6 VL2 (VOUT) – R Q + VREFIN 11 + 200kΩ AGND – ERROR AMP RAMP COMPARATOR 13 VFB 10 DGND 8 PGND2 PGND1 4 5 REV. 1.0.2 3/11/02 FAN6550 PRODUCT SPECIFICATION Pin Configuration FAN6550 16-Pin SOIC (M16) VDD 1 16 AVCC PVDD1 2 15 VCCQ VL1 3 14 VREFOUT PGND1 4 13 AGND PGND2 5 12 SHDN VL2 6 11 VREFIN PVDD2 7 10 VFB DGND 8 9 VDD TOP VIEW Pin Description 2 Pin Name Function 1 VDD 2 PVDD1 3 VL1 Output voltage/ inductor connection 4 PGND1 Ground for output power transistors 5 PGND2 Ground for output power transistors 6 VL2 Output voltage/inductor connection 7 PVDD2 Voltage supply for internal power transistors 8 DGND Digital ground Digital supply voltage Voltage supply for internal power transistors 9 VDD Digital supply voltage 10 VFB Input for external compensation feedback 11 VREFIN 12 SHDN Shutdown active low. CMOS input level 13 AGND Ground for internal reference voltage divider 14 VREFOUT 15 VCCQ Voltage reference for internal voltage divider 16 AVCC Analog voltage supply Input for external reference voltage Reference voltage output REV. 1.0.2 3/11/02 PRODUCT SPECIFICATION FAN6550 Absolute Maximum Ratings Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Parameter PVDD Voltage on Any Other Pin Average Switch Current (IAVG) Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance (θJA) Output Current, Source or Sink (peak) Min. Max. 4.5 VIN + 0.3 2.0 150 150 300 30 3.0 Units V V A °C °C °C °C/W A Min. 0 2.0 Max. 70 4.0 Units °C V 1.4 4.0 V GND – 0.3 -65 Operating Conditions Parameter Temperature Range PVDD Operating Range VCCQ Operating Range Electrical Characteristics Unless otherwise specified, AVCC = VDD = PVDD = 3.3V ±10%, TA = Operating Temperature Range (Note 1) Symbol Parameter Switching Regulator VTT Output Voltage, VTT (See Figure 1) Conditions IOUT = 0, VREF = open Note 2 IOUT = ±2A, VREF = open Note 2 VREFOUT Internal Resistor Divider IOUT = 0 Note 2 ZIN VREF Reference Pin Input Impedance Switching Frequency Offset Voltage VTT – VREFOUT Note 2 ∆VOFFSET Supply IQ Quiescent Current Buffer IREF Output Load Current Min. Typ. Max. Units VCCQ = 2.3V 1.12 1.15 1.18 VCCQ = 2.5V 1.22 1.25 1.28 VCCQ = 2.7V 1.32 1.35 1.38 VCCQ = 2.3V 1.09 1.15 1.21 VCCQ = 2.5V 1.19 1.25 1.31 VCCQ = 2.7V 1.28 1.35 1.42 VCCQ = 2.3V 1.139 1.15 1.162 VCCQ = 2.5V 1.238 1.25 1.263 VCCQ = 2.7V 1.337 1.35 1.364 VCCQ = 0 100 650 VCCA = 2.5V No Load VCCQ = 2.5 IOUT = 0, no load VCCQ = 2.5V IVCCQ IAVCC IAVCC SD IVDD IVDD SD IPVDD –20 6 0.5 0.2 0.25 0.2 100 3 V V V V V V V V V kΩ 20 kHz mV 10 1.0 0.5 1.0 1.0 250 µA mA mA mA mA µA mA Notes 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 2. AVCC, PVDD = 3.3V ±10% REV. 1.0.2 3/11/02 3 FAN6550 PRODUCT SPECIFICATION Functional Description VREF Input and Output The FAN6550 integrates two power MOSFETs that can be used to source and sink 2A of current while maintaining a tight voltage regulation. Using the external feedback, the output can be regulated well within 3% or less, depending on the external components chosen. Separate voltage supply inputs have been added to accommodate applications with various power supplies for the databus and power buses. The VREFIN input can be used to force a voltage at the outputs (Inputs section, above). The VREFOUT pin is an output pin that is driven by a small output buffer to provide the VREF signal to other devices in the system. The output buffer is capable of driving several output loads. The output buffer can handle 3mA. Other Supply Voltages Outputs Several inputs are provide for the supply voltages: PVDD1, PVDD2, AVCC, and VDD. The output voltage pins (VL1, VL2) are tied to the databus, address, or clock lines via an external inductor. See the Applications section for recommendations. Output voltage is determined by the VCCQ or VREFIN inputs. The PVDD1 and PVDD2 provide the power supply to the power MOSFETs. VDD provides the voltage supply to the digital sections, while AVCC supplies the voltage for the analog sections. Again, see the Applications section for recommendations. Inputs The input voltage pins (VCCQ or VREFIN) determine the output voltages (VL1 or VL2) . In the default mode, where the VREFIN pin is floating, the output voltage is 50% of the VCCQ input. VCCQ can be the reference voltage for the databus. Feedback Input The VFB pin is an input that can be used for closed loop compensation. This input is derived from the voltage output. See application section for recommendation. Output voltage can also be selected by forcing a voltage at the VREFIN pin. In this case, the output voltage follows the voltage at the VREFIN input. Simple voltage dividers can be used this case to produce a wide variety of output voltages between 2.3V to 4V. 2.5V TO 4V C8 0.1µF R2 100Ω C9 0.1µF R1 100Ω R3 100kΩ C5 470µF U1 FAN6550 1 TPI 2 L1 3.3µH C3 0.1µF VTT C1 820µF F2V OS-CON 4 5 C2 0.1µF C4 0.1µF TO SDRAMS 3 6 7 8 VDD AVCC PVDD1 VCCQ VL1 VREFOUT PGND1 AGND PGND2 SHDN VL2 VREFIN PVDD2 VFB DGND VDD 16 15 14 VCCQ VREFOUT 13 12 11 SHDN VREFIN 10 9 R4 100kΩ R5 1kΩ GND C7 1nF GND Figure 1. 4 REV. 1.0.2 3/11/02 PRODUCT SPECIFICATION FAN6550 Applications Bus Termination Solutions for Others Buses Using the FAN6550 for DDR Bus Termination Table 2 provides a summary of various bus termination VREF & VTT requirements. The FAN6550 can be used for those applications. The circuit schematic in Figure 1 shows a recommended approach for constructing a bus terminating solution for a DDR bus. This circuit can be used in PC memory and Graphics memory applications as shown in Figures 2 and 3. Note that the FAN6550 can provide the voltage reference (VREF) and terminating voltages (VTT). Using the layout as shown in Figures 4, 5, and 6, and measuring the VTT performance using the test setup as described in Figure 7, the FAN6550 delivered a VTT ± 20mV for 1A to 2A loads (see Figure 8). Table 1 provides a recommended parts list. 168/184/208-PIN DIMM CONNECTORS AND SDRAM/SGRAM MODULES TERMINATION RESISTORS PC CHIP SET NORTHBRIDGE DATA LINE, CLOCK LINES, ADDRESS LINES, CONTROL LINES TERMINATION RESISTORS VTT FAN6550 VREF Figure 2. Complete Termination Solution PC Main Memory (PC Motherboard) REV. 1.0.2 3/11/02 5 FAN6550 PRODUCT SPECIFICATION SO DIMM AND MODULES 3D GRAPHIC CHIP TERMINATION RESISTORS SGRAM DATA LINE, CLOCK LINES, ADDRESS LINES, CONTROL LINES TERMINATION RESISTORS VREF FAN6550 2.5V VOLTAGE REGULATOR VTT 5V OR 3.3V AGP/PCI BUS Figure 3. Complete Termination Solution Graphics Memory Bus – AGP Graphics Cards 6 REV. 1.0.2 3/11/02 PRODUCT SPECIFICATION FAN6550 Figure 4. Top Silk Figure 5. Top Layer REV. 1.0.2 3/11/02 Figure 6. Bottom Layer 7 FAN6550 PRODUCT SPECIFICATION 3.3V POWER SUPPLY V A ACTIVE CLAMP VDD VCCQ VCCQ SUPPLY FAN6550 EVAL VTT CURRENT SOURCE/SINK POWER SUPPLY GND V ITT A Figure 7. Test Circuit Setup VTT VARIANCE WITH VDD@ITT (VCCQ 2.5V) TESTED WITH EVAL PCB ITT 1.29 2A SINKING 1A SINKING 1.28 VTT (V) 0A SINKING 2A SOURCING 1.27 1A SOURCING 1.26 2.0 2.5 3.0 3.5 4.0 VDD (V) Figure 8. VTT Performance for DDR Bus 8 REV. 1.0.2 3/11/02 PRODUCT SPECIFICATION FAN6550 Table 1. Recommend Parts List for Figure 1. Item Qty Description Manufacturer / Part Number Designator Resistors 1 2 100Ω1210 SMD Panasonic/ERJ-8ENF1000V R1, R2 2 1 1kΩ 1210 SMD Panasonic/ERJ-8ENF1001V R5 3 2 100kΩ1210 SMD Panasonic/ERJ-8ENF1003V R3, R4 4 3 0.1µF 1210 Film SMD Panasonic/ECV3VB1E104K Panasonic/ECU-V1H104KBW C2, C8, C9 5 1 820µF 2V Solid Elect. SMD Sanyo/2SV820M Os Con C1 6 1 470µF 6.3V Solid Elect. SMD Sanyo/6SVP470M Os Con C5 7 1 1nF 1210 Film SMD Panasonic/ECU-V1H102KBM C7 8 2 0.1µF 0805 Film Panasonic/ECJ-2VF1C104Z C3, C4 9 1 FAN6550 Bus Terminator FAN6550M U1 1 3.3µH 5A inductor SMD Coilcraft/D03316P-332HC Pulse Eng./ P0751.332T Gowanda/SMP3316-331M XFMRS inc./XF0046-S4 L1 11 1 Scope probe socket Tektronics/131-4353-00 TP1 12 1 12 Pin breakaway strip Sullins/PTC36SAAN (36 PINS) I/O, standoffs Capacitors ICs Magnetics 10 Other Vendor List 1. AVX (207) 282-5111 2. Sanyo (619) 661-6835 3. Tektronix (408) 496-0800 4. Coilcraft (847) 639-6400 5. Pulse (800) 797-8573 6. Gowanda (716) 532-2234 7. Xfmrs Inc. (317) 834-1066 8. Panasonic (714) 373-7366 9. Digikey (800) 344-4539 REV. 1.0.2 3/11/02 9 FAN6550 PRODUCT SPECIFICATION Table 2. Termination Solutions Summary By Bus Type Bus Description Driving Method VDDQ VTT VREF Industry System Components FAN6550; Mode: VREF Input = 1.5V, VCC = 3.3V 300 to 500MHz Processor; PC Chipsets; GTLP 16xxx Buffers; Fairchild, Texas Instr. 2.5V FAN6550, ML6554CU, or ML6553CS; Mode: VREF Input = Floating or Forced, VCC = 3.3V DDR SDRAM; Hitachi, Fujitsu, NEC, Micro, Mitsubishi 2.5V 2.0V ML6553CS; Mode: VREF Input = Open, VCC = VDDQ nDRAM, RAMBUS, Intel, Toshiba VDDQ/2 3.3V ML6553CS; Mode: VREF Input = Open, VCC = VDDQ Processors or backplanes; LV-TTL SDRAM, EDO RAM GTL+ Gunning Transceiver Bus Plus Open Drain 3.3V Note 10 1.5V±10% Note12 1.0V±2% Note 11 DDR (SSTL-2) Series Stub Terminated Logic for 2V Symmetric Drive, Series Resistance 2.5V±10% 0.5x (VDDQ) ±3% RAMBUS RAMBUS Signaling Logic Open Drain None Specified LV-TTL Low Voltage TTL Logic or PECL or 3.3V VME Symmetric Drive 3.3±10% 10 Fairchild Solutions REV. 1.0.2 3/11/02 PRODUCT SPECIFICATION FAN6550 Mechanical Dimensions Inches (Millimeters) Package: M16 16-Pin SOIC Inches Symbol Min. A A1 B C D E e H h L N α ccc Millimeters Max. Min. 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.81 4.00 1.27 BSC .228 .010 .016 5.80 0.25 0.40 16 6.20 0.50 1.27 16 0° 8° 0° 8° — .004 — 0.10 16 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. Max. .053 .069 .004 .010 .013 .020 .0075 .010 .386 .394 .150 .158 .050 BSC .244 .020 .050 Notes: Notes 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals. 3 6 9 E 1 H 8 h x 45° D C A1 A e B SEATING PLANE –C– LEAD COPLANARITY α L ccc C REV. 1.0.2 3/11/02 11 FAN6550 PRODUCT SPECIFICATION Ordering Information Part Number Temperature Range Package Packing FAN6550M 0°C to 70°C 16-Pin SOIC (M16) Rails FAN6550MX 0°C to 70°C 16-Pin SOIC (M16) Tape and Reel DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury of the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 3/11/02 0.0m 002 Stock#DS30006550 2002 Fairchild Semiconductor Corporation