MICRO-LINEAR ML6554CU

November 1999
PRELIMINARY
FEATURING
P
POWER SO
ance
High-Perform
age
ipation Pack
Thermal Diss
ML6554
3A Bus Termination Regulator
GENERAL DESCRIPTION
FEATURES
The ML6554 switching regulator is designed to convert
voltage supplies ranging from 2.3V to 4V into a desired
output voltage or termination voltage for various
applications. The ML6554 can be implemented to
produce regulated output voltages in two different modes.
In the default mode, when the VREF pin is open, the
ML6554 output voltage is 50% of the voltage applied to
VCCQ. The ML6554 can also be used to produce various
user-defined voltages by forcing a voltage on the VREFIN
pin. In this case, the output voltage follows the input
VREFIN voltage. The switching regulator is capable of
sourcing or sinking up to 3A of current while regulating an
output VTT voltage to within 3% or less.
■
Power SOP package
■
Can source and sink up to 3A, no heat sink required
■
Integrated Power MOSFETs
■
Generates termination voltages for SSTL-2 SDRAM,
SGRAM, or equivalent memories
■
Generates termination voltages for active termination
schemes for GTL+, Rambus, VME, LV-TTL, PECL and
other high speed logic
■
VREF input available for external voltage divider
■
Separate voltages for VCCQ and PVDD
■
Buffered VREF output
■
VOUT of ±3% or less at 3A
■
Minimum external components
■
Shutdown for standby or suspend mode operation
■
Thermal Shutdown » 130ºC
The ML6554, used in conjunction with series termination
resistors, provides an excellent voltage source for active
termination schemes of high speed transmission lines as
those seen in high speed memory buses and distributed
backplane designs. The voltage output of the regulator
can be used as a termination voltage for other bus
interface standards such as SSTL, CMOS, Rambus™,
GTL+, VME, LV-CMOS, LV-TTL, and PECL.
BLOCK DIAGRAM
15
VCCQ
16
AVCC
14
1
VREFOUT
9
VDD
12
VDD
SHDN
2
PVDD1
7
VL1
(VOUT)
OSCILLATOR/
RAMP
GENERATOR
200kΩ
3
+
S
–
VREF BUFFER
11
PVDD2
–
R
+
VREFIN
+
200kΩ
AGND
–
ERROR AMP
Q
VL2
(VOUT)
Q
6
RAMP
COMPARATOR
13
10
VFB
8
DGND
4
PGND1
5
PGND2
1
ML6554
PIN CONFIGURATION
ML6554
16-Pin PSOP (U16)
VDD
1
16
AVCC
PVDD1
2
15
VCCQ
VL1
3
14
VREFOUT
PGND1
4
13
AGND
PGND2
5
12
SHDN
VL2
6
11
VREFIN
PVDD2
7
10
VFB
DGND
8
9
VDD
TOP VIEW
PIN DESCRIPTION
PIN
NAME
FUNCTION
1
V DD
2
PIN
NAME
FUNCTION
Digital supply voltage
9
V DD
Digital supply voltage
PVDD1
Voltage supply for internal power
transistors
10
V FB
Input for external compensation
feedback
3
VL1
Output voltage/ inductor connection
11
VREFIN
Input for external reference voltage
4
P GND1
Ground for output power transistors
12
SHDN
Shutdown active low. CMOS input
level
P GND2
Ground for output power transistors
13
AGND
6
VL2
Output voltage/inductor connection
Ground for internal reference voltage
divider
7
PVDD2
Voltage supply for internal power
transistors
14
VREFOUT
Reference voltage output
15
8
D GND
Digital ground
VCCQ
Voltage reference for internal voltage
divider
16
AVCC
Analog voltage supply
5
2
NOVEMBER, 1999
ML6554
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Lead Temperature (Soldering, 10 sec) ..............................
Thermal Resistance (qJC)(Note 3) ........................... 2°C/W
Output Current, Source or Sink ................................. 3.0A
PV DD .......................................................................................... 5.0V
Voltage on Any Other Pin ...... GND – 0.3V to VIN + 0.3V
Average Switch Current (IAVG) .................................. 3.0A
Junction Temperature .......................................................
Storage Temperature Range .............................................
OPERATING CONDITIONS
Temperature Range ....................................... 0°C to 70°C
PVDD Operating Range ................................ 2.0V to 4.0V
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, PVDD = 3.3V±10%, TA = Operating Temperature Range (Note 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING REGULATOR
V TT
Output Voltage, SSTL_2
IOUT = 0,
VCCQ = 2.3V
1.12
1.15
1.18
V
(See Figure 1)
VREF = open
VCCQ = 2.5V
1.22
1.25
1.28
V
Note 2
VCCQ = 2.7V
1.32
1.35
1.38
V
IOUT = ±3A,
VCCQ = 2.3V
1.09
1.15
1.21
V
VREF = open
VCCQ = 2.5V
1.19
1.25
1.31
V
Note 2
VCCQ = 2.7V
1.28
1.35
1.42
V
IOUT = 0
VCCQ = 2.3V
1.139
1.15
1.162
V
Note 2
VCCQ = 2.5V
1.238
1.25
1.263
V
VCCQ = 2.7V
1.337
1.35
1.364
V
VREFOUT Internal Resistor Divider
ZIN
VREF Reference Pin Input Impedance
Note 2
VCCQ = 0
Switching Frequency
DVOFFSET Offset Voltage VTT – VREFOUT
VCCA = 2.5V No Load
VCCQ = 2.5
100
kW
650
kHz
–12.5
12.5
mV
SUPPLY
IQ
Quiescent Current
IOUT = 0, no load
IVCCQ
10
µA
I AVCC
500
µA
I DVCC
7
mA
BUFFER
IREF
Output Load Current
3
mA
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: AVCC, PVDD = 3.3V ±10%
Note 3: Infinite heat sink
NOVEMBER, 1999
3
ML6554
FUNCTIONAL DESCRIPTION
This switching regulator is capable of sinking and sourcing
3A of current without an external heatsink. The ML6554
uses a power surface mount package (PSOP) that includes
an integrated heat slug. The heat can be piped through the
bottom of the device and onto the PCB (Figure 2).
Output voltage can also be selected by forcing a voltage
at the VREFIN pin. In this case, the output voltage follows
the voltage at the VREFIN input. Simple voltage dividers
can be used this case to produce a wide variety of output
voltages between 2.3V to 4V.
The ML6554 integrates two power MOSFETs that can be
used to source and sink 3A of current while maintaining a
tight voltage regulation. Using the external feedback, the
output can be regulated well within 3% or less,
depending on the external components chosen. Separate
voltage supply inputs have been added to accommodate
applications with various power supplies for the databus
and power buses.
VREF INPUT AND OUTPUT
OUTPUTS
OTHER SUPPLY VOLTAGES
The output voltage pins (VL1, VL2) are tied to the databus,
address, or clock lines via an external inductor. See the
Applications section for recommendations. Output
voltage is determined by the VCCQ or VREFIN inputs.
Several inputs are provide for the supply voltages: PVDD1,
PVDD2, AVCC, and VDD.
The VREFIN input can be used to force a voltage at the
outputs (Inputs section, above). The VREFOUT pin is an
output pin that is driven by a small output buffer to
provide the VREF signal to other devices in the system.
The output buffer is capable of driving several output
loads. The output buffer can handle 3mA.
The PVDD1 and PVDD2 and provide the power supply to
the power MOSFETs. VDD provides the voltage supply to
the digital sections, while AVCC supplies the voltage for
the analog sections. Again, see the Applications section
for recommendations.
INPUTS
The input voltage pins (VCCQ or VREFIN) determine the
output voltages (VL1 or VL2) . In the default mode, where
the VREFIN pin is floating, the output voltage is 50% of
the VCCQ input. VCCQ can be the reference voltage for the
databus.
FEEDBACK INPUT
The VFB pin is an input that can be used for closed loop
compensation. This input is derived from the voltage
output. See application section for recommendation.
2.5V TO 4V
C8 0.1µF
R2 100Ω
C9 0.1µF
R1 100Ω
R3
100kΩ
220µF
220µF
U1
ML6554
1
TPI
2
L1 3.3µH C3 0.1µF
VTT
C1
820µF
F2V
OS-CON
4
5
C2
0.1µF
C4 0.1µF
TO SDRAMS
3
6
7
8
VDD
AVCC
PVDD1
VCCQ
VL1
VREFOUT
PGND1
AGND
PGND2
SHDN
VL2
VREFIN
PVDD2
VFB
DGND
VDD
16
15
14
VCCQ
VREFOUT
13
12
11
SHDN
VREFIN
10
9
R4 100kΩ
R5 1kΩ
C7 1nF
GND
GND
Figure 1.
4
NOVEMBER, 1999
ML6554
APPLICATIONS
USING THE ML6554 FOR SSTL BUS TERMINATION
The circuit schematic in Figure 1 shows a recommended
approach for an constructing a bus terminating solution for
an SSTL-2 bus. This circuit can be used in PC memory and
Graphics memory applications as shown in Figures 3 and
4. Note that the ML6554 can provide the voltage
reference (VREF) and terminating voltages (VTT). Using
the layout as shown in Figures 5, 6, and 7, and measuring
the VTT performance using the test setup as described in
Figure 8, the ML6554 delivered a VTT ± 20mV for 1A to
3A loads (see Figure 9). Table 1 provides a recommended
parts list. For more recent Applications Notes or
Evaluation Boards contact Micro Linear.
Airflow is not likely to be needed in the operation of this
device (assuming a board layout similar to that described
above). The power handling performance of the PSOP
package is shown by a study of the package manufacturer
for various airflow vs. qJA conditions in Figure 10.
BUS TERMINATION SOLUTIONS FOR OTHER BUSES
Table 2 provides a summary of various bus termination
VREF & VTT requirements. The ML6554 can be used for
those applications.
POWER HANDLING CAPABILITY OF THE PSOP PACKAGE
Using the board layout shown in Figures 5,6, and 7;
soldering the ML6554 to the board at zero LFPM the
temperature around the package measured 55
ºC for 3A
loads. Note that a 1ounce copper plane was used in the
board construction.
HEAT SLUG
Figure 2. Cutaway view of PSOP Package
NOVEMBER, 1999
5
ML6554
168/184/208-PIN DIMM CONNECTORS
AND SDRAM/SGRAM MODULES
TERMINATION
RESISTORS
PC CHIP SET
NORTHBRIDGE
DATA LINE, CLOCK LINES,
ADDRESS LINES, CONTROL LINES
TERMINATION
RESISTORS
VTT
ML6554
VREF
Figure 3. Complete Termination Solution PC Main Memory (PC Motherboard)
6
NOVEMBER, 1999
ML6554
SO DIMM
AND MODULES
3D
GRAPHIC CHIP
TERMINATION
RESISTORS
SGRAM
DATA LINE, CLOCK LINES,
ADDRESS LINES, CONTROL LINES
TERMINATION
RESISTORS
VREF
ML6554
2.5V
VOLTAGE
REGULATOR
VTT
5V OR 3.3V
AGP/PCI BUS
Figure 4. Complete Termination Solution Graphics Memory Bus – AGP Graphics Cards
NOVEMBER, 1999
7
ML6554
Figure 5. Top Silk
Figure 6. Top Layer
8
Figure 7. Bottom Layer
NOVEMBER, 1999
ML6554
3.3V POWER
SUPPLY
V
A
ACTIVE
CLAMP
VDD
VCCQ
VCCQ
SUPPLY
ML6554
EVAL
VTT
CURRENT SOURCE/SINK
POWER SUPPLY
GND
A
Figure 8. Test Circuit Setup
VTT VARIANCE WITH VDD@ITT (VCCQ 2.5V)
TESTED WITH EVAL PCB
ITT
1.29
3A SINKING
2A SINKING
1.28
1A SINKING
VTT (V)
V
ITT
0A SINKING
1.27
3A SOURCING
2A SOURCING
1.26
2.0
2.5
3.0
3.5
4.0
1A SOURCING
VDD (V)
Figure 9. VTT Performance for SSTL-2 Bus
NOVEMBER, 1999
9
ML6554
ITEM
QTY
DESCRIPTION
MANUFACTURER / PART NUMBER
DESIGNATOR
RESISTORS
1
2
3
CAPACITORS
2
1
2
100W1210 SMD
1kW 1210 SMD
100kW1210 SMD
Panasonic/ERJ-8ENF1000V
Panasonic/ERJ-8ENF1001V
Panasonic/ERJ-8ENF1003V
R1, R2
R5
R3, R4
4
3
0.1µF 1210 Film SMD
C2, C8, C9
5
6
7
8
ICS
1
2
1
2
820µF 2V Solid Elect. SMD
330µF Tant 6.3V 100mW
1nF 1210 Film SMD
0.1µF 0805 Film
Panasonic/ECV3VB1E104K
Panasonic/ECU-V1H104KBW
Sanyo/ 2SV820M Os Con
AVX/ TPSE337M006R0100
Panasonic/ECU-V1H102KBM
Panasonic/ECJ-2VF1C104Z
C1
C5, C6
C7
C3, C4
9
1
ML6554 Bus Terminator
Power SOP Package
ML6554CU
U1
1
3.3µH 5A inductor SMD
Coilcraft/D03316P-332HC
Pulse Eng./ P0751.332T
Gowanda/SMP3316-331M
XFMRS inc./XF0046-S4
L1
1
1
Scope probe socket
12 Pin breakaway strip
Tektronics/131-4353-00
Sullins/PTC36SAAN (36 PINS)
TP1
I/O, standoffs
MAGNETICS
10
OTHER
11
12
Table 1. Recommend Parts List for SSTL-2 Termination Circuit
VENDOR LIST
1. AVX
(207) 282-5111
2. Sanyo
(619) 661-6835
3. Tektronix
(408) 496-0800
4. Coilcraft
(847) 639-6400
5. Pulse
(800) 797-8573
6. Gowanda
(716) 532-2234
7. Xfmrs Inc.
(317) 834-1066
8. Panasonic
(714) 373-7366
9. Digikey
(800) 344-4539
10
NOVEMBER, 1999
ML6554
60
40
40
θJA (ºC/W)
ΘJA (ºC/W)
60
20
20
16Ld PSOP2
2.3x3.1mm PAD
1.9mm DIE
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
16Ld PSOP2
2.3x3.1mm PAD
1.9mm DIE @ 0.8 WATTS
0
0
200
100
300
400
POWER (W)
AIR VELOCITY (LFPM)
NATURAL CONVECTION ΘJA TEST RESULTS
1.27mm PITCH PowerSOP™ 2
SLUG SOLDERED
FORCED CONVECTION ΘJA TEST RESULTS
1.27mm PITCH PowerSOP™ 2
SLUG SOLDERED
500
Figure 10. Graphical Results Summary – 1S2P Test Board
DRAWING NUMBER
ENG-CB-1007 REV A
Applicable Jedec Spec
JC 51-X (Note 1)
(Sroposed Spec)
Substrate Material
FR-4
Dimensions (LxW) (Overall)
114.3 x 76.2mm
Dimensions (LxW) (Metallization)
55 x 65mm
Dimensions (LxW) (Inner Planes)
73 x 73mm
Thickness
1.6 mm
Pitch
1.27mm
Stackup (# Signal Layers, # Cu Planes)
1S2P
Cu Trace Coverage (Signal Layer)
12%
Cu Coverage (Internal Layer)
100%
Trace Width (Spec/Measured)
235.5±25.5/288µm
Trace Cu Thickness (Spec/Measured)
70±14/67µm
Inner Cu Thickness (Spec/Measured)
35±3.5/31µm
Build #
C1797
Note 1: Proposed Spec "Thermal Test Board with Two Internal Solid Copper Planes for leaded Surface Mount Packages".
Figure 11. Test Board Layout for QJA vs. Airflow
NOVEMBER, 1999
11
ML6554
BUS
DESCRIPTION
DRIVING
METHOD
GTL+
Gunning
Transceiver
Bus Plus
Open Drain
SSTL_2
Series Stub
Terminated
Logic for 2V
RAMBUS
LV-TTL
VDDQ
VTT
VREF
MICRO
LINEAR
SOUTIONS
5v or 3.3V 1.5V±10%
Note 10
Note12
1.0V±2%
Note 11
ML6554CU;
Mode: VREF
Input = 1.5V,
VCC = 5V
Symmetric
Drive, Series
Resistance
2.5V±10% 0.5x(VDDQ)
±3%
2.5V
RAMBUS
Signaling
Logic
Open Drain
None
Specified
2.5V
2.0V
Low Voltage
TTL Logic or
PECL or
3.3V VME
Symmetric
Drive
3.3±10%
VDDQ/2
3.3V
ML6554CU
or ML6553CS;
Mode: VREF
Input = Floating
or Forced,
VCC = 3.3V
ML6553CS;
Mode: VREF
Input = Open,
VCC = VDDQ
ML6553CS;
Mode: VREF
Input = Open,
VCC = VDDQ
Table 2. Termination Solutions Summary By Buss Type
12
NOVEMBER, 1999
INDUSTRY
SYSTEM
COMPONENTS
300 to 500MHz
Processor;
PC Chipsets;
GTLP 16xxx
Buffers;
Fairchild,
Texas Instr.
SSTL SDRAM;
Hitachi,
Fujitsu,
NEC, Micro,
Mitsubishi
nDRAM,
RAMBUS,
Intel, Toshiba
Processors or
backplanes;
LV-TTL
SDRAM,
EDO RAM
ML6554
PHYSICAL DIMENSIONS
inches (millimeters)
Package: U16
16-Pin PSOP
0.386 - 0.393
9.80 - 9.98
HEAT SLUG
DIMENSIONS:
0.079 × 0.279
(2.01 × 7.09)
16
PIN 1 ID
HEAT SLUG
0.150 - 0.157 0.230 - 0.244
3.81 - 3.99
(5.84 - 6.20)
1
0.017 - 0.027
0.43 - 0.69
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.061 - 0.068
(1.55 - 1.73)
0º - 8º
0.055 - 0.061
(1.40 - 1.55)
0.014 - 0.019
(0.35 - 0.49)
SEATING PLANE
0.00 - 0.004
(0.127 - 0.25)
0.016 - 0.035
(0.41 - 0.89)
0.0075 - 0.0098
(0.19 - 0.25)
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML6554CU
0°C to 70°C
16-Pin PSOP (U16)
Micro Linear Corporation
2092 Concourse Drive
San Jose, CA 95131
Tel: (408) 433-5200
Fax: (408) 432-0295
www.microlinear.com
© Micro Linear 1999.
property of their respective owners.
is a registered trademark of Micro Linear Corporation. All other trademarks are the
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116;
5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376;
5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174;
5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223;
5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.
Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents
of this publication and reserves the right to make changes to specifications and product descriptions at any time without
notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted
by this document. The circuits contained in this document are offered as possible applications only. Particular uses or
applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged
to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including
liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property
right. Micro Linear products are not designed for use in medical, life saving, or life sustaining applications.
DS6554-01
NOVEMBER, 1999
13
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