ispLSI 1024/883 ® In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 4000 PLD Gates — 48 I/O Pins, Six Dedicated Inputs — 144 Registers — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Fast Random Logic — Security Cell Prevents Unauthorized Copying • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 60 MHz Maximum Operating Frequency — tpd = 20 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile E2CMOS Technology — 100% Tested • IN-SYSTEM PROGRAMMABLE Output Routing Pool D Q A1 A2 Logic A3 Array C6 C5 D Q D Q C4 GLB C3 A4 D Q C2 A5 C1 A6 A7 Global Routing Pool (GRP) B0 B1 B2 B3 B4 B5 B6 B7 C0 CLK Output Routing Pool — In-System Programmable™ (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging • COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity 0139-A-isp Description The ispLSI 1024/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD883. This military grade device contains 144 Registers, 48 Universal I/O pins, six Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1024/883 features 5-Volt in-system programmability and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. • ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms unctional Block C7 A0 Output Routing Pool Features The basic unit of logic on the ispLSI 1024/883 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. C7 (see figure 1). There are a total of 24 GLBs in the ispLSI 1024/883 device. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Diagram Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 1024MIL_01 1 September 2000 Specifications ispLSI 1024/883 Functional Block Diagram Figure 1.ispLSI 1024/883 Functional Block Diagram RESET Generic Logic Blocks (GLBs) IN 5 IN 4 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 C6 I/O 44 C5 A2 C4 Global Routing Pool (GRP) A3 C3 A4 C2 A5 I/O 43 I/O 42 I/O 41 lnput Bus Output Routing Pool (ORP) I/O 8 A1 Input Bus I/O 4 I/O 5 I/O 6 I/O 7 A0 I/O 47 I/O 46 I/O 45 Output Routing Pool (ORP) I/O 0 I/O 1 I/O 2 I/O 3 C7 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 C1 A6 C0 A7 SDI/IN 0 SDO/IN 1 B0 B1 Megablock B2 B3 B4 B5 B6 B7 Clock Distribution Network Output Routing Pool (ORP) CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1 Input Bus ispEN SCLK/IN 2 MODE/IN 3 I/O I/O I/O I/O 16 17 18 19 I/O I/O I/O I/O 20 21 22 23 I/O I/O I/O I/O 24 25 26 27 I/O I/O I/O I/O 28 29 30 31 Y Y Y Y 0 1 2 3 0139D_1024.eps The device also has 48 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. The GRP has as its inputs the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1024/883 device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (B4 on the ispLSI 1024/883 device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device. Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. The I/O cells within the Megablock also share a common Output Enable (OE) signal. The ispLSI 1024/883 device contains three of these Megablocks. 2 Specifications ispLSI 1024/883 Absolute Maximum Ratings 1 Supply Voltage Vcc ...................................-0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Conditions SYMBOL PARAMETER MIN. MAX. 4.5 5.5 VCC Supply Voltage VIL VIH Input Low Voltage 0 0.8 Input High Voltage 2.0 Vcc + 1 Military/883 TC = -55°C to +125°C UNITS V V 0005A mil.eps Capacitance (TA=25oC, f=1.0 MHz) MAXIMUM1 UNITS TEST CONDITIONS Dedicated Input Capacitance 10 pf VCC=5.0V, VIN=2.0V I/O and Clock Capacitance 10 pf VCC=5.0V, VI/O, VY=2.0V SYMBOL PARAMETER C1 C2 Table 2- 0006mil 1. Characterized but not 100% tested. Data Retention Specifications PARAMETER MINIMUM MAXIMUM 20 — Years 10000 — Cycles Data Retention Erase/Reprogram Cycles UNITS Table 2- 0008B 3 Specifications ispLSI 1024/883 Switching Test Conditions Input Pulse Levels Figure 2. Test Load GND to 3.0V ≤ 3ns 10% to 90% Input Rise and Fall Time Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load + 5V R1 See figure 2 Device Output 3-state levels are measured 0.5V from steady-state active level. Test Point Table 2- 0003 CL* R2 Output Load Conditions (see figure 2) Test Condition R1 R2 CL 470Ω 390Ω 35pF Active High ∞ 390Ω 35pF Active Low 470Ω 390Ω 35pF Active High to Z at VOH - 0.5V ∞ 390Ω 5pF Active Low to Z 470Ω 390Ω 5pF A B C *CL includes Test Fixture and Probe Capacitance. at VOL + 0.5V Table 2- 0004A DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL CONDITION PARAMETER MIN. TYP. 3 MAX. UNITS VOL VOH IIL IIH IIL-isp IIL-PU IOS1 Output Low Voltage IOL =8 mA – – 0.4 V Output High Voltage IOH =-4 mA 2.4 – – V Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) – – -10 µA Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC – – 10 µA isp Input Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) – – -150 µA I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 µA Output Short Circuit Current VCC = 5V, VOUT = 0.5V – – -200 mA ICC2,4 Operating Power Supply Current VIL = 0.5V, VIH = 3.0V – 135 215 mA fTOGGLE = 1 MHz 1. One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using six 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25oC. 4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC. 0007A-24 mil 4 Specifications ispLSI 1024/883 External Timing Parameters Over Recommended Operating Conditions 5 2 PARAMETER TEST # COND. tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 ten tdis twh twl tsu5 th5 -60 DESCRIPTION1 UNITS MIN. MAX. A 1 Data Propagation Delay, 4PT bypass, ORP bypass – 20 A 2 Data Propagation Delay, Worst Case Path – 25 ns A 3 Clock Frequency with Internal Feedback 3 60 – MHz – 4 Clock Frequency with External Feedback (tsu2 1+ tco1) 38 – MHz Toggle 4 ns – 5 Clock Frequency, Max 83 – MHz – 6 GLB Reg. Setup Time before Clock, 4PT bypass 9 – ns A 7 GLB Reg. Clock to Output Delay, ORP bypass – 13 ns – 8 GLB Reg. Hold Time after Clock, 4 PT bypass 0 – ns – 9 GLB Reg. Setup Time before Clock 13 – ns – 10 GLB Reg. Clock to Output Delay – 16 ns – 11 GLB Reg. Hold Time after Clock 0 – ns A 12 Ext. Reset Pin to Output Delay – 22.5 ns – 13 Ext. Reset Pulse Duration 13 – ns B 14 Input to Output Enable – 24 ns C 15 Input to Output Disable – 24 ns – 16 Ext. Sync. Clock Pulse Duration, High 6 – ns – 17 Ext. Sync. Clock Pulse Duration, Low 6 – ns – 18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) 2.5 – ns – 19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 8.5 – ns Table 2-0030-24 mil 1. 2. 3. 4. 5. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-Bit loadable counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions Section. 5 Specifications ispLSI 1024/883 Internal Timing Parameters1 PARAMETER 2 # -60 DESCRIPTION UNITS MIN. MAX. Inputs tiobp tiolat tiosu tioh tioco tior tdin GRP tgrp1 tgrp4 tgrp8 tgrp12 tgrp16 tgrp24 GLB t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgr tptre tptoe tptck ORP torp torpbp – 2.7 ns – 4.0 ns 7.3 – ns 1.3 – ns I/O Register Clock to Out Delay – 4.0 ns 25 I/O Register Reset to Out Delay – 3.3 ns 26 Dedicated Input Delay – 5.3 ns 27 GRP Delay, 1 GLB Load – 2.0 ns 28 GRP Delay, 4 GLB Loads – 2.7 ns 29 GRP Delay, 8 GLB Loads – 4.0 ns 30 GRP Delay, 12 GLB Loads – 5.0 ns 31 GRP Delay, 16 GLB Loads – 6.0 ns 32 GRP Delay, 24 GLB Loads – 8.3 ns 33 4 Product Term Bypass Path Delay – 8.6 ns 34 1 Product Term/XOR Path Delay – 9.3 ns 35 20 Product Term/XOR Path Delay – 10.6 ns 36 XOR Adjacent Path Delay3 – 12.7 ns 37 GLB Register Bypass Delay – 1.3 ns 38 GLB Register Setup Time before Clock 1.3 – ns 39 GLB Register Hold Time after Clock 6.0 – ns 40 GLB Register Clock to Output Delay – 2.7 ns 41 GLB Register Reset to Output Delay – 3.3 ns 42 GLB Product Term Reset to Register Delay – 13.3 ns 43 GLB Product Term Output Enable to I/O Cell Delay – 12.0 ns 44 GLB Product Term Clock Delay 4.6 9.9 ns 45 ORP Delay – 3.3 ns 46 ORP Bypass Delay – 0.7 ns 20 I/O Register Bypass 21 I/O Latch Delay 22 I/O Register Setup Time before Clock 23 I/O Register Hold Time after Clock 24 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Lattice Hard Macros. 6 Specifications ispLSI 1024/883 Internal Timing Parameters1 PARAMETER 2 # -60 DESCRIPTION UNITS MIN. MAX. Outputs tob toen todis Clocks tgy0 tgy1/2 tgcp tioy2/3 tiocp 47 Output Buffer Delay – 4.0 ns 48 I/O Cell OE to Output Enabled – 6.7 ns 49 I/O Cell OE to Output Disabled – 6.7 ns 50 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 6.0 6.0 ns 51 Clock Delay, Y1 or Y2 to Global GLB Clock Line 4.6 7.3 ns 52 Clock Delay, Clock GLB to Global GLB Clock Line 1.3 6.6 ns 53 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line 4.6 7.3 ns 54 Clock Delay, Clock GLB to I/O Cell Global Clock Line 1.3 6.6 ns – 12.0 ns Global Reset tgr 55 Global Reset to GLB and I/O Registers 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 7 Specifications ispLSI 1024/883 ispLSI Timing Model I/O Cell GRP GLB ORP I/O Cell Feedback Ded. In I/O Pin (Input) #55 #26 I/O Reg Bypass 4 PT Bypass GLB Reg Bypass ORP Bypass #20 #28 #33 #37 #46 Input D Register Q RST #21 - 25 GRP Loading Delay #27, 29, 30, 31, 32 20 PT XOR Delays GLB Reg Delay ORP Delay GRP 4 D Clock Distribution #51, 52, 53, 54 Q RST #55 Reset Y1,2,3 #34, 35, 36 #38, 39, 40, 41 Control RE PTs OE #42, 43, CK 44 #50 Y0 Derivations of tsu, th and tco from the Product Term Clock1 tsu = Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) = (#20 + #28 + #35) + (#38) - (#20 + #28 + #44) 7.3 ns = (2.7 + 2.7 + 10.6) + (1.3) - (2.7 + 2.7 + 4.6) th = Clock (max) + Reg h - Logic = (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) = (#20 + #28 + #44) + (#39) - (#20 + #28 + #35) 5.3 ns = (2.7 + 2.7 + 9.9) + (6.0) - (2.7 + 2.7 + 10.6) tco = Clock (max) + Reg co + Output = (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) = (#20 + #28 + #44) + (#40) + (#45 + #47) 25.3 ns = (2.7+ 2.7 +9.9) + (2.7) + (3.3 + 4.0) Derivations of tsu, th and tco from the Clock GLB1 tsu = Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) = (#20 + #28 + #35) + (#38) - (#50 + #40 + #52) 7.3 ns = (2.7 + 2.7 + 10.6) + (1.3) - (6.0 + 2.7 + 1.3) th = Clock (max) + Reg h - Logic = (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) = (#50 + #40 + #52) + (#39) - (#20 + #28 + #35) 5.3 ns = (6.0 + 2.7 + 6.6) + (6.0) - (2.7 + 2.7 + 10.6) tco = Clock (max) + Reg co + Output = (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) = (#50 + #40 + #52) + (#40) + (#45 + #47) 25.3 ns = (6.0 + 2.7 + 6.6) + (2.7) + (3.3 + 4.0) 1. Calculations are based upon timing specifications for the ispLSI 1024-60. 8 #45 #47 I/O Pin (Output) #48, 49 Specifications ispLSI 1024/883 Maximum GRP Delay vs GLB Loads ispLSI 1024-60 GRP Delay (ns) 6 5 4 3 2 1 0 4 8 GLB Loads 12 16 0126A-80-24-mil.eps Power Consumption Power consumption in the ispLSI 1024/883 device depends on two primary factors: the speed at which the device is operating, and the number of Product Terms used. Figure 3 shows the relationship between power and operating speed. Figure 3. Typical Device Power Consumption vs fmax 200 ispLSI 1024 ICC (mA) 150 100 50 0 10 20 30 40 50 60 70 80 fmax (MHz) Notes: Configuration of Six 16-bit Counters Typical Current at 5V, 25˚C ICC can be estimated for the ispLSI 1024 using the following equation: ICC = 42 + (# of PTs * 0.45) + (# of nets * Max. freq * 0.008) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127A-24-80-isp 9 Specifications ispLSI 1024/883 Pin Description NAME JLCC PIN NUMBERS 24, 28, 32, 39, 43, 47, 58, 62, 66, 5, 9, 13, 25, 29, 33, 40, 44, 48, 59, 63, 67, 6, 10, 14 DESCRIPTION Input/Output Pins - These are the general purpose I/O pins used by the logic array. I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 I/O 32 - I/O 35 I/O 36 - I/O 39 I/O 40 - I/O 43 I/O 44 - I/O 47 22, 26, 30, 37, 41, 45, 56, 60, 64, 3, 7, 11, 23, 27, 31, 38, 42, 46, 57, 61, 65, 4, 8, 12, IN 4 - IN 5 2, 15 ispEN 19 SDI/IN 01 21 MODE/IN 31 55 SDO/IN 11 34 SCLK/IN 21 49 NC2 — No Connect RESET 20 Y0 16 Y1 54 Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Y2 51 Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Y3 50 Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. GND 1, 18, 35, 52 Ground (GND) VCC 17, 36, 53, 68 VCC Input - These pins are dedicated input pins to the device. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input - This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 is also used as one of the two control pins for the isp state machine. It is a dedicated input pin when ispEN is logic high. Input - This pin performs two functions. When ispEN is logic low, it functions as pin to control the operation of the isp state machine. It is a dedicated input pin when ispEN is logic high. Output/Input - This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. It is a dedicated input pin when ispEN is logic high. Input - This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. It is a dedicated input pin when ispEN is logic high. 1. Pins have dual function capability. 2. NC pins are not to be connected to any active signals, Vcc or GND. 10 Table 2 - 0002C-24 mil Specifications ispLSI 1024/883 Pin Configuration 2 4 3 I/O 31 I/O 30 I/O 29 IN 4 GND 5 I/O 32 I/O 38 I/O 37 I/O 36 6 7 I/O 33 I/O 39 8 I/O 35 I/O 34 I/O 41 I/O 40 9 VCC I/O 42 ispLSI 1024/883 68-Pin JLCC Pinout Diagram 1 68 67 66 65 64 63 62 61 I/O 43 10 60 I/O 28 I/O 44 I/O 45 11 59 12 58 I/O 27 I/O 26 I/O 46 13 57 I/O 25 I/O 47 14 56 I/O 24 IN 5 15 55 IN 3/MODE1 Y0 16 54 Y1 VCC 17 53 VCC GND 18 ispLSI 1024/883 52 GND ispEN RESET 19 Top View 51 Y2 20 50 Y3 1SDI/IN 0 21 49 I/O 0 22 48 IN 2/SCLK1 I/O 23 I/O 1 23 47 I/O 22 I/O 2 24 46 I/O 3 I/O 4 25 45 I/O 21 I/O 20 44 I/O 19 26 I/O 16 I/O 17 I/O 18 I/O 15 I/O 14 VCC I/O 12 I/O 13 1SDO/IN 1 GND I/O 9 I/O 10 I/O 11 I/O 8 I/O 6 I/O 7 I/O 5 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 1. Pins have dual function capability. 0123-24-isp/JLCC 11 Specifications ispLSI 1024/883 Part Number Description ispLSI 1024 – XX X X Device Family ispLSI X Grade /883 = 883 Military Process Device Number Package H = JLCC Speed 60 = 60 MHz fmax Power L = Low 00212-80B-isp1024 mil Ordering Information MILITARY/883 Family fmax (MHz) tpd (ns) Ordering Number SMD # Package ispLSI 60 20 ispLSI 1024-60LH/883 5962-9476101MXC 68-Pin JLCC Note: Lattice Semiconductor recognizes the trend in military device procurement towards using SMD compliant devices, as such, ordering by this number is recommended. 12 Table 2-0041A-24-mil