LT1684 Micropower Ring Tone Generator U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Allows Dynamic Control of Output Frequency, Cadence, Amplitude and DC Offset Active Tracking Supply Configuration Allows Linear Generation of Ring Tone Signal No High Voltage Post-Filtering Required Capacitive Isolation Eliminates Optocouplers Low Distortion Output Meets International PTT Requirements Differential Input Signal for Noise Immunity User Adjustable Active Output Current Limit Powered Directly From High Voltage Ringer Supply—No Additional Supplies Necessary Supply Current: < 1mA 2% Signal Amplitude Reference Available in 14-Pin SO and DIP Packages U APPLICATIO S ■ ■ Wireless Local Loop Telephones Key System/PBX Equipment Fiber to the Curb Telecom Equipment The LT1684 receives capacitor-isolated differential PWM input signals encoded with desired ring output cadence, frequency, and amplitude information. The LT1684 normalizes the pulse amplitude to ±1.25V for an accurate signal voltage reference. The cadence, frequency and amplitude information is extracted using a multiplepole active filter/amplifier, producing the output ring tone signal. The LT1684 uses its own ring tone output as a reference for generating local supply rails using complementary high voltage external MOSFETs as dynamic level-shifting devices. This “active tracking” supply mode of operation allows linear generation of the high voltage ring tone signal, reducing the need for large high voltage filtering elements. , LTC and LT are registered trademarks of Linear Technology Corporation. U ■ The LT®1684 is a telecommunication ring tone generator. The IC takes a user-generated pulse width modulated (PWM) input and converts it to a high voltage sine wave suitable for telephone ringing applications. TYPICAL APPLICATIO Electrically Isolated Ring Tone Generator DC ISOLATION PWM CONTROLLER P1 µC P2 100pF 10k 100pF 10k 100V 6.8nF 100k GATE + IN A IRF610 100Ω FB1 V+ IN B LT1684 BGOUT LIM + OUT ATREF COMP1 1N4001 + 100pF RING TONE OUTPUT 0.1µF 20pF 3k 2k 5k AMPIN 300k 4700pF COMP2 LIM – V– ±100mA CAPABILITY ) 1N5817 100Ω GATE– 1µF – ( IRF9610 6.8nF 100k –100V FB1: FERRONICS FMB1601 (716) 388-1020 1684 TA01 1 LT1684 W W W AXI U U ABSOLUTE RATI GS (Note 1) Voltages: Active Tracking Differential Voltage (GATE + – GATE –) ..................................– 0.3V to 42V Local Supply Differential Voltage (V + – V –) ...............................................– 0.3V to 36V Local Supply Voltage V + .............. (GATE + – 7.0V) to (GATE + + 0.3V) Local Supply Voltage V – .............. (GATE – – 0.3V) to (GATE – + 7.0V) PWM Input Differential Voltage (IN A – IN B) .........................................– 7.0V to 7.0V PWM Input Voltage Common Mode ................. (V – – 0.3V) to (V + + 0.3V) LIM + Current Limit Pin Voltage ..................... (OUT – 0.3V) to (V+ + 0.3V) LIM– Current Limit Pin Voltage .................... (V – – 0.3V) to (OUT + 0.3V) All Other Pin Voltages ........... (V – – 0.3V) to (V + + 0.3V) Currents: LIM +, LIM – Current .......................................... – 350mA OUT Current ....................................................... 350mA BGOUT Current .................................................... ±10mA PWM (IN A, IN B) Current .................................... ±5mA GATE +, GATE – Current ....................................... ±20mA COMP1 Current .................................................... ±1mA COMP2 Current .................................................... ±1mA ATREF Current ..................................................... ±20mA Temperatures: Operating Junction Temperature Range Commercial Grade ................................. 0°C to 125°C Industrial Grade ................................ – 40°C to 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C U U W PACKAGE/ORDER I FOR ATIO TOP VIEW IN B 1 14 IN A COMP1 2 13 BGOUT COMP2 3 12 AMPIN LIM – 4 11 GATE + V– 5 10 V + – 6 9 LIM + ATREF 7 8 OUT GATE N PACKAGE 14-LEAD PDIP S PACKAGE 14-LEAD PLASTIC SO TJMAX = 125°C, θJA = 75°C/W (N) TJMAX = 125°C, θJA = 115°C/W (S) Consult factory for Military grade parts. 2 ORDER PART NUMBER LT1684CN LT1684CS LT1684IN LT1684IS LT1684 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V + – V – = 20V, Voltages referenced to pin OUT, VOUT = VATREF unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 680 950 µA Supply and Protection IS DC Supply Current (Note 2) IN A – IN B ≥ 1.6V ● |V +| |V –| Local Supply Voltages VGATE+ ≥ V + VGATE– ≤ V – ● 6.5 10 VGATE+ Active Tracking Supply FET Bias Voltage IGATE+ = –100µA, ATREF = 0V ● 13.2 14.0 14.8 V VGATE – Active Tracking Supply FET Bias Voltage IGATE– = 100µA, ATREF = 0V ● –14.8 –14.0 –13.2 V IN A – IN B or IN B – IN A ● 1.6 ● 0.50 0.70 10 V PWM Receiver fPWM Input Carrier Frequency VIN Minimum Valid Differential Input 10 Differential Input Threshold | IN A – IN B | RIN Differential Input Overdrive Impedance (Note 3, 5) VIN > VTH + 100mV ● 7 RINA,INB Single-Ended Input Impedance (Note 5) To Pin OUT ● 50 BGOUT Normalized Voltage Magnitude |VBGOUT| ● 1.235 1.225 ● –7 –10 ● ±2 kHz V 1.00 V kΩ kΩ BG Buffer VBGOUT VBGOUTOS Output Offset Voltage [(VBGOUT+) + (VBGOUT –)]/2 1.250 1.250 1.265 1.275 V V 7 10 mV mV ±4.5 mA 0.2 Ω IBGOUTSC BGOUT Short-Circuit Current RBGOUT BGOUT Output Impedance tr BGOUT Rise Time (10% to 90%) ROUT = 5k, COUT = 10pF ● 160 300 ns tf BGOUT Fall Time (10% to 90%) ROUT = 5k, COUT = 10pF ● 260 400 ns ∆tr-f BGOUT RiseTime – Fall Time –100 0 ns tpr BGOUT Propagation Delay PWM Input Transition to 10% Output (Rising Edge) ROUT = 5k, COUT = 10pF ● 340 500 ns tpf BGOUT Propagation Delay PWM Input Transition to 90% Output (Falling Edge) ROUT = 5k, COUT = 10pF ● 440 600 ns ∆tp BGOUT Propagation Delay Rising Edge – Falling Edge –100 100 ns 6 8 mV mV – 2mA ≤ IBGOUT ≤ 2mA ● – 200 ● – 200 ● –6 –8 Output Amplifier VOUTOS OUT Offset Voltage VAMPIN = 0v, IOUT = 0A RAMPIN = 10k (Note 4) ROUT OUT Output Impedance –10mA ≥ ILIM+ ≥ –100mA, LIM + Shorted to OUT 10mA ≤ IOUT ≤ 100mA, LIM – Shorted to V – IOUTSC OUT Short-Circuit Current LIM + Shorted to OUT LIM – Shorted to V – Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: IC Supply current specification represents unloaded condition and does not include external FET gate pull up/down currents (GATE +, GATE – pins). Actual total IC bias currents will be higher and vary with operating conditions. See Applications Information. ● ±100 0.01 0.15 Ω Ω ±190 mA Note 3: PWM inputs are high impedance through ±100mV beyond the input thresholds. Note 4: 10k resistor from pin AMPIN to ground. Note 5: Guaranteed but not tested. 3 LT1684 U W TYPICAL PERFOR A CE CHARACTERISTICS DC Supply Current vs V+ – V– 740 IN A – IN B ≥ 1.6V 680 660 IN A – IN B ≤ –1.6V 620 IN A – IN B ≥ 1.6V 14.2 670 VGATE – VATREF (V) 700 640 TJ = 25°C 690 DC SUPPLY CURRENT (µA) DC SUPPLY CURRENT (µA) 14.3 710 TJ = 25°C 720 650 630 IN A – IN B ≤ –1.6V 610 590 14.1 14.0 13.9 570 550 –50 600 14 16 18 20 V + – V – (V) 22 24 –25 0 25 50 75 TEMPERATURE (°C) 1684 G01 13.8 0.1 125 14.3 IN A – IN B (V) 14.1 14.0 13.9 13.8 1.0 IGATE (mA) 3.0 10.0 VBGOUT Magnitude vs Temperature 0.85 1.253 0.80 1.252 0.75 1.251 VBGOUT (V) IGATE = 1mA 14.2 0.3 1684 G03 PWM Input Thresholds vs Temperature 14.5 14.4 100 1684 G02 VGATE – VATREF Voltage Magnitudes vs Temperature VGATE – VATREF (V) VGATE – VATREF Voltage Magnitudes vs IGATE DC Supply Current vs Temperature 0.70 0.65 0.60 1.250 1.249 1.248 0.55 1.247 0.50 1.246 13.7 13.6 13.5 – 50 –25 0 25 50 75 TEMPERATURE (°C) 100 0.45 – 50 125 –25 0 25 50 75 TEMPERATURE (°C) PWM Buffer (Pin BGOUT) Current Limit vs Temperature 4.0 3.5 3.0 2.5 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1684 G07 100 225 200 175 150 125 100 – 50 125 200 OUTPUT CURRENT LIMIT (mA) OUTPUT CURRENT LIMIT (mA) PWM BUFFER CURRENT LIMIT (mA) 5.5 4.5 0 25 50 75 TEMPERATURE (°C) Output Amplifier Current Limit vs External Limiting Resistor Values 250 5.0 –25 1684 G06 Output Amplifier Current Limit vs Temperature (RLIM = 0Ω) 6.0 4 1.245 – 50 125 1684 G05 1684 G04 2.0 – 50 100 150 100 TYPICAL (TJ = 25°C) 50 MINIMUM (TJ = 125°C) 0 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1684 G08 0 1 2 3 4 5 6 RLIM (Ω) 7 8 9 10 1684 G09 LT1684 U U U PI FU CTIO S IN B (Pin 1): PWM Negative Input. Input is isolated from digital source by ~100pF series capacitor. A 10k resistor can be connected to the IN B pin in series with the isolation capacitor for transient protection. The PWM receiver implements a diode forward drop of input hysteresis (relative to IN A). This hysteresis and internal signal limiting assure common mode glitch rejection with isolation capacitor mismatches up to 2:1. For maximum performance, however, effort should be made to match the two PWM input isolation capacitors. Pin IN B is differentially clamped to pin IN A through back-to-back diodes. This results in a high impedance differential input through ±100mV beyond the input thresholds. 5k internal input resistors yield a 10k (nominal) differential overdrive impedance. COMP1 (Pin 2): Output Amplifier Primary Compensation. Connect a 100pF capacitor from pin COMP1 to pin OUT. COMP2 (Pin 3): Output Amplifier Secondary Compensation. Connect a 20pF capacitor from pin COMP2 to pin OUT. LIM – (Pin 4): Output Amplifier Current Sink Limit. Pin implements IOUT • R = VBE current clamp. Internal clamp resistor has a typical value of 3.5Ω. For maximum current drive capability (190mA typical) short pin to pin V –. Reduction of current sink capability is achieved by placing additional resistance from pin LIM – to pin V –. (i.e. An external 3.5Ω resistance from pin LIM – to pin V – will reduce the current sinking capability of the output amplifier by approximately 50%.) V – (Pin 5): Local Negative Supply. Typically connected to the source of the active tracking supply P-channel MOSFET. V – rail voltage is GATE – self-bias voltage less the MOSFET VGS. Typical P-channel MOSFET characteristics provide ATREF – V – ≈ 10V. GATE– (Pin 6): Negative Power Supply FET Gate Drive. Pin sources current from pull-down resistor to bias gate of active tracking supply P-channel MOSFET. Self-biases to a typical value of –14V, referenced to pin ATREF. Pull-down resistor value is determined such that current sourced from the GATE – pin remains greater than 50µA at minimum output signal voltage and less than 10mA at maximum output signal voltage. ATREF (Pin 7): Active Tracking Supply Reference. Typically connected to pin OUT. Pin bias current is the difference between the magnitudes of GATE + pin bias and GATE– pin bias (IATREF = IGATE + – IGATE –). OUT (Pin 8): Ring Tone Output Pin. Output of active filter amplifier/buffer. Used as reference voltage for internal functions of IC. Usually shorted to pin ATREF to generate reference for active tracking supply circuitry. Connect a 1A (1N4001-type) diode between V + and OUT and a 1A Schottky diode from V – to OUT for line transient protection. LIM+ (Pin 9): Output Amplifier Current Source Limit. Pin implements IOUT • R = VBE current clamp. Internal clamp resistor has a typical value of 3.5Ω. For maximum current drive capability (190mA typical) short pin LIM + to pin OUT. Reduction of current source capability is achieved by placing additional resistance from pin LIM + to pin OUT. (i.e. An external 3.5Ω resistance from pin LIM + to pin OUT will reduce the current sourcing capability of the output amplifier by approximately 50%.) V + (Pin 10): Local Positive Supply. Typically connected to the source of the active tracking supply N-channel MOSFET. This condition should be made using a ferrite bead. Operating V + rail voltage is GATE + self-bias voltage less the MOSFET VGS. Typical N-channel MOSFET characteristics provide V + – ATREF ≈ 10V. GATE + (Pin 11): Positive Power Supply FET Gate Drive. Pin sinks current from pull-up resistor to bias gate of active tracking supply N-channel MOSFET. Self-biases to a typical value of 14V, referenced to pin ATREF. Pull-up resistor value is determined such that sink current into GATE + pin remains greater than 50µA at maximum output signal voltage and less than 10mA at minimum output signal voltage. AMPIN (Pin 12): Output Amplifier Input. Connected to external filter components through series protection resistor (usually 5k). Thevenin DC resistance of external filter and protection components should be 10k for optimum amplifier offset performance. See Applications Information section. 5 LT1684 U U U PI FU CTIO S BGOUT (Pin 13): Normalized PWM Buffered Output. PWM differential input is amplitude normalized to ±1.25V (referenced to the OUT pin). This signal is used to drive the active filter/amplifier. Filter resistor values must be chosen to limit the maximum current load on this pin to less than 2mA. The output is current limit protected to a typical value of ±4.5mA. receiver implements a diode forward drop of input hysteresis (relative to IN B). This hysteresis and internal signal limiting assure common mode glitch rejection with isolation capacitor mismatches up to 2:1. For maximum performance, however, effort should be made to match the two PWM input isolation capacitors. Pin IN A is differentially clamped to pin IN B through back-to back isolation-base diodes. This results in a high impedance differential input ±100mV beyond the input thresholds. 5k internal input resistors yield a 10k (nominal) differential overdrive impedance. IN A (Pin 14): PWM Positive Input. Input is isolated from digital source by ~100pF series capacitor. A 10k resistor should be connected to the IN A pin in series with the isolation capacitor for transient protection. The PWM W FUNCTIONAL BLOCK DIAGRA U U 100pF + PWM INPUT 100pF – 1.25V 10k IN A 5k 10k IN B 5k V+ –1.25V V+ GATE + BGOUT 14V ATREF 15k LIM + – AMPIN 5k + OUT CURRENT LIMIT 14V GATE – COMP1 100pF FILTER ELEMENTS LIM – COMP2 V– 20pF RING OUTPUT (RING RETURN) V– 1684 BD LT1684 Block Diagram 6 LT1684 U OPERATIO (Refer to Functional Block Diagram) BASIC THEORY OF OPERATION The LT1684 operates using a user-provided pulse-widthmodulated (PWM) digital signal as input*. The low frequency modulation component of this signal represents the desired output waveform. Changing the PWM input can thus dynamically control the frequency, cadence, amplitude and DC offset of the desired output. This method of sine wave generation can accomodate all popular ring tone frequencies including 17Hz, 20Hz, 25Hz and 50Hz. The LT1684 receives the PWM input by a capacitorisolated differential input at pins IN A and IN B. This signal is amplitude normalized by a bandgap reference and output single-ended on the BGOUT pin such that the PWM carrier is ±1.25V about the voltage on the OUT pin. The low frequency component of the normalized PWM signal is recovered using an active filter circuit constructed using an onboard driver amplifier. This amplifier also provides current drive for the final ring tone output. The ring tone output is used as the reference for a floating active biasing scheme by pin ATREF. As the ring tone output rises and falls through its typical range of hundreds of volts, the LT1684 “tracks” the output signal, maintaining local supply voltages across the IC of approximately ±10V. Input Receiver/Reference Buffer The differential receiver for the PWM input signal requires minimum differential input levels of 1.6V to assure valid change-of-state. The receiver inputs are capacitor coupled, isolating the LT1684 from the PWM generator. The receiver is leading edge triggered. The input receiver controls a switched-state output that forces an amplitude normalized voltage (referenced to the OUT pin) of ±1.25V that follows the PWM input. This switched voltage is driven off-chip on pin BGOUT. When the IN A input is driven higher than IN B (by the required 1.6V), the reference drives BGOUT to +1.25V above OUT. When IN B input is driven higher than IN A, BGOUT is forced to –1.25V relative to OUT. The amplitude normalized representation of the input PWM signal is used as the input for the active filter element and output driver. Output Amplifier/Driver The normalized PWM signal output on the BGOUT pin is converted to the final ring tone signal by an active filter. This filter consists of an onboard amplifier and a few external components. Although many different types of filters can be constructed, a 2-pole Multiple Feedback (MFB) configuration generally provides adequate performance and is desirable due to its simplicity and effectiveness. The low frequency component of the ±1.25V PWM signal contains the desired ring tone frequency and cadence information. The MFB active filter strips this information from the PWM signal and amplifies this low frequency component to generate the final desired output. Active Tracking Supplies Implementation of the active tracking supply technique enables linear generation of the ring tone output, and takes advantage of the intrinsic supply noise immunity of a linear amplifier, reducing the need for large high voltage filtering elements. Two external power MOSFETs act as voltage level-shifting devices and generate the power supply voltages for the LT1684. The LT1684 uses its own output as a voltage reference for the FET level shifters, “suspending” itself (by these generated supply voltages) about the signal output. In this manner, the LT1684 can linearly generate a signal hundreds of volts in amplitude at its output, while maintaining ±10V local supply rails across the IC itself. * Contact Linear Technology for code. 7 LT1684 U W U U APPLICATIO S I FOR ATIO Encoded PWM Signal Input Basics The LT1684 accepts a user-supplied PWM carrier that represents the desired output ring tone signal. This PWM input is normalized by the LT1684 such that ring tone output amplitudes can be accurately encoded into the PWM input. The LT1684 accepts a differential input to maximize rejection of system transients and ground noise. If no differential signal is readily available from the PWM controller, a simple inverter/buffer block can be used to create the differential signal required. Each differential input is internally connected through a 5k series resistor to back-to-back isolation-base diodes. These devices internally clamp the differential input signal to ±100mV greater than the input comparator hysteresis range. The input comparator toggles with a differential hysteresis equal to that of a standard diode forward voltage (0.7V nominal). As such, the differential impedance of the input remains high throughout the input hysteresis region, then reduces to a nominal value of 10k (7k minimum) as the input is overdriven beyond the comparator input threshold. A minimum differential input of 1.6V is specified to assure valid switching. The PWM signal can be visualized in terms of instantaneous ring tone amplitude, normalized to the LT1684 amplitude reference. For a given desired output voltage VOUTN, the input pulse train required follows the relation: VOUTN = 2 • VREF • (DC – 0.5), or DC = [VOUTN / (2 • VREF)] + 0.5, where: VREF = 1.25V normalized peak voltage DC = PWM input duty cycle 8 A 10% to 90% duty cycle range is a practical limit for a 10kHz input carrier. This corresponds to normalized signal amplitude of ±1V. Duty cycles exceeding this range can cause increased output signal distortion as signal energy is lost due to finite rise and fall times becoming a significant percentage of the signal pulses. The associated reduction in the pulse energy manifests itself as a “soft clipping” of the output signal resulting in an increase in harmonic distortion. The normalized PWM signal is amplified to the desired output signal level by the active filter/amplifier stage. Thus, dividing the desired peak output amplitude by the peak normalized encoded amplitude (VOUT/VOUTN) yields the required DC gain of the active filter. System Considerations Assuming use of a 10% to 90% maximum PWM range, the peak normalized signal will be: VPWM(pk) = ± 0.8 • VREF = ±1.0V, and: VOUT(pk) = VPWM(pk) • Filter DC Gain Thus, the DC gain of the output filter equals the desired peak voltage of the output ring tone signal. The frequency characteristics of the lowpass output filter must reflect the allowable carrier ripple on the output signal. For example, a 10kHz carrier system could use a 2-pole Butterworth lowpass with a cutoff frequency of 100Hz. This filter provides 40dB of input signal rejection at 10kHz yielding 25mVP-P output ripple. If the DC gain of the output filter/amplifier was 100, the output ripple voltage would be riding on a ±100V sine wave, and therefore be about – 78dB relative to the output ring signal. LT1684 U W U U APPLICATIO S I FOR ATIO For applications that are extremely output ripple sensitive, additional carrier rejection can be accomplished by modifying the output filter/amplifier characteristics such as implementing elliptical filter characteristics with a lower cutoff frequency or implementation of additional poles. Filter Design and Component Selection The ring tone information represented in the low frequency component of the input PWM signal is retrieved using an active filter. This filter also generates the appropriate low frequency gain required to produce the high voltage output signal and references the output to ground (or other system reference). The frequency and gain characteristics of this circuit element are both configurable by the appropriate choice of external passive filter elements. Because of the active tracking supply mode of operation, conventional active filter topologies cannot be used. Most amplifier/filter topologies can, however, be “transformed” into active tracking supply topologies. A conventional amplifier circuit topology can be “transformed” into an active tracking supply amplifier circuit by: a) Inverting the amplifier signal polarity (swap amplifier + and – connections) and input source polarity. b) Referencing all signals to the output except the feedback elements, which are referenced to ground (swap output and ground). A variety of amplifier/filter configurations can be realized using the transformation technique. A 2-pole filter is generally adequate for most ringer applications. Due to the relative simplicity of infinite-gain Multiple Feedback (MFB) configurations, these filters are good candidates for ringer applications. Component selection and active tracking supply transformation will be described for the following 2-pole MFB infinite-gain lowpass filter. Conventional Amplifier Configuration R1 Active Tracking Supply Amplifier R2 + – + – VIN VIN – TRANSFORMATION + – R1 + LOAD LOAD R2 Lowpass Mulitple Feedback Active Filter R2 R1 C2 R3 + VIN – Active Tracking Supply Lowpass Multiple Feedback Filter + – TRANSFORMATION C1 – C1 VIN – R1 R3 + + LOAD LOAD R2 C2 1684 F01 9 LT1684 U W U U APPLICATIO S I FOR ATIO The component selections for the active tracking supply lowpass MFB filter configuration follow the relations: Active Tracking Supply Lowpass Multiple Feedback Filter Transfer Characteristic (AV vs fn) 50 m ≤ 1 / [4Q2(1+|HO|)] C2 = mC1 FILTER GAIN (dB) R2 = 1± [1–4mQ2(1+|HO|)]1/2 2ωnC1mQ R1 = R2 / |HO| R3 = 1 0 ωn2C12R2m –50 Example: Conditions: Output ring tone peak voltage = 100V 1 10 100 1K HERTZ (Hz) Filter Q = 0.707 Set: fn = ωn / 2π = 100Hz Choose: C1 = 1.0µF (a convenient value) Then: m ≤ [4(0.7)2(1+100)]–1 ≈ .005 C2 = mC1 C2 = 4700pF (sets m = 0.0047) R2 = 1± [1– 4(0.0047)(0.707)2(101)]1/2 (4π100)(1e–6)(.0047)(0.707) R2 = 300k R1 = 300k/100 R1 = 3.0k R3 = [(2π100)2(1e–6)2(300k)(0.0047)]–1 R3 = 2k This filter configuration yields a DC Gain of 100, a corner frequency of just under 100Hz with gain reduction of only 0.1% at 20Hz, and a 10kHz carrier rejection of greater than 40dB at the output. Active Tracking Supply Components Given the previous discussion, implementation of an active tracking supply system may seem almost trivial. 10 100K 1684 F02 Ring frequency = 20Hz Input duty cycle range = 10% to 90% 10K However, bootstrapping an amplifier system about its own output creates a complex myriad of inherent stability and response issues. Attempting such a configuration with generic “jelly-bean” components is not recommended for the faint of heart or type-A personalities. The LT1684, however, makes for a simplistic approach to active tracking component selection. The high voltage MOSFET transistors used in the circuit must have an operating VDS specified at greater than the corresponding high voltage supply rail plus the opposite maximum excursion of the output signal. For example, if a system is designed with a 240V supply (+ 120V, –120V) and outputs a ring signal that has a 100V peak amplitude, the MOSFET VDS ratings must be greater than 240/2 + 100 = 220V. Active Filter Tuned Oscillator— No PWM Input Required A simple yet effective method of producing a high quality sine wave is to place a high-Q bandpass filter and a hard limited gain element in a positive feedback loop. This circuit will oscillate at the bandpass frequency, producing a sine wave at the filter output. The product of the fundamental component of the limiter and the filter gain at the bandpass frequency determines the output amplitude. This type of circuit is commonly referred to as an active filter tuned oscillator. LT1684 U W U U APPLICATIO S I FOR ATIO Active Filter Tuned Oscillator Block Diagram 1684 F03 The LT1684 can be implemented easily into a telephone ringer circuit based on the active filter tuned oscillator topology, eliminating the need for a user-supplied PWM input signal. The LT1684’s active filter amplifier can be used as a high-Q bandpass filter element by configuring it as an active tracking supply bandpass. The LT1684’s controlled output receiver/buffer is also convenient for use as the hard limiter. Because the LT1684 receiver/ buffer requires a true differential input for proper operation, a dual comparator IC such as the LT1017 must be bootstrapped along with the LT1684 to provide differential control signals. The LT1017 and LT1684 receiver/ buffer combine to create a high gain hard limiter whose RF3 VIN CF1 – VOUT RF2 – + 1684 F4a Active Tracking Bandpass MFB Filter – RF1 RF2 VIN + – CF1 VOUT + 1684 F5b CF2 RF3 The design equations for the active tracking bandpass filter are the same as the pretransformation MFB topology, such that if CF1 = CF2 = C: RF1 = Q/(ωO • C •H0) RF2 = Q/(2Q2 –H0)(ωO • C) RF3 = 2Q/(ωO • C) Example: Conditions: Output peak voltage = 95V Bandpass Q = 9.4 CF2 + The active bandpass filter circuit is easily configured using a basic MFB bandpass configuration, however, the active tracking supply technique used by the LT1684 requires “transformation” of this topology. This “transformation” swaps the amplifier signal polarity, references all signals to the output, and references all feedback elements to ground as described previously in the Filter Design and Component Selection section. Ring frequency = 20Hz Bandpass MFB Filter RF1 output is controlled to ±1.25V. The LT1684 active bandpass filter is then connected as a positive feedback element with the limiter component, which completes the active filter tuned oscillator topology. A square wave with peak amplitude A has a fundamental component with amplitude 4A/π, where A = 1.25V. Therefore, the desired filter’s bandpass gain HO = 95/(4 • 1.25/π) ~ 60. Given capacitor values C = 0.22µF (a convenient value) and desired filter characteristics of: Q = 9.4, HO = 60, ωO = 2π(20Hz), then: RF1 = 5.6k, RF2 = 2.7k, RF3 = 680k. The amplitude, frequency and envelope response time of the output signal can be adjusted by simply changing the values of resistors RF1 to RF3 accordingly. This produces a high voltage, high quality 20Hz sine wave at the filter output with a peak amplitude of 95V. Differential amplitude and frequency characteristics are achieved by simply changing a few resistor values. The output of the LT1684 is internally current limited to a minimum of ±100mA peak, allowing this ring tone generation circuit to be used with loads up to 7 REN with no degradation of the output waveform. 11 LT1684 U W U U APPLICATIO S I FOR ATIO Active Filter Tuned Oscillator Ring Tone Generator 110V 8 7 + + V 1/2 LT1017 V– – 5 8 R9 10k 6 + + V 1/2 LT1017 V– 1 4 – 3 2 4 R10 10k 1 C2 100pF 2 IN B COMP1 BGOUT COMP2 AMPIN C1 20pF 3 4 D1 1N5817 IN A LT1684 GATE + LIM – 14 R8 10k R6 1k R5 100k 13 R3 100k 12 R2 100Ω 11 FB1 5 6 7 V– V+ GATE – LIM + ATREF OUT 10 9 8 RF3 680k D2 1N4001 RF1 5.6k CF1 0.22µF C4 6.8nF C5 0.1µF – C3 6.8nF R1 100Ω R4 100k –110V M2 IRF9610 1684 F05a FB1: FERRONICS FMB1601 + OUTPUT CF2 0.22µF RF2 2.7k (716) 388-1020 Ringer Output 12 M1 IRF610 ( ±100mA PEAK ) 5V TO 15V INPUT + C4 1µF C7 220µF 10V FB VIN SW R9 39Ω D3 1N4001 R15 2k C10 0.1µF 1 4 7, 8 FB1: FERRONICS FMB1601 3 GND VC LT1270 C13 0.01µF 2 5 C8 1nF DZ1 44V 5, 6 • T1 COILTRONICS 14239-X3 4 11 12 1 2 1 2 4 OPTO2 H11AG1 2 1 C15 10µF 160V C14 10µF 160V DZ4 91V R13 50k R11 50k DZ2 R10 91V 10k + + 5 6 4 5 6 C12 0.47µF 160V C11 0.47µF 160V OPTO1 H11AG1 D2 MURS160 C9 0.47µF 160V (716) 388-1020 DS2 MBRS1100 9 • • D4 MURS160 R12 10k DS1 1N5817 C5 20pF C6 100pF 7 6 5 4 3 2 1 AMPIN BGOUT IN A ATREF GATE – V– OUT LIM + V+ LT1684 LIM – GATE + COMP2 COMP1 IN B 8 9 10 11 12 13 14 RF3 680k R3 10k RF2 2.7k RF1 5.6k R1 1k 4 3 2 1 R14 100k VEE 5 6 7 8 FB1 R6 100Ω R7 100k R5 100Ω C1 6.8nF C2 6.8nF R4 10k +IN B –IN B OUT B –IN A +IN A VCC LT1017 OUT A LOAD (REN) V (PEAK) RF1 RF2 RF3 7 5.6k 2.7k 680k 95V 10 6.8k 3.3k 620k 70V CF2 0.22µF CF1 0.22µF R8 100k R2 10k 5V-15V to Ring Tone Fully Isolated Converter Using an Active Filter-Tuned Oscillator Circuit 1684 TA03 M2 IRF9610 C3 0.1µF M1 IRF610 – OUTPUT + D1 1N4001 LT1684 TYPICAL APPLICATIO S 13 U LT1684 U TYPICAL APPLICATIO S 5kW PWM-to-Analog Converter 47Ω 100Ω 2N3906 120V 100V 2N3906 100Ω 6800pF 1nF 100k 100Ω 1000pF PWM IN 1000pF 10k 14 10k 1 300k 2k 0.1µF 5k V+ IN A OUT LT1684 ATREF BGOUT COMP2 12 470pF AMPIN 6800pF 8 ILIM+ 7 100pF 180µH 8 7 1k 3.9k 2 2 VOUT VIN 4 V– 5 0.22Ω 3 1µH 1µF 20pF ILIM– 6 0.22Ω 1k 180µH SENSE– VBOTTOM 5 4 6 100Ω MTP2N50E 100Ω 1nF IRF9240 100k 2N3904 –120V (716) 388-1020 –100V 100Ω 2N3904 47Ω FB1: FERRONICS FMB1601 0.22Ω 1µF LT1166 2k 3 LIM– GATE– SENSE+ 10 9 LIM+ IN B 1 VTOP FB1 GATE+ COMP1 13 3k MTP2N50E 11 IRF230 TYPICAL POWER SLICE (1 OF 13 IN PARALLEL) 1684 TA04 14 5kW LOAD LT1684 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N Package 14-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.770* (19.558) MAX 14 13 12 11 10 9 8 1 2 3 4 5 6 7 0.255 ± 0.015* (6.477 ± 0.381) 0.130 ± 0.005 (3.302 ± 0.127) 0.300 – 0.325 (7.620 – 8.255) 0.045 – 0.065 (1.143 – 1.651) 0.020 (0.508) MIN 0.065 (1.651) TYP 0.009 – 0.015 (0.229 – 0.381) +0.035 0.325 –0.015 0.005 (0.125) MIN 0.100 (2.54) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. BSC MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) ( +0.889 8.255 –0.381 ) 0.018 ± 0.003 (0.457 ± 0.076) 0.125 (3.175) MIN N14 1098 S Package 14-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.337 – 0.344* (8.560 – 8.738) 14 13 12 11 10 9 8 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 2 3 4 5 6 0.053 – 0.069 (1.346 – 1.752) 0.004 – 0.010 (0.101 – 0.254) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.014 – 0.019 (0.355 – 0.483) TYP 7 0.050 (1.270) BSC *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. S14 1298 15 LT1684 U TYPICAL APPLICATIO 5V Input Nonisolated 5 REN Ring Generator VIN 5V C2 100pF 100V + PWM INPUT C1 100pF – R4 10k D2 MURS160T3 R2 10k IN B IN A COMP1 + R10 100k LT1684 C3 100pF BGOUT R3 5k C4 20pF COMP2 AMPIN LIM – GATE + + R8 100Ω C8 1µF 10 9 • 7 + 4, 5 C12 220µF 35V • 1, 2 4 R1 2k C7 6.8nF 160V LIM + R5 300k ATREF • U1 V+ D1 1N4001 GATE – C10 0.47µF 160V D3 MURS160T3 12 M1 IRF610 FB1 V– C11 0.47µF 160V T1 COILTRONICS CTX 14468-X1 DS1 MBRS1100 C5 4700pF DZ1 60V MMSZ5264BT1 OUT C6 6.8nF 160V R6 3k R7 100Ω LT1271 VC FB 5 2 R12 5k GND 3 R11 470Ω C9 0.1µF R9 100k M2 IRF9610 1 VIN SW –100V R16 1M R15 12k D4 D1N4148 LT1211 1 2 3 DS2 D1N5817 FB1: FERRONICS FMB1601 4 C13 0.1µF (716) 388-1020 OUT A VCC –IN A OUT B +IN A –IN B VEE +IN B 8 7 D5 D1N4148 R14 1M 6 5 R13 12k RING TONE OUT 1684 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1082 1A High Voltage Switching Regulator VIN = 3V to 75V, SW Voltage = 100V LT1166 Power Output Stage Automatic Bias System Sets Class AB Bias Currents, Eliminates Adjustments and Thermal Runaway LTC1177-5/LTC1177-12 Isolated MOSFET Drivers 2500VRMS Isolation, UL Recognized LT1270 8A Power Switching Regulator VIN = 3.5V to 30V, IQ = 7mA LT1271 4A Power Switching Regulator VIN = 3.5V to 30V, IQ = 7mA LT1339 High Power Synchronous DC/DC Controller Operation Up to 60V, Output Current Up to 50A LT1676 Wide Input Range, High Efficiency, Step-Down Switching Regulator Operation Up to 60V, 100kHz, Up to 500mA Output 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com 1684f LT/TP 0300 4K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 1999