IRF610 Data Sheet June 1999 3.3A, 200V, 1.500 Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17442. Ordering Information PART NUMBER File Number 1576.3 Features • 3.3A, 200V • rDS(ON) = 1.500Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol PACKAGE BRAND D IRF610 TO-220AB IRF610 NOTE: When ordering, use the entire part number. G S Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) 4-190 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRF610 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRF610 200 200 3.3 2.1 8 ±20 43 0.34 46 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA (Figure 10) 200 - - V Gate Threshold Voltage VGS(TH) VDS = VGS, ID = 250µA 2 - 4 V VDS = Max Rating, VGS = 0V - - 25 µA VDS = Max Rating x 0.8, VGS = 0V, TJ = 125oC - - 250 µA 3.3 - - A - - ±100 nA - 1.0 1.5 Ω 0.8 1.3 - S Zero Gate Voltage Drain Current IDSS On-State Drain Current (Note 2) ID(ON) Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time rDS(ON) gfs td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time VDS > ID(ON) x rDS(ON)MAX, VGS = 10V (Figure 7) VGS = ±20V VGS = 10V, ID = 1.6A (Figures 8, 9) VDS ≥ 50V, ID = 1.6A (Figure 12) VDD = 100V, ID ≈ 3.3A, RG = 24Ω, RL = 30Ω MOSFET Switching Times are Essentially Independent of Operating Temperature tf Total Gate Charge (Gate to Source + Gate to Drain) Qg(TOT) Gate to Source Charge Qgs Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Internal Drain Inductance LD VGS = 10V, ID = 3.3A, VDS = 0.8 x Rated BVDSS, Ig(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature VGS = 0V, VDS = 25V, f = 1MHz (Figure 11) Measured From the Contact Screw on Tab to Center of Die Measured From the Drain Lead, 6mm (0.25in) From Package to Center of Die Internal Source Inductance LS Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA 4-191 Measured From the Source Lead, 6mm (0.25in) from Header to Source Bonding Pad Free Air Operation Modified MOSFET Symbol Showing the Internal Device Inductances D - 8 12 ns - 17 26 ns - 13 21 ns - 9 13 ns - 5.3 8.2 nC - 1.2 - nC - 3.0 - nC - 135 - pF - 60 - pF - 16 - pF - 3.5 - nH - 4.5 - nH - 7.5 - nH - - 2.9 oC/W - - 80 oC/W LD G LS S IRF610 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current TEST CONDITIONS ISD Pulse Source to Drain Current (Note 3) Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Rectifier ISDM D MIN TYP MAX UNITS - - 3.3 A - - 8 A - - 2.0 V 75 160 310 ns 0.33 0.9 1.4 µC G S Source to Drain Diode Voltage (Note 2) TJ = 25oC, ISD = 3.3A, VGS = 0V (Figure 13) VSD Reverse Recovery Time TJ = 25oC, ISD = 3.3A, dISD/dt = 100A/µs TJ = 25oC, ISD = 3.3A, dISD/dt = 100A/µs trr Reverse Recovery Charge QRR NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 6.4mH, RG = 25Ω, peak IAS = 3.3A. Typical Performance Curves Unless Otherwise Specified 5.0 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 0 50 100 4.0 3.0 2.0 1.0 0 25 150 50 TC, CASE TEMPERATURE (oC) 75 100 150 125 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 10 ZθJC, TRANSIENT THERMAL IMPEDANCE (oC/W) POWER DISSIPATION MULTIPLIER 1.2 0.5 1 0.2 0.1 PDM 0.05 0.02 0.1 0.01 0.01 10-5 t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC 10-4 10-3 10-2 0.1 t1, RECTANGULAR PULSE DURATION (S) FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE 4-192 1 10 IRF610 Typical Performance Curves 100 5 TJ = 150oC SINGLE PULSE TC = 25oC 10µs 10 100µs 1ms 1 10ms VGS = 10V VGS = 8V ID, DRAIN CURRENT (A) OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) ID, DRAIN CURRENT (A) Unless Otherwise Specified (Continued) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 4 VGS = 7V 3 2 VGS = 6V 1 VGS = 5V DC 0.1 0 1000 100 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 1 20 5 ID, DRAIN CURRENT (A) VGS = 8V 3 VGS = 7V 2 VGS = 6V 1 1 TJ = 150oC 0.1 TJ = 25oC VGS = 5V VGS = 4V 0 6 ID, DRAIN CURRENT (A) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS ≥ 50V VGS = 10V 4 8 10 10-2 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS 3.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 12 9 6 VGS = 10V 3 VGS = 20V 2.4 4 6 ID, DRAIN CURRENT (A) 8 10 FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4-193 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 3.2A 1.8 1.2 0.6 0 0 2 10 FIGURE 7. TRANSFER CHARACTERISTICS 15 0 100 10 4 2 60 FIGURE 5. OUTPUT CHARACTERISTICS PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0 40 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA rDS(ON), ON STATE RESISTANCE (Ω) VGS = 4V 80 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRF610 Typical Performance Curves 400 ID = 250µA 1.05 0.95 240 CISS 160 COSS 0.85 0.75 -60 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 320 1.15 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 Unless Otherwise Specified (Continued) 80 -40 -20 0 20 40 60 80 0 100 120 140 160 CRSS 1 2 TJ, JUNCTION TEMPERATURE (oC) gfs, TRANSCONDUCTANCE (S) 1.5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS ≥ 50V 1.2 TJ = 25oC TJ = 150oC 0.9 0.6 0.3 0 102 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE ISD, SOURCE TO DRAIN CURRENT (A) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 5 10 2 5 VDS, DRAIN TO SOURCE VOLTAGE (V) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 100 TJ = 150oC 10 TJ = 25oC 1 0 1 2 3 ID, DRAIN CURRENT (A) 4 0 5 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT VGS, GATE TO SOURCE VOLTAGE (V) 20 0.4 0.8 1.2 1.6 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE ID = 3.2A VDS = 100V 16 VDS = 40V 12 8 VDS = 160V 4 0 0 2 4 6 8 10 Qg, GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-194 2.0 IRF610 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN + RG REQUIRED PEAK IAS VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 17. SWITCHING TIME TEST CIRCUIT 0.2µF 50% PULSE WIDTH 10% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd 0.3µF VGS Qgs D VDS DUT G 0 Ig(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 4-195 IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRF610 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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