LTC1292/LTC1297 Single Chip 12-Bit Data Acquisition Systems U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ Built-In Sample-and-Hold Single Supply 5V Operation 60kHz Maximum Throughput Rate (LTC1292) Power Shutdown After Each Conversion (LTC1297) Direct 3-Wire Interface to Most MPU Serial Ports and All MPU Parallel Ports Analog Inputs Common Mode to Supply Rails U KEY SPECIFICATIO S ■ ■ ■ ■ Resolution: 12 Bits Fast Conversion Time: 12µs Max Over Temp Low Supply Current: 6.0mA Shutdown Supply Current: 5µA (LTC1297) The LTC1292/LTC1297 are data acquisition systems that contain a 12-bit, switched-capacitor successive approximation A/D, a differential input, sample-and-hold on the (+) input, and serial I/O. When the LTC1297 is idle between conversions it automatically powers down reducing the supply current to 5µA, typically. The LTC1292 is capable of digitizing signals at a 60kHz rate and with the device’s excellent AC characteristics, it can be used for DSP applications. All these features are packaged in an 8-pin DIP and are made possible using LTCMOSTM switched-capacitor technology. The serial I/O is designed to communicate without external hardware to most MPU serial ports and all MPU parallel I/O ports allowing data to be transmitted over three wires. Because of their accuracy, ease of use and small package size these devices are well suited for digitizing analog signals in remote applications where minimum number of interconnects and power consumption are important. LTCMOS is trademark of Linear Technology Corporation UO TYPICAL APPLICATI Power Supply Current vs Sampling Frequency 12-Bit Differential Input Data Acquisition System 10000 DIFFERENTIAL INPUTS COMMON MODE RANGE 0V TO 5V* + +IN CLK – –IN LTC1297 DOUT GND 5V 22µF TANTALUM + DO 1000 MC68HC11 SCK 1N4148 MISO LT1027 VREF + 4.7µF TANTALUM 8V TO 40V AVERAGE ICC (µA) VCC CS 100 10 1µF 1 1 *FOR OVERVOLTAGE PROTECTION LIMIT THE INPUT CURRENT TO 15mA PER PIN OR CLAMP THE INPUTS TO VCC AND GND WITH 1N4148 DIODES. CONVERSION RESULTS ARE NOT VALID WHEN ANY INPUT IS OVERVOLTAGED (VIN < GND OR VIN > VCC). SEE SECTION ON OVERVOLTAGE PROTECTION IN THE APPLICATIONS INFORMATION. 10 1k 100 fSAMPLE (Hz) 10k 100k LTC1297• TA02 LTC1292/7 TA01 1 LTC1292/LTC1297 U U RATI GS W W W W AXI U U ABSOLUTE PACKAGE/ORDER I FOR ATIO (Notes 1 and 2) Supply Voltage (VCC) to GND .................................. 12V Voltage Analog and Reference Inputs..................................... –0.3V to VCC + 0.3V Digital Inputs........................................ –0.3V to 12V Digital Outputs .......................... –0.3V to VCC + 0.3V Power Dissipation.............................................. 500mW Operating Temperature Range LTC1292/LTC1297BC, LTC1292/LTC1297CC, LTC1292/LTC1297DC ............................ 0°C to 70°C LTC1292/LTC1297BI, LTC1292/LTC1297CI, LTC1292/LTC1297DI ........................ –40°C to 85°C Storage Temperature Range ................ –65°C to 150°C Lead Temperature (Soldering, 10 sec.)................ 300°C ORDER PART NUMBER TOP VIEW CS 1 8 VCC +IN 2 7 CLK –IN 3 6 DOUT GND 4 5 VREF J8 PACKAGE 8-LEAD CERAMIC DIP N8 PACKAGE 8-LEAD PLASTIC DIP LTC1292BIN8 LTC1292CIN8 LTC1292DIN8 LTC1292BCJ8 LTC1292CCJ8 LTC1292DCJ8 LTC1292BCN8 LTC1292CCN8 LTC1292DCN8 LTC1297BIN8 LTC1297CIN8 LTC1297DIN8 LTC1297BCJ8 LTC1297CCJ8 LTC1297DCJ8 LTC1297BCN8 LTC1297CCN8 LTC1297DCN8 TJMAX = 150°C, θJA =100°C/W (J8) TJMAX = 100°C, θJA =130°C/W (N8) For Military Temperature Ranges please contact factory. U U W CO VERTER A D ULTIPLEXER CHARACTERISTICS (Note 3) LTC1292B LTC1297B MIN TYP MAX LTC1292C LTC1297C MIN TYP MAX LTC1292D LTC1297D MIN TYP MAX UNITS PARAMETER CONDITIONS Offset Error (Note 4) ● ±3.0 ±3.0 ±3.0 LSB Linearity Error (INL) (Note 4 & 5) ● ±0.5 ±0.5 ±0.75 LSB Gain Error (Note 4) ● ±0.5 ±1.0 ±4.0 LSB 12 12 12 Bits Minimum Resolution for Which No Missing Codes are Guaranteed Analog and REF Input Range (Note 7) ● On Channel Leakage Current (Note 8) On Channel = 5V Off Channel = 0V ● ±1 ±1 ±1 µA On Channel = 0V Off Channel = 5V ● ±1 ±1 ±1 µA On Channel = 5V Off Channel = 0V ● ±1 ±1 ±1 µA On Channel = 0V Off Channel = 5V ● ±1 ±1 ±1 µA Off Channel Lekage Current (Note 8) 2 –0.05V to VCC + 0.05V V LTC1292/LTC1297 AC CHARACTERISTICS (Note 3) LTC1292B/LTC1297B LTC1292C/LTC1297C LTC1292D/LTC1297D MIN TYP MAX SYMBOL PARAMETER CONDITIONS fCLK Clock Frequency VCC = 5V (Note 6) tSMPL Analog Input Sample Time See Operating Sequence tCONV Conversion Time See Operating Sequence tCYC Total Cycle Time See Operating Sequence (Note 6) LTC1292 LTC1297 (Note 9) LTC1292 LTC1297 1.0 UNITS MHz 1.5CLK 0.5CLK+5.5µs 12 CLK Cycles 14CLK+2.5µs 14CLK+6µs tdDO Delay Time, CLK↓ to DOUT Data Valid See Test Circuits ● 160 300 ns tdis Delay Time, CS↑ to DOUT Hi-Z See Test Circuits ● 80 150 ns ten Delay Time, CLK↓ to DOUT Enabled See Test Circuits ● 80 200 ns thDO Time Output Data Remains Valid After CLK↓ tf DOUT Fall Time See Test Circuits ● 65 130 ns tr DOUT Rise Time See Test Circuits ● 25 50 ns tWHCLK CLK High Time VCC = 5V (Note 6) 130 ns 300 ns tWLCLK CLK Low Time VCC = 5V (Note 6) 400 ns tsuCS Setup Time, CS↓ Before CLK↑ (LTC1297 Wakeup Time) VCC = 5V (Note 6) LTC1292 LTC1297 50 5.5 ns µs tWHCS CS High Time Between Data Transfer Cycles VCC = 5V (Note 6) LTC1292 LTC1297 2.5 0.5 µs µs tWLCS CS Low Time During Data Transfer VCC = 5V (Note 6) LTC1292 LTC1297 14CLK 14CLK+ 5.5µs CIN Input Capacitance Analog Inputs On Channel Analog Inputs Off Channel Digital Inputs 100 5 5 pF pF pF U DIGITAL A D DC ELECTRICAL CHARACTERISTICS (Note 3) LTC1292B/LTC1297B LTC1292C/LTC1297C LTC1292D/LTC1297D MIN TYP MAX SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VCC = 5.25V ● VIL Low Level Input Voltage VCC = 4.75V ● 0.8 V IIH High Level Input Current VIN = VCC ● 2.5 µA IIL Low Level Input Current VIN = 0V ● –2.5 µA VOH High Level Output Voltage VCC = 4.75V, IO = –10µA IO = 360µA ● 2.0 2.4 UNITS V 4.7 4.0 V V VOL Low Level Output Voltage VCC = 4.75V, IO = 1.6mA ● 0.4 V IOZ High Z Output Leakage VOUT = VCC, CS High VOUT = 0V, CS High ● ● 3 –3 µA µA ISOURCE Output Source Current VOUT = 0V –20 mA ISINK Output Sink Current VOUT = VCC 20 mA 3 LTC1292/LTC1297 U DIGITAL A D DC ELECTRICAL CHARACTERISTICS (Note 3) LTC1292B/LTC1297B LTC1292C/LTC1297C LTC1292D/LTC1297D MIN TYP MAX SYMBOL PARAMETER CONDITIONS ICC Positive Supply Current CS High LTC1292 ● 6 12 mA CS Low LTC1297 ● 6 12 mA LTC1297BC, LTC1297CC, LTC1297DC ● 5 10 µA LTC1297BI, LTC1297CI, LTC1297DI LTC1297BM, LTC1297CM, LTC1297DM ● 5 15 µA ● 10 50 µA CS High Power Shutdown CLK Off IREF Reference Current CS High The ● denotes specifications which apply over the operating temperature range; all other limits and typicals TA = 25°C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground (unless otherwise noted). Note 3: VCC = 5V, VREF = 5V, CLK = 1.0MHz unless otherwise specified. Note 4: One LSB is equal to VREF divided by 4096. For example, when VREF = 5V, 1LSB = 5V/4096 = 1.22mV. Note 5: Linearity error is specified between the actual end points of the A/D transfer curve. The deviation is measured from the center of the quantization band. Note 6: Recommended operating conditions. Note 7: Two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop UNITS below GND or one diode drop above VCC. Be careful during testing at low VCC levels (4.5V), as high level reference or analog inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for inputs near full scale. This spec allows 50mV forward bias of either diode. This means that as long as the reference or analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V over initial tolerance, temperature variations and loading. Note 8: Channel leakage current is measured after the channel selection. Note 9: Increased leakage currents at elevated temperatures cause the S/ H to droop, therefore it is recommended that fCLK ≥125kHz at 125°C, fCLK ≥ 31kHz at 85°C, and fCLK ≥ 3kHz at 25°C. U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage 10 SUPPLY CURRENT (mA) 6 4 CLK = 1MHz VCC = 5V 8 7 6 5 8 7 VCC = 5V VREF = 5V CS HIGH CLK OFF 6 5 4 3 2 2 4 4 5 6 SUPPLY VOLTAGE (V) LTC1292/7 G01 4 9 SUPPLY CURRENT (µA) 9 8 SUPPLY CURRENT (mA) 10 10 CLK = 1MHz TA = 25°C 0 LTC1297 Supply Current (Power Shutdown) vs Temperature Supply Current vs Temperature 1 3 –50 –30 –10 10 30 50 70 90 110 130 AMBIENT TEMPERATURE (°C) LTC1292/7 G02 0 50 25 0 75 100 – 50 – 25 AMBIENT TEMPERATURE (°C) 125 LTC1292/7 G03 LTC1292/LTC1297 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC1297 Supply Current (Power Shutdown) vs CLK Frequency Unadjusted Offset Voltage vs Reference Voltage 25 VCC = 5V 10 5 0.7 0.6 0.5 0.4 VOS = 0.250mV 0.3 0.2 200 600 800 400 CLK FREQUENCY (kHz) 0.1 1000 5 –0.4 –0.6 –0.8 –1.0 –1.2 2 3 4 REFERENCE VOLTAGE (V) 3 4 2 REFERENCE VOLTAGE (V) 0.5 0.4 0.3 0.2 0.1 0 –50 5 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) VCC = 5V VREF = 5V CLK = 1MHz 0.4 0.3 0.2 0.1 0 –50 125 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) LTC1292/7 G08 125 LTC1292/7 G09 Minimum Clock Rate for 0.1 LSB Error* Change in Gain vs Temperature 5 Change in Linearity vs Temperature VCC = 5V VREF = 5V CLK = 1MHz LTC1292/7 G07 DOUT Delay Time vs Temperature 0.5 250 VCC = 5V 0.3 0.2 0.1 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) 125 LTC1292/7 G10 VCC = 5V DOUT DELAY TIME FROM CLK↓ (ns) VCC = 5V VREF = 5V CLK = 1MHz MINIMUM CLK FREQUENCY (MHz) MAGNITUDE OF GAIN CHANGE (LSB) 1 0 LTC1292/7 G06 MAGNITUDE OF LINEARITY CHANGE (LSB) MAGNITUDE OF OFFSET CHANGE (LSB) –0.2 0 –50 0.25 0 3 2 4 REFERENCE VOLTAGE (V) 1 0.5 VCC = 5V 0.4 0.50 Change in Offset vs Temperature 0 1 0.75 LTC1292/7 G05 Change in Gain vs Reference Voltage 0 1.00 VOS = 0.125mV LTC1292/7 G04 CHANGE IN GAIN (LSB = 1/4096 × VREF) LINEARITY (LSB = 1/4096 × VREF) 15 0 VCC = 5V 0.8 OFFSET (LSB = 1/4096 × VREF) SUPPLY CURRENT (µA) 1.25 0.9 VCC = 5V VREF = 5V CS HIGH CMOS LOGIC LEVELS 20 0 Change in Linearity vs Reference Voltage 0.25 0.20 0.15 0.10 0.05 –50 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) 125 LTC1292/7 G11 200 150 MSB FIRST DATA LSB FIRST DATA 100 50 0 –50 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) 125 LTC1292/7 G12 * AS THE CLK FREQUENCY IS DECREASED FROM 1MHz, MINIMUM CLK FREQUENCY (∆ERROR ≤ 0.1LSB) REPRESENTS THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 1MHz VALUE IS FIRST DETECTED (NOTE 9). 5 LTC1292/LTC1297 U W TYPICAL PERFOR A CE CHARACTERISTICS Maximum Filter Resistor vs Cycle Time Maximum Clock Rate vs Source Resistance 0.8 +VIN 0.6 RSOURCE RFILTER + +IN – –IN 0.4 +VIN CFILTER ≥1µF 1k S & H AQUISITION TIME TO 0.02% (µs) VCC = 5V VREF = 5V CLK = 1MHz MAXIMUM RFILTER** (Ω) MAXIMUM CLK FREQUENCY* (MHz) 100 10k 1.0 + – 100 10 0.2 0 100 1 1k 10k RSOURCE– (Ω) 100k 100 1k CYCLE TIME (µs) 10 LTC1292/7G13 10k LTC1292/7 G14 Input Channel Leakage Current vs Temperature 2.25 900 PEAK-TO-PEAK NOISE ERROR (LSB) GUARANTEED 800 700 600 500 400 300 200 ON CHANNEL OFF CHANNEL 100 0 –50 –30 –10 10 30 50 70 90 110 130 AMBIENT TEMPERATURE (°C) VREF = 5V VCC = 5V TA = 25°C 0V TO 5V INPUT STEP 10 +VIN RSOURCE + – 1 100 1000 RSOURCE+ (Ω) 10000 LTC1292/7 G15 Noise Error vs Reference Voltage 1000 INPUT CHANNEL LEAKAGE CURRENT (nA) Sample-and-Hold Acquisition Time vs Source Resistance * MAXIMUM CLK FREQUENCY REPRESENTS THE CLK FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE ERROR AT ANY CODE TRANSITION FROM ITS 1MHz VALUE IS FIRST DETECTED. LTC1292/LTC1297 NOISE = 200µVP-P 2.00 1.75 1.50 ** MAXIMUM RFILTER REPRESENTS THE FILTER RESISTOR VALUE AT WHICH A 0.1LSB CHANGE IN FULL SCALE ERROR FROM ITS VALUE AT RFILTER = 0Ω IS FIRST DETECTED. 1.25 1.00 0.75 0.50 0.25 0 0 LTC1292/7 G16 1 4 3 2 REFERENCE VOLTAGE (V) 5 LTC1292/7 G17 U U U PI FU CTIO S # PIN FUNCTION DESCRIPTION 1 CS Chip Select Input 2, 3 4 5 6 7 8 +IN, –IN GND VREF DOUT CLK VCC Analog Inputs Analog Ground Reference Input Digital Data Output Shift Clock Positive Supply A logic low on this input enables the LTC1292/LTC1297. Power shutdown is activated on the LTC1297 when CS is brought high. These inputs must be free of noise with respect to GND. GND should be tied directly to an analog ground plane. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. The A/D conversion result is shifted out of this output. This clock synchronizes the serial data transfer. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. 6 LTC1292/LTC1297 W BLOCK DIAGRA 8 VCC 7 INPUT SHIFT REGISTER OUTPUT SHIFT REGISTER 2 +IN SAMPLE AND HOLD ANALOG INPUT MUX 3 –IN 6 CLK DOUT COMP 12-BIT SAR 12-BIT CAPACITIVE DAC 4 5 GND VREF CONTROL AND TIMING 1 CS LTC1292/7 BD TEST CIRCUITS Voltage Waveforms for DOUT Delay Time, tdDO On and Off Channel Leakage Current 5V CLK ION 0.8V tdDO ON CHANNEL A IOFF 2.4V A DOUT OFF CHANNEL 0.4V LTC1292/7 TC04 Voltage Waveforms for DOUT Rise and Fall Times, tr, tf POLARITY LTC1292/7 TC01 Load Circuit for tdis and ten 2.4V DOUT 0.4V TEST POINT tr tf LTC1292/7 TC05 5V tdis WAVEFORM 2, ten 3k DOUT Voltage Waveforms for tdis tdis WAVEFORM 1 100pF Load Circuit for tdDO, tr and tf 1.4V 2.0V CS LTC1292/7 TC02 DOUT WAVEFORM 1 (SEE NOTE 1) 90% tdis 3kΩ DOUT TEST POINT DOUT WAVEFORM 2 (SEE NOTE 2) 100pF LTC1292/7 TC03 LTC1292/7 TC06 10% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. 7 LTC1292/LTC1297 TEST CIRCUITS Voltage Waveforms for ten CS CLK B11 DOUT 0.8V ten U W U UO APPLICATI S I FOR ATIO The LTC1292/LTC1297 are data acquisition components which contain the following functional blocks: 1. 12-Bit Succesive Approximation Capacitive A/D Converter 2. Differential Input 3. Sample-and-Hold (S/H) 4. Synchronous, Half-Duplex Serial Interface 5. Control and Timing Logic DIGITAL CONSIDERATIONS Serial Interface The LTC1292/LTC1297 communicate with microprocessors and other external circuitry via a synchronous, halfduplex, three-wire serial interface (see Operating Sequence). The clock (CLK) synchronizes the data transfer with each bit being transmitted on the falling CLK edge. The LTC1292/LTC1297 do not require a configuration input word and have no DIN pin. They are permanently configured to have a single differential input and to perform a unipolar conversion. A falling CS initiates data transfer. To allow the LTC1297 to recover from the power shutdown mode, tsuCS has to be met. Then the first CLK pulse enables DOUT. After one null bit, the A/D conversion result is output on the DOUT line with a MSB-first sequence followed by a LSB-first sequence. With the half-duplex serial interface the DOUT data is from the current conversion. This provides easy interface to MSB-first or LSB-first 8 LTC1292/7 TC07 serial ports. Bringing CS high resets the LTC1292/LTC1297 for the next data exchange and puts the LTC1297 into its power shutdown mode. Table 1. Microprocessor with Hardware Serial Interfaces Compatible with the LTC1292/LTC1297** PART NUMBER Motorola MC6805S2, S3 MC68HC11 MC68HC05 RCA CDP68HC05 Hitachi HD6305 HD6301 HD63701 HD6303 HD64180 National Semiconductor COP400 Family COP800 Family NS8050U HPC16000 Family Texas Instruments TMS7002 TMS7042 TMS70C02 TMS70C42 TMS32011* TMS32020* TMS370C050 TYPE OF INTERFACE SPI SPI SPI SPI SCI Synchronous SCI Synchronous SCI Synchronous SCI Synchronous SCI Synchronous MICROWIRE† MCROWIRE/PLUS† MICROWIRE/PLUS MICROWIRE/PLUS Serial Port Serial Port Serial Port Serial Port Serial Port Serial Port SPI * Requires external hardware ** Contact factory for interface information for processors not on this list † MICROWIRE and MICROWIRE/PLUS are trademarks of National Semiconductor Corp. LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO LTC1292 Operating Sequence tCYC CS CLK Hi-Z B11 B10 DOUT B9 B8 B7 tSMPL B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 tSMPL tCONV LTC1292/7 AI01 LTC1297 Operating Sequence tCYC CS tsuCS POWER SHUTDOWN MODE CLK Hi-Z B11 B10 DOUT B9 B7 B8 tSMPL B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 LTC1292/7 AI02 tCONV Microprocessor Interfaces The LTC1292/LTC1297 can interface directly (without external hardware) to most popular microprocessors’ (MPU) synchronous serial formats (see Table 1). If an MPU without a dedicated serial port is used, then three of the MPU’s parallel port lines can be programmed to form the serial link to the LTC1292/LTC1297. Included here are one serial interface example and one example showing a parallel port programmed to form the serial interface. Motorola SPI (MC68HC11) The MC68HC11 has been chosen as an example of an MPU with a dedicated serial port. This MPU transfers data MSB first and in 8-bit increments. A dummy DIN word sent to the data register starts the SPI process. With two 8-bit transfers, the A/D result is read into the MPU (Figure 1). For the LTC1292 the first 8-bit transfer clocks B11 through B8 of the A/D conversion result into the processor. The second 8-bit transfer clocks the remaining bits B7 through B0 into CS CLK DOUT B11 B10 B9 B8 B10 B9 B8 B7 B6 B5 B4 B6 B5 B4 ? ? ? O B11 B2 B1 B0 B2 B1 B0 B1 BYTE 2 BYTE 1 MPU RECEIVED WORD B3 1ST TRANSFER B7 B3 2ND TRANSFER LTC1292/7 F01 Figure 1. Data Exchange Between LTC1292 and MC68HC11 9 LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO LTC1292 CS MSB LOCATION #61 O O O O B11 B10 B9 B8 LOCATION #62 B7 B6 B5 B4 B3 B1 B0 BYTE 1 SCK CLK ANALOG INPUTS DOUT FROM LTC1292 STORED ON MC68HC11 RAM MC68HC11 DO DOUT MISO B2 BYTE 2 LTC1292/7 F02 Figure 2. Hardware and Software Interface to Motorola MC68HC11 Microcontroller MC68HC11 CODE for LTC1292 Interface LABEL MNEMONIC LDAA STAA LDAA STAA LDAA LOOP OPERAND #$50 $1028 #$1B $1009 #$00 STAA LDX $50 #$1000 LDAB LDAA #$00 $50 STAA $102A COMMENTS CONFIGURATION DATA FOR SPCR LOAD DATA INTO SPCR ($1028) CONFIG. DATA FOR PORT D DDR LOAD DATA INTO PORT D DDR LOAD DUMMY DIN WORD INTO ACC A LOAD DUMMY DIN DATA INTO $50 LOAD INDEX REGISTER X WITH $1000 LOAD ACC B WITH $00 LOAD DUMMY DIN INTO ACC A FROM $50 LOAD DUMMY DIN INTO SPI, START SCK DELAY CS FALL TIME TO RIGHT JUSTIFY DATA NOP the MPU. The data is right-justified in the two memory locations (Figure 2). This was made possible by delaying the falling edge of CS till after the second CLK. ANDing the first byte with 0FHEX clears the four most significant bits. This operation was not included in the code. It can be inserted in the data gathering loop or outside the loop when the data is processed. LABEL MNEMONIC STAB OPERAND $08, X NOP COMMENTS D0 GOES LOW (CS GOES LOW) 6 NOPS FOR TIMING LDAA LDAA STAA STAA $1029 $102A $61 $102A CHECK SPI STATUS REG LOAD LTC1292 MSBs INTO ACC A STORE MSBs IN $61 LOAD DUMMY DIN INTO SPI, START SCK NOPS 6 NOPS FOR TIMING BSET LDAA LDAA STAA $08,X,$01 $1029 $102A $62 D0 GOES HIGH (CS GOES HIGH) CHECK SPI STATUS REGISTER LOAD LTC1292 LSBs IN ACC STORE LSBs IN $62 JMP LOOP START NEXT CONVERSION For the LTC1297 (Figure 3) a delay must be introduced to accommodate the setup time, tsuCS, before the dummy DIN word is sent to the data register. The first 8-bit transfer clocks B11 through B6 of the A/D conversion result into the processor. The second 8-bit transfer clocks the remaining bits B5 through B0 into the MPU. Note B1 and B2 from the LSB-first data word have also been clocked in. CS CLK DOUT B11 B10 B9 B8 B7 B6 B8 B7 B6 B5 B4 B3 B2 B4 B3 B2 ? 0 B11 B10 B9 1ST TRANSFER B0 B1 B0 B1 B5 B1 2ND TRANSFER Figure 3. Data Exchange Between LTC1297 and MC68HC11 10 B2 B3 BYTE 2 BYTE 1 MPU RECEIVED WORD B1 B2 LTC1292/7 F03 LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO LTC1297 CS CLK ANALOG INPUTS DOUT DOUT FROM LTC1297 STORED ON MC68HC11 RAM MC68HC11 DO MSB LOCATION #61 O O O O B11 B10 B9 B8 LOCATION #62 B7 B6 B5 B4 B3 B1 B0 BYTE 1 SCK MISO B2 BYTE 2 LTC1292/7 F04 Figure 4. Hardware and Software Interface to Motorola MC68HC11 Microcontroller MC68HC11 CODE for LTC1297 Interface LABEL MNEMONIC LDAA STAA LDAA STAA LDAA LOOP OPERAND #$50 $1028 #$1B $1009 #$00 STAA LDX $50 #$1000 LDAB LDAA BCLR NOP NOP NOP STAA #$00 $50 $08,X,$01 $102A COMMENTS CONFIGURATION DATA FOR SPCR LOAD DATA INTO SPCR ($1028) CONFIG. DATA FOR PORT D DDR LOAD DATA INTO PORT D DDR LOAD DUMMY DIN WORD INTO ACC A LOAD DUMMY DIN DATA INTO $0 LOAD INDEX REGISTER X WITH $1000 LOAD ACC B WITH $00 LOAD DIN INTO ACC FROM $50 D0 GOES LOW (CS GOES LOW) 3 NOP FOR tsuCS TIMING LOAD DUMMY DIN INTO SPI, START CLK The data is right- justified in the two memory locations by rotating right twice (Figure 4). ANDing the first byte with 0FHEX clears the four most significant bits. This operation was not included in the code. It can be inserted in the data gathering loop or outside the loop when the data is processed. Interfacing to the Parallel Port of the Intel 8051 Family The Intel 8051 has been chosen to show the interface between the LTC1292/LTC1297 and parallel port microprocessors. The signals CS and CLK are generated LABEL MNEMONIC LOOP1 LDAA BPL LDAA STAA STAA OPERAND $1029 LOOP1 $102A $61 $102A LOOP2 LDAA BPL BSET LDAA STAA ROR ROR ROR ROR JMP $1029 LOOP2 $08X,$01 $102A $62 $61 $62 $61 $62 LOOP COMMENTS CHECK SPI STATUS REG CHECK IF TRANSFER IS DONE LOAD LTC1297 MSBs INTO ACC A STORE MSBs IN $61 LOAD DUMMY DIN INTO SPI, START SCK CHECK SPI STATUS RES CHECK IF TRANSFER IS DONE D0 GOES HIGH (CS GOES HIGH) LOAD LTC1297 LSBs INTO ACC A STORE LSBs IN $62 ROTATE RIGHT WITH CARRY NEEDED TO RIGHT JUSTIFY THE DATA IN $61 AND $62 START NEXT CONVERSION on two port lines and the DOUT signal is read on a third port line. After a falling CLK edge each data bit is loaded into the carry bit and then rotated into the accumulator. Once the first 8 MSBs have been shifted into the accumulator they are loaded into register R2. The last four bits are shifted in the same way and loaded into register R3. The output data is left-justified in registers R2 and R3 (Figure 5). For the LTC1297 four NOPs need to be inserted in the 8051 code after CS goes low to allow the LTC1297 to wake up from power shutdown (tsuCS). 11 LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO LTC1292 LTC1297 ANALOG INPUTS DOUT FROM LTC1292/LTC1297 STORED IN 8051 RAM 8051 CS MSB P1.4 CLK P1.3 DOUT P1.1 R2 B11 B10 B9 B8 B7 B6 B5 B4 R3 B3 B2 B1 B0 O O O O B5 B4 B3 B1 B0 CS CLK DOUT B11 B10 B9 B8 B7 B6 B2 LTC1292/7 F05 Figure 5. Hardware and Software Interface to Intel 8051 Processor 8051 CODE LABEL MNEMONIC MOV CLR SETB CONT CLR NOP NOP NOP NOP SETB CLR SETB CLR MOV LOOP MOV RLC SETB CLR DJNZ MOV MOV OPERAND P1,#02h P1.3 P1.4 P1.4 COMMENTS BIT 1 PORT 1 SET AS INPUT CLK GOES LOW CS GOES HIGH CS GOES LO 4 NOP FOR LTC1297 tsuCS (Wakeup Time) (Not Needed for LTC1292) P1.3 P1.3 P1.3 P1.3 R4,#08H C,P1.1 A P1.3 P1.3 R4,LOOP R2,A C,P1.1 CLK GOES HIGH CLK GOES LOW CLK GOES HIGH CLK GOES LOW LOAD COUNTER READ DATA BIT INTO CARRY ROTATE DATA BIT INTO ACC CLK GOES HIGH CLK GOES LOW NEXT BIT STORE MSBs IN R2 READ DATA BIT INTO CARRY Sharing the Serial Interface The LTC1292/LTC1297 can share the same two-wire serial interface with other peripheral components or other LTC1292/LTC1297s (Figure 6). In this case, the CS signals decide which LTC1292 is being addressed by the MPU. 12 LABEL MNEMONIC CLR RLC CLR MOV RLC SETB CLR MOV RLC SETB CLR MOV SETB RRC RRC RRC RRC MOV AJMP OPERAND A A SETB P1.3 C,P1.1 A P1.3 P1.3 C,P1.1 A P1.3 P1.3 C,P1.1 P1.4 A A A A R3,A CONT COMMENTS CLEAR ACC ROTATE DATA BIT (B3) INTO ACC P1.3 CLK GOES HIGH CLK GOES LOW READ DATA BIT INTO CARRY ROTATE DATA BIT (B2) INTO ACC CLK GOES HIGH CLK GOES LOW READ DATA BIT INTO CARRY ROTATE DATA BIT (B1) INTO ACC CLK GOES HIGH CLK GOES LOW READ DATA BIT INTO CARRY CS GOES HIGH ROTATE DATA BIT (B0) INTO ACC ROTATE RIGHT INTO ACC ROTATE RIGHT INTO ACC ROTATE RIGHT INTO ACC STORE LSBs IN R3 START NEXT CONVERSION ANALOG CONSIDERATIONS Grounding The LTC1292/LTC1297 should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance LTC1292/LTC1297 U UO 1 W 2 U APPLICATI S I FOR ATIO OUTPUT PORT SERIAL DATA MPU VCC 22µF TANTALUM 0 2-WIRE SERIAL INTERFACE TO OTHER PERIPHERALS OR LTC1292/LTC1297s 2 2 2 2 CS LTC1292 LTC1297 CS LTC1292 LTC1297 2 CHANNELS 2 CHANNELS CS LTC1292 LTC1297 1 8 2 LTC1292 7 3 LTC1297 6 4 2 CHANNELS 0.1µF 5 LTC1292/7 F06 Figure 6. Several LTC1292/LTC1297s Sharing One 2-Wire Serial Interface LTC1292/7 F07 Figure 7. Example Ground Plane for the LTC1292/LTC1297 use a PC board. The ground pin (Pin 4) should be tied directly to the ground plane with minimum lead length (a low profile socket is fine). Figure 7 shows an example of an ideal LTC1292/LTC1297 ground plane design for a twosided board. Of course this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. minimum and the VCC supply should have a low output impedance such as obtained from a voltage regulator (e.g., LT323A). For high frequency bypassing a 0.1µF ceramic disk placed in parallel with the 22µF is recommended. Again the leads should be kept to a minimum. Figures 8 and 9 show the effects of good and poor VCC bypassing. Bypassing Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1292/ LTC1297 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. If large source resistances are used or if slow settling op amps drive the inputs, take care to insure that the transients caused by the current spikes settle completely before the conversion begins. VERTICAL: 0.5mV/DIV VERTICAL: 0.5mV/DIV For good performance, VCC must be free of noise and ripple. Any changes in the VCC voltage with respect to ground during a conversion cycle can induce errors or noise in the output code. VCC noise and ripple can be kept below 0.5mV by bypassing the VCC pin directly to the analog ground plane with a minimum of 22µF tantalum capacitor and with leads as short as possible. The lead from the device to the VCC supply also should be kept to a CS VCC HORIZONTAL: 10µs/DIV Figure 8. Poor VCC Bypassing. Noise and Ripple Can Cause A/D Errors HORIZONTAL: 10µs/DIV Figure 9. Good VCC Bypassing Keeps Noise and Ripple on VCC Below 1mV 13 LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO Source Resistance The analog inputs of the LTC1292/LTC1297 look like a 100pF capacitor (CIN) in series with a 500Ω resistor (RON) (Figures 10a and 10b). CIN gets switched between (+) and (–) inputs once during each conversion cycle. Large external source resistors and capacitances will slow the settling of the inputs. It is important that the overall RC time constant is short enough to allow the analog inputs to settle completely within the allowed time. “+” Input Settling The input capacitor for the LTC1292 is switched onto the “+” input during the sample phase (tSMPL, see Figures 11a, 11b and 11c). The sample period can be as short as tWHCS + 1/2 CLK cycle or as long as tWHCS + 1 1/2 CLK cycles before a conversion starts. This variability depends on where CS falls relative to CLK. The voltage on the “+” input must settle completely within the sample period. Minimizing RSOURCE+ and C1 will improve the settling time. If large “+” input source resistance must be used, the sample time can be increased by using a slower CLK frequency. With the minimum possible sample time of 3.0µs, RSOURCE+ < 2.0k and C1 < 20pF will provide adequate settling time. The sample period for the LTC1297 starts on the falling edge of CS and ends on the falling edge of the first CLK “+” INPUT RSOURCE + VIN + CS↑ C1 “–” INPUT RSOURCE – VIN – LTC1292 RON 500Ω CIN 100pF tWHCS + 0.5 CLK C2 LTC1292/7 F10a Figure 10a. Analog Input Equivalent Circuit for the LTC1292 “+” INPUT RSOURCE + LTC1297 VIN + CS↓ C1 “–” INPUT RSOURCE – VIN – RON 500Ω CIN 100pF tsuCS + 0.5 CLK C2 LTC1292/7 F10b Figure 10b. Analog Input Equivalent Circuit for the LTC1297 (Figure 12). The length of the sample period is tsuCS +0.5 CLK cycles. Again, the voltage on the “+” input must settle completely within the sample period. If large “+” input source resistance must be used, the sample time can be increased by using a slower CLK frequency or by increasing “+” and “–” Input Settling Windows tWHCS CS tSUCS CLK tSMPL (+) INPUT MUST SETTLE DURING THIS TIME DOUT B11 HI-Z B10 B9 1ST BIT TEST (–) INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT LTC1292/7 F11a Figure 11a. Setup Time (tsuCS) Is Met for the LTC1292 14 LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO tWHCS CS CLK tSMPL (+) INPUT MUST SETTLE DURING THIS TIME DOUT B11 B10 B9 HI-Z 1ST BIT TEST (–) INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT LTC1292/7 F11b Figure 11b. Setup Time (tsuCS) Is Met for the LTC1292 tWHCS CS CLK tSMPL (+) INPUT MUST SETTLE DURING THIS TIME DOUT B11 B10 HI-Z 1ST BIT TEST (–) INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT LTC1292/7 F11c Figure 11c. Setup Time (tsuCS) Is Not Met for the LTC1292 tsuCS. With the minimum possible sample time of 6µs, RSOURCE+ < 5k and C1 < 20pF will provide adequate settling time. In general for both the LTC1292 and LTC1297 keep the product of the total resistance and the total capacitance less than tSMPL/9. If this condition can not be met, then make C1 > 0.47µF (see RC Input Filtering section). “–” Input Settling At the end of the sample phase the input capacitor switches to the “–” input and the conversion starts (see Figures 11a, 11b, 11c and 12). During the conversion, the “+” input voltage is effectively “held” by the sample-and-hold and will not affect the conversion result. It is critical that the 15 LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO tWHCS tsuCS CS CLK DOUT tSMPL (+) INPUT MUST SETTLE DURING THIS TIME B11 B10 HI-Z 1ST BIT TEST (–) INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT LTC1292/7 F12 Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settles within the allowed time (see Figures 11a, 11b, 11c and 12). Again the “+” and “–” input sampling times can be extended as described above to accommodate slower op amps. Most op amps including the LT1006 and LT1013 single supply op amps can be made to settle well even with the minimum settling windows of 3.0µs for the LTC1292 or 6.0µs for the LTC1297 (“+” input) and 1µs (“–” input) that occurs at the maximum clock rate of 1MHz. Figures 13 and 14 show examples of both adequate and poor op amp settling. HORIZONTAL: 500ns/DIV Figure 13. Adequate Settling of Op Amp Driving Analog Input VERTICAL: 5mV/DIV “–” input voltage be free of noise and settle completely during the first CLK cycle of the conversion. Minimizing RSOURCE – and C2 will improve settling time. If large “–” input source resistance must be used the time can be extended by using a slower CLK frequency. At the maximum CLK frequency of 1MHz, RSOURCE – < 250Ω and C2 < 20pF will provide adequate settling. VERTICAL: 5mV/DIV Figure 12. “+” and “–” Input Settling Windows for the LTC1297 HORIZONTAL: 20µs/DIV Figure 14. Poor Op Amp Settling Can Cause A/D Errors 16 LTC1292/LTC1297 U W U UO APPLICATI S I FOR ATIO RC Input Filtering It is possible to filter the inputs with an RC network as shown in Figure 15. For large values of CF (e.g., 1µF) the capacitive input switching currents are averaged into a net DC current. A filter should be chosen with a small resistor and large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately IDC = 100pF × VIN/tCYC and is roughly proportional to VIN. When running the LTC1292(LTC1297) at the minimum cycle time of 16.5µs (20µs), the input current equals 30µA (25µA) at VIN = 5V. Here a filter resistor of 4Ω (5Ω) will cause 0.1LSB of full scale error. If a large filter resistor must be used, errors can be reduced by increasing the cycle time as shown in the typical performance characteristics curve Maximum Filter Resistor vs Cycle Time. RFILTER IDC VIN “+” CFILTER LTC1292 LTC1297 curve of S&H Acquisition Time vs Source Resistance). The input voltage is sampled during the tSMPL time as shown in Figure 11. The sampling interval begins at the rising edge of CS for the LTC1292, and at the falling edge of CS for the LTC1297, and continues until the falling edge of the CLK before the conversion begins. On this falling edge the S&H goes into the hold mode and the conversion begins. Differential Input With a differential input the A/D no longer converts a single voltage but converts the difference between two voltages. The voltage on the +IN pin is sampled and held and can be rapidly time-varying as in single-ended mode. The voltage on the –IN pin must remain constant and be free of noise and ripple throughout the conversion time. Otherwise the differencing operation will not be done accurately. The conversion time is 12 CLK cycles. Therefore a change in the –IN input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the –IN input this error would be: “–” LTC1292/7 F15 Figure 15. RC Input Filtering Input Leakage Current Input leakage currents also can create errors if the source resistance gets too large. For example, the maximum input leakage specification of 1µA (at 125°C) flowing through a source resistance of 1k will cause a voltage drop of 1mV or 0.8LSB. This error will be much reduced at lower temperatures because leakage drops rapidly (see typical performance characteristics curve Input Channel Leakage Current vs Temperature). SAMPLE-AND-HOLD Single-Ended Input The LTC1292/LTC1297 provide a built-in sample-andhold (S&H) function on the +IN input for signals acquired in the single-ended mode (–IN pin grounded). The sampleand-hold allows the LTC1292/LTC1297 to convert rapidly varying signals (see typical performance characteristics 12 VERROR(MAX) = 2πf(–IN)VPEAK fCLK ( ) 1292/7 E1 Where f(–IN) is the frequency of the –IN input voltage, VPEAK is its peak amplitude and fCLK is the frequency of the CLK. Usually VERROR will not be significant. For a 60Hz signal on the –IN input to generate a 0.25LSB error (300µV) with the converter running at CLK = 1MHz, its peak value would have to be 66mV. Rearranging the above equation the maximum sinusoidal signal that can be digitized to a given accuracy is given as: VERROR(MAX) fCLK f(–IN) MAX = 2πVPEAK 12 1292/7 E2 For 0.25LSB error (300µV) the maximum input sinusoid with a 5V peak amplitude that can be digitized is 0.8Hz. Reference Input The voltage on the reference input of the LTC1292/ LTC1297 determine the voltage span of the A/D converter. The reference input has transient capacitive switching currents due to the switched-capacitor con- 17 LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO version technique (see Figure 16). During each bit test of the conversion (every CLK cycle) a capacitive current spike will be generated on the reference pin by the A/D. These current spikes settle quickly and do not cause a problem. If slow settling circuitry is used to drive the reference input, take care to insure that transients caused by these current spikes settle completely during each bit test of the conversion. REF 14 + ROUT VREF REF – 13 EVERY CLK CYCLE RON LTC1292 LTC1297 8pF TO 40pF LTC1292/7 F16 VERTICAL: 0.5mV/DIV Figure 16. Reference Input Equivalent Circuit HORIZONTAL: 1µs/DIV VERTICAL: 0.5mV/DIV Figure 17. Adequate Reference Settling (LT1027) Reduced Reference Operation The effective resolution of the LTC1292/LTC1297 can be increased by reducing the input span of the converter. The LTC1292/LTC1297 exhibit good linearity over a range of reference voltages (see typical performance characteristics curves of Change in Linearity vs Reference Voltage). Care must be taken when operating at low values of VREF because of the reduced LSB step size and the resulting higher accuracy requirement placed on the converter. Offset and noise are factors that must be considered when operating at low VREF values. The internal reference for VREF has been tied to the GND pin. Any voltage drop from the GND pin to the ground plane will cause a gain error. Offset with Reduced VREF The offset of the LTC1292/LTC1297 has a larger effect on the output code when the A/D is operated with a reduced reference voltage. The offset (which is typically a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced. The typical performance characteristics curve of Unadjusted Offset Error vs Reference Voltage shows how offset in LSBs is related to reference voltage for a typical value of VOS. For example a VOS of 0.1mV, which is 0.1LSB with a 5V reference becomes 0.4LSB with a 1.25V reference. If this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the –IN input to the LTC1292/LTC1297. Noise with Reduced VREF HORIZONTAL: 10µs/DIV Figure 18. Poor Reference Settling Can Cause A/D Errors 18 Figures 17 and 18 show examples of both adequate and poor settling. Using a slower CLK will allow more time for the reference to settle. Even at the maximum CLK rate of 1MHz most references and op amps can be made to settle within the 1µs bit time. For example the LT1027 will settle adequately. With a 10µF bypass capacitor at VREF the LT1021 can also be used. The total input referred noise of the LTC1292/LTC1297 can be reduced to approximately 200µVP-P using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This noise is insignificant with a 5V reference input but will LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO become a larger fraction of an LSB as the size of the LSB is reduced. The typical performance characteristics curve of Noise Error vs Reference Voltage shows the LSB contribution of this 200µV of noise. For operation with a 5V reference, the 200µV noise is only 0.16LSB peak-to-peak. Here the LTC1292/LTC1297 noise will contribute virtually no uncertainty to the output code. For reduced references, the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code. For example, with a 1.25V reference, this 200µV noise is 0.64LSB peakto-peak. This will reduce the range of input voltages over which a stable output code can be achieved by 0.64LSB. Now, averaging readings may be necessary. This noise data was taken in a very clean test fixture. Any setup induced noise (noise or ripple on VCC, VREF or VIN) will add to the internal noise. The lower the reference voltage used, the more critical it becomes to have a noise-free setup. Gain Error Due to Reduced VREF The gain error of the LTC1292/LTC1297 is very good over a wide range of reference voltages. The error component that is seen in the typical performance characteristics curve Change in Gain Error vs Reference Voltage is due to the voltage drop on the GND pin from the device to the ground plane. To minimize this error the LTC1292/LTC1297 should be soldered directly onto the PC board. The internal reference point for VREF is tied to GND. Any voltage drop in the GND pin will make the reference voltage, internal to the device, less than what is applied externally (Figure 19). This drop is typically 420µV due to the product of the pin LTC1292 LTC1297 DAC REF– REF+ GND ICC RPIN VREF ± REFERENCE VOLTAGE LTC1292/7 F19 Figure 19. Parasitic Resistance in GND Pin resistance (RPIN) and the LTC1292/LTC1297 supply current. For example, with VREF = 1.25V this will result in a gain error change of –1.0LSB from the gain error measured with VREF = 5V. LTC1292 AC Characteristics Two commonly used figures of merit for specifying the dynamic performance of the A/Ds in digital signal processing applications are the Signal-to-Noise Ratio (SNR) and the “Effective Number of Bits (ENOB).” SNR is the ratio of the RMS magnitude of the fundamental to the RMS magnitude of all the non-fundamental signals up to the Nyquist frequency (half the sampling frequency). The theoretical maximum SNR for a sine wave input is given by: SNR = (6.02N + 1.76dB) where N is the number of bits. Thus the SNR depends on the resolution of the A/D. For an ideal 12-bit A/D the SNR is equal to 74dB. Fast Fourier Transform (FFT) plots of the output spectrum of the LTC1292 are shown in Figures 20a and 20b. The input (fIN) frequencies are 1kHz and 28kHz with the sampling frequency (fS) at 58.8 kHz. The SNRs obtained from the plots are 73.0dB and 61.5dB. By rewriting the SNR expression it is possible to obtain the equivalent resolution based on the SNR measurement. SNR – 1.76dB N= 6.02 1292/7 E3 This is the effective number of bits (ENOB). For the example shown in Figures 20a and 20b, N = 11.8 bits and 9.9 bits, respectively. Figure 21 shows a plot of ENOB as a function of input frequency. The 2nd harmonic distortion term accounts for the degradation of the ENOB as fIN approaches fS/2. Figure 22 shows an FFT plot of the output spectrum for two tones applied to the input of the A/D. Nonlinearities in the A/D will cause distortion products at the sum and difference frequencies of the fundamentals and products of the fundamentals. This is classically referred to as intermodulation distortion (IMD). 19 LTC1292/LTC1297 U UO S I FOR ATIO 0 0 –20 –20 –40 –40 MAGNITUDE (dB) MAGNITUDE (dB) W U APPLICATI –60 –80 –80 –100 –100 –120 –120 –140 –140 0 20 15 10 FREQUENCY (kHz) 5 30 25 LTC1292/7 F20a Figure 20a. fIN = 1kHz, fS = 58.8kHz, SNR = 73.0dB 0 –20 MAGNITUDE (dB) –40 –60 –80 –100 –120 –140 0 20 15 10 FREQUENCY (kHz) 5 30 25 LTC1292/7 F20b Figure 20b. fIN = 28kHz, fS = 58.8kHz, SNR = 61.5dB 12.0 fS = 58.8kHz EFFECTIVE NUMBER OF BITS 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 0 20 40 60 FREQUENCY (kHz) 80 100 LT1292/7 F21 Figure 21. LTC1292 ENOB vs Input Frequency 20 –60 0 5 20 15 10 FREQUENCY (kHz) 25 30 LTC1292/7 F22 Figure 22. fIN1 = 5.1kHz, fIN2 = 5.6kHz, fS = 58.8kHz Overvoltage Protection Applying signals to the LTC1292/LTC1297’s analog inputs that exceed the positive supply or that go below ground will degrade the accuracy of the A/D and possibly damage the devices. For example this condition would occur if a signal is applied to the analog inputs before power is applied to the LTC1292/LTC1297. Another example is the input source is operating from different supplies of larger value than the LTC1292/ LTC1297. These conditions should be prevented either with proper supply sequencing or by use of external circuitry to clamp or current limit the input source. There are two ways to protect the inputs. In Figure 23 diode clamps from the inputs to VCC and GND are used. The second method is to put resistors in series with the analog inputs for current limiting. Limit the current to 15mA per channel. The +IN input can accept a resistor value of 1k but the –IN input cannot accept more than 250Ω when clocked at its maximum clock frequency of 1MHz. If the LTC1292/LTC1297 are clocked at the maximum clock frequency and 250Ω is not enough to current limit the input source, then the clamp diodes are recommended (Figures 24a and 24b). The reason for the limit on the resistor value is that the MSB bit test is affected by the value of the resistor placed at the –IN input (see discussion on Analog Inputs and the typical performance characteristics Maximum CLK Frequency vs Source Resistance). LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO If VCC and VREF are not tied together, then VCC should be turned on first, then VREF. If this sequence cannot be met, connecting a diode from VREF to VCC is recommended (see Figure 25). Because a unique input protection structure is used on the digital input pins, the signal levels on these pins can exceed the device VCC without damaging the device. 1N4148 DIODES 1N4148 DIODES CS 5V 5V VCC CS VCC +IN CLK +IN DOUT –IN 1k –IN LTC1292 LTC1297 GND CLK LTC1292 LTC1297 DOUT GND VREF VREF LTC1292/7 F24 LTC1292/7 F23 Figure 23. Overvoltage Protection with Clamp Diodes CS VCC +IN CLK Figure 24b. Overvoltage Protection with Diode Clamps and Current Limiting Resistor 5V CS 1k 250Ω –IN LTC1292 LTC1297 +IN DOUT –IN GND VCC 5V CLK LTC1292 LTC1297 1N4148 DOUT VREF LTC1292/7 F24a GND VREF 5V LTC1292/7 F25 Figure 24a. Overvoltage Protection with Current Limiting Resistors Figure 25. Separate VCC and VREF Supplies +5V f/32 22µF CS VCC VDD CLK VIN +IN CLK LTC1292 –IN DOUT EN RESET Q1 Q4 GND Q3 Q2 Q3 VREF CD4520 Q2 Q4 Q1 RESET EN VSS TO OSCILLOSCOPE 0.1µF CLOCK IN 1MHz CLK LTC1292/7 F26 Figure 26. “Quick Look” Circuit for the LTC1292 21 LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO A “Quick Look” Circuit for the LTC1292 Users can get a quick look at the function and timing of the LTC1292 by using the “Quick Look” circuit in Figure 26. VREF is tied to VCC. VIN is applied to the +IN input and the –IN input is tied to the ground plane. CS is driven at 1/32 the clock rate by the CD4520 and DOUT outputs the data. The output data from the DOUT pin can be viewed on an oscilloscope that is set up to trigger on the falling edge of CS (Figure 27). Note the LSB data is partially clocked out before CS goes high. A “Quick Look” Circuit for the LTC1297 A circuit similar to the one used for the LTC1292 can be used for the LTC1297(Figure 28). A one shot has been generated with NAND gates, a resistor and capacitor to satisfy the setup time tsuCS. This can be eliminated if a slower clock is used. When CS goes low the one shot is triggered. This turns off the clock to the LTC1297 for a fixed time to meet tsuCS. Once the clock starts DOUT is shifted out one bit at a time. CS is driven at 1/64 the clock rate by the 74HC393. The output data from the DOUT pin can be viewed on an oscilloscope that is set to trigger on the falling edge of CS. See Figure 29. CLK CS CLK DOUT CS NULL BIT MSB LSB (B11) (B0) VERTICAL: 5V/DIV HORIZONTAL: 2µs/DIV DOUT LSB-FIRST DATA (B1) NULL MSB LSB LSB-FIRST DATA (B1) BIT (B11) (B0) VERTICAL: 5V/DIV HORIZONTAL: 5µs/DIV Figure 27. Scope Trace of the LTC1292 “Quick Look” Circuit Showing A/D Output 101010101010 (AAAHEX) Figure 29. Scope Trace of the LTC1297 “Quick Look” Circuit Showing A/D Output 101010101010 (AAAHEX) 22µF TANTALUM + 5V f/64 f CS VCC A1 VCC CLR1 VIN +IN LTC1297 –IN 1QB DOUT GND A2 1QA CLK 1QC VREF 0.1µF CLR2 74HC393 2QA 2QB 1QD 2QC GND 2QD TO OSCILLOSCOPE 340Ω 0.02µF CLOCK IN 1MHz Figure 28. “Quick Look” Circuit for the LTC1297 22 LTC1292/7 F28 LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO Opto-Isolated Temperature Monitor Amplification of sensor outputs is often required to generate a signal large enough to be properly digitized. For example, a J-type thermocouple provides only 52µV/°C. The 5µV offset of the LTC1050 chopper op amp generates less than 0.1°C error (Figure 31). Cold junction compensation is provided by the LT1025A. (For more detail see LTC Design Note 5). In the opto-isolated interface two signals are generated from one. This allows a two-wire interface to the LTC1292. A long high signal (>1ms) on the CLK IN input allows the 0.1µF capacitor to discharge taking CS high. This resets the A/D for the next conversion. When CLK IN starts toggling, CS goes low and stays there until the next extended CLK IN high time. See Figure 30. 5V/DIV CLK IN A CS DATA OUT 20µs/DIV Figure 30. Opto-Isolated Temperature Monitor Digital Waveforms ISOLATED 5V + 2k 0.1% 22 µ F 3.4k 0.1% 1N4148 178k 0.1% A + 0.33 µ F 2 2 VIN 7 LTC1050 J 3 H – + LT1025A GND 4 1N4148 + R 5 + 1 6 47Ω 2 3 4 1 µF 4 1 µF + 3 1N4148 10k + LTC1292 – 4N28s LT1019-2.5 CS +IN –IN GND 100k 8 VCC CLK 7 6 DOUT 5 VREF 4.7 µ F 1 2 4 5V 1k CLK IN 6 0.1 µ F 500k 5k + 5V 74C14 1k TYPE J 5k 1 3Ω 3 DATA OUT 0°C – 500°C TEMPERATURE RANGE 4 2 6 500k LTC1292/7 F31 Figure 31. Opto-Isolated Temperature Monitor Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC1292/LTC1297 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. J8 Package 8-Lead Ceramic DIP 0.200 (5.080) MAX CORNER LEADS OPTION (4 PLCS) 0.290 – 0.320 (7.366 – 8.128) 0.008 – 0.018 (0.203 – 0.457) 0.015 – 0.060 (0.381 – 1.524) 0.023 – 0.045 (0.584 – 1.143) HALF LEAD OPTION 0° – 15° 0.045 – 0.068 (1.143 – 1.727) FULL LEAD OPTION 8 7 6 5 0.025 (0.635) RAD TYP 0.045 – 0.068 (1.143 – 1.727) 0.220 – 0.310 (5.588 – 7.874) 0.125 3.175 0.100 ± 0.010 MIN (2.540 ± 0.254) 0.014 – 0.026 (0.360 – 0.660) 0.385 ± 0.025 (9.779 ± 0.635) 0.405 (10.287) MAX 0.005 (0.127) MIN 1 2 3 4 NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP OR TIN PLATE LEADS. J8 0293 N8 Package 8-Lead Plastic DIP 0.300 – 0.320 (7.620 – 8.128) 0.009 – 0.015 (0.229 – 0.381) ( 24 +0.025 0.325 –0.015 +0.635 8.255 –0.381 ) 0.045 – 0.065 (1.143 – 1.651) 0.130 ± 0.005 (3.302 ± 0.127) 0.400 (10.160) MAX 8 7 6 5 0.065 (1.651) TYP 0.045 ± 0.015 (1.143 ± 0.381) 0.100 ± 0.010 (2.540 ± 0.254) Linear Technology Corporation 0.250 ± 0.010 (6.350 ± 0.254) 0.125 (3.175) MIN 0.018 ± 0.003 (0.457 ± 0.076) 0.020 (0.508) MIN 1 2 3 4 N8 0392 LT/GP 0294 2K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977 LINEAR TECHNOLOGY CORPORATION 1994