Revised June 2005 74LCXH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold General Description Features The LCXH16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. ■ 5V tolerant control inputs and outputs The LCXH16374 is designed for low voltage (2.5V or 3.3V) VCC applications. The LCXH16374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. The LCXH16374 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. ■ 2.3V–3.6V VCC specifications provided ■ 6.2 ns tPD max (VCC 3.3V), 20 PA ICC max ■ Bushold on inputs eliminating the need for external pull-up/pull-down resistors ■ Power down high impedance outputs ■ r24 mA output drive (VCC 3.0V) ■ Implements patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human body model ! 2000V Machine model ! 200V ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Ordering Code: Order Number Package Number 74LCXH16374G (Note 1)(Note 3) BGA54A Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LCXH16374MEA (Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LCXH16374MTD (Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 1: Ordering code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol GTO¥ is a trademark of Fairchild Semiconductor Corporation. © 2005 Fairchild Semiconductor Corporation DS500441 www.fairchildsemi.com 74LCXH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold February 2001 74LCXH16374 Connection Diagrams Pin Descriptions Pin Assignment for SSOP and TSSOP Pin Names Description OEn Output Enable Input (Active LOW) CPn Clock Pulse Input I0–I15 Bushold Inputs O0–O15 Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A O0 NC OE1 CP1 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 I12 G O12 O11 VCC VCC I11 H O14 O13 NC NC I13 I14 J O15 NC OE2 CP2 NC I15 Truth Tables Inputs Pin Assignment for FBGA Outputs OE1 I0–I7 O0–O7 L H H L L L L L X O0 X H X Z CP1 Inputs CP2 (Top Thru View) H L X Z O0 www.fairchildsemi.com 2 Outputs OE2 I8–I15 O8–O15 L H H L L L L L X O0 X H X Z HIGH Voltage Level LOW Voltage Level Immaterial High Impedance Previous O0 before HIGH-to-LOW of CP the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops. The LCXH16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store Logic Diagrams Byte 1 (0:7) Byte 2 (8:15) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74LCXH16374 Functional Description 74LCXH16374 Absolute Maximum Ratings(Note 3) Symbol Parameter VCC Supply Voltage VI DC Input Voltage Value I0 - I15 OE1, CPn VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Source/Sink Current ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature Conditions 0.5 to 7.0 0.5 to VCC 0.5 0.5V to 7.0V 0.5 to 7.0 0.5 to VCC 0.5 50 50 50 r50 r100 r100 65 to 150 Units V V 3-STATE Output in HIGH or LOW State (Note 4) VI GND V mA VO GND mA VO ! VCC mA mA mA qC Recommended Operating Conditions (Note 5) Symbol VCC Parameter VI Input Voltage VO Output Voltage IOH/IOL Min Max Operating 2.0 3.6 Data Retention 1.5 3.6 Supply Voltage Output Current TA Free-Air Operating Temperature 't/'V Input Edge Rate, VIN 0.8V–2.0V, VCC 0 VCC HIGH or LOW State 0 VCC 3-STATE 0 5.5 VCC 3.0V 3.6V VCC 2.7V 3.0V VCC 2.3V 2.7V 3.0V r24 r12 r8 Units V V V mA 40 85 qC 0 10 ns/V Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: Floating or unused control inputs must be HIGH or LOW. DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current www.fairchildsemi.com TA 40qC to 85qC (V) Min 2.3 2.7 1.7 2.7 3.6 2.0 V 2.3 2.7 0.7 0.8 100 PA 2.3 3.6 VCC 0.2 IOH 8 mA 2.3 1.8 IOH 12 mA 2.7 2.2 IOH 18 mA 3.0 2.4 2.2 IOH 24 mA 3.0 100 PA 2.3 3.6 0.2 IOL 8 mA 2.3 0.6 IOL 12 mA 2.7 0.4 IOL 16 mA 3.0 0.4 3.0 0.55 24 mA VI VCC or GND Control 0V d VI d 5.5 4 V V IOL Data Units Max 2.7 3.6 IOH IOL II VCC 2.3 3.6 r5.0 2.3 3.6 r5.0 V PA Symbol (Continued) Parameter VCC Conditions (V) II(HOLD) II(OD) Bushold Input Minimum VIN 0.7V Drive Hold Current VIN 1.7V VIN 0.8V VIN 2.0V Bushold Input Over-Drive (Note 7) Current to Change State (Note 8) Min 45 75 300 2.7 300 (Note 8) 0 d VO d 5.5V IOFF Power-Off Leakage Current VO ICC Quiescent Supply Current VI 'ICC Increase in ICC per Input VIH 3.6V d VO d 5.5V (Note 6) VCC 0.6V 450 2.3 3.6 r5.0 PA 0 10 PA 2.3 3.6 20 2.3 3.6 r20 2.3 3.6 500 VCC VCC or GND PA 450 3.6 3-STATE Output Leakage PA 75 3.0 IOZ Units Max 45 2.3 (Note 7) 40qC to 85qC TA PA PA Note 6: Outputs disabled or 3-STATE only. Note 7: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 8: An external driver must sink at least the specified current to switch from HIGH-to-LOW. AC Electrical Characteristics TA Symbol Parameter VCC 50 pF CL Min CL 2.7V 500: VCC 50 pF CL 2.5V r 0.2V Min Max Min Max 1.5 6.2 1.5 6.5 1.5 7.4 CP to On 1.5 6.2 1.5 6.5 1.5 7.4 Output Enable time 1.5 6.1 1.5 6.3 1.5 7.9 1.5 6.1 1.5 6.3 1.5 7.9 1.5 6.0 1.5 6.2 1.5 7.2 1.5 6.0 1.5 6.2 1.5 7.2 Maximum Clock Frequency 170 tPHL Propagation Delay tPLH tPZL tPZH Output Disable Time tPHZ Units 30 pF Max fMAX tPLZ 40q to 85qC, RL 3.3V r 0.3V VCC MHz ns ns ns tS Setup Time 2.5 2.5 3.0 ns tH Hold Time 1.5 1.5 2.0 ns tW Pulse Width 3.0 3.0 3.5 ns tOSHL Output to Output Skew (Note 9) 1.0 ns 1.0 tOSLH Note 9: Skew is defined as the absolute value of the differences between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL VCC Conditions TA 25qC (V) Typical CL 50 pF, VIH 3.3V, VIL 0V 3.3 0.8 CL 30 pF, VIH 2.5V, VIL 0V 2.5 0.6 CL 50 pF, VIH 3.3V, VIL 0V 3.3 0.8 CL 30 pF, VIH 2.5V, VIL 0V 2.5 0.6 Units V V Capacitance Symbol Parameter Conditions CIN Input Capacitance VCC Open, VI COUT Output Capacitance VCC 3.3V, VI 0V or VCC CPD Power Dissipation Capacitance VCC 3.3V, VI 0V or VCC, f 5 0V or VCC 10 MHz Typical Units 7 pF 8 pF 20 pF www.fairchildsemi.com 74LCXH16374 DC Electrical Characteristics 74LCXH16374 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC 3.3 r 0.3V, and 2.7V VCC x 2 at VCC 2.5 r 0.2V tPZH, tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol www.fairchildsemi.com VCC 3.3V r 0.3V 2.7V 2.5V r 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL 0.3V VOL 0.3V VOL 0.15V Vy VOH 0.3V VOH 0.3V VOH 0.15V 6 74LCXH16374 Schematic Diagram Generic for LCXH Family (with Bushold) 7 www.fairchildsemi.com 74LCXH16374 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A www.fairchildsemi.com 8 74LCXH16374 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 9 www.fairchildsemi.com 74LCXH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10