Revised August 2001 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs General Description Features The LVTH162374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. ■ Input and output interface capability to systems at 5V VCC The LVTH162374 is designed with equivalent 25Ω series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. ■ Power Up/Power Down high impedance provides glitch-free bus loading The LVTH162374 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. ■ Functionally compatible with the 74 series 16374 These flip-flops are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH162374 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs ■ Live insertion/extraction permitted ■ Outputs include equivalent series resistance of 25Ω to make external termination resistors unnecessary and reduce overshoot and undershoot ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Code: Order Number 74LVTH162374GX (Note 1) Package Number BGA54A (Preliminary) Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 74LVTH162374MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBES] 74LVTH162374MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 74LVTH162374MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBES] 74LVTH162374MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] Note 1: BGA package available in Tape and Reel only. © 2001 Fairchild Semiconductor Corporation DS500355 www.fairchildsemi.com 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs June 2000 74LVTH162374 Logic Symbol Connection Diagrams Pin Descriptions Pin Names Pin Assignments for SSOP and TSSOP Description OEn Output Enable Input (Active LOW) CPn Clock Pulse Input I0–I15 Inputs O0–O15 3-STATE Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A O0 NC OE1 CP1 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 I12 G O12 O11 VCC VCC I11 H O14 O13 NC NC I13 I14 J O15 NC OE2 CP2 NC I15 Truth Tables Inputs CP1 Pin Assignment for FBGA Outputs OE1 I0–I7 O0–O7 L H H L L L L L X Oo X H X Z CP2 OE2 I8–I15 O8–O15 L H H L L L L L X Oo X H X Z Inputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance Oo = Previous Oo before HIGH-to-LOW of CP (Top Thru View) www.fairchildsemi.com Outputs 2 The LVTH162374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops. Logic Diagrams Byte 1 (0:7) Byte 2 (8:15) Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74LVTH162374 Functional Description 74LVTH162374 Absolute Maximum Ratings(Note 2) Symbol Parameter Value Conditions Units VCC Supply Voltage −0.5 to +4.6 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Output in 3-STATE −0.5 to +7.0 Output in HIGH or LOW State (Note 3) V V V IIK DC Input Diode Current −50 VI < GND mA IOK DC Output Diode Current −50 VO < GND mA IO DC Output Current 64 VO > VCC Output at HIGH State 128 VO > VCC Output at LOW State mA ICC DC Supply Current per Supply Pin ±64 mA IGND DC Ground Current per Ground Pin ±128 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VI Input Voltage IOH HIGH Level Output Current IOL LOW Level Output Current TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Min Max Units 2.7 3.6 V 0 5.5 V −12 mA 12 mA −40 85 °C 0 10 ns/V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol T A = −40°C to +85°C VCC Parameter (V) Min Input Clamp Diode Voltage VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC − 0.2 3.0 2.0 VOL II(HOLD) 2.7 Output LOW Voltage Bushold Input Minimum Drive Max −1.2 VIK 2.0 0.8 0.2 3.0 0.8 75 II(OD) Bushold Input Over-Drive II Input Current Control Pins Data Pins IOFF Power Off Leakage Current IPU/PD Power Up/Down 3-STATE Output Current 500 3.0 Current to Change State V VO ≤ 0.1V or V VO ≥ VCC − 0.1V V µA −500 3.6 10 3.6 ±1 −5 3.6 II = −18 mA µA −75 Conditions V V 2.7 3.0 Units IOH = −100 µA IOH = −12 mA IOL = 100 µA IOL = 12 mA VI = 0.8V VI = 2.0V (Note 4) (Note 5) VI = 5.5V µA VI = 0V or VCC VI = 0V VI = VCC 1 0 ±100 µA 0–1.5V ±100 µA 0V ≤ VI or VO ≤ 5.5V VO = 0.5V to 3.0V VI = GND or VCC IOZL 3-STATE Output Leakage Current 3.6 −5 µA VO = 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 µA VO = 3.0V IOZH+ 3-STATE Output Leakage Current 3.6 10 µA VCC < VO ≤ 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled www.fairchildsemi.com 4 Symbol 74LVTH162374 DC Electrical Characteristics (Continued) T A = −40°C to +85°C VCC Parameter (V) Min Units Conditions Max ICCZ+ Power Supply Current 3.6 0.19 mA VCC ≤ VO ≤ 5.5V, ∆ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC − 0.6V Outputs Disabled Other Inputs at VCC or GND (Note 6) Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol (Note 7) TA = 25°C VCC Parameter (V) Min Typ Conditions Units Max CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 8) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.8 V (Note 8) Note 7: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 8: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA = −40°C to +85°C, CL = 50 pF, RL = 500Ω Symbol VCC = 3.3V ± 0.3V Parameter Min Max VCC = 2.7V Min fMAX Maximum Clock Frequency 160 tPHL Propagation Delay 2.0 5.1 2.0 5.3 tPLH CP to On 1.6 5.3 1.6 6.2 tPZL Output Enable Time 1.8 5.0 1.8 6.0 1.2 5.6 1.2 6.9 1.9 5.0 1.9 5.1 2.0 5.4 2.0 5.7 tPZH tPLZ Output Disable Time tPHZ Units Max 150 MHz ns ns ns tS Setup Time 1.8 2.0 tH Hold Time 0.8 0.1 ns tW Pulse Width 3.0 3.0 ns tOSHL Output to Output Skew (Note 9) tOSLH ns 1.0 1.0 1.0 1.0 ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance (Note 10) Typical Units CIN Symbol Input Capacitance Parameter VCC = OPEN, VI = 0V or VCC Conditions 4 pF COUT Output Capacitance VCC = 3.0V, VO = 0V or VCC 8 pF Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. 5 www.fairchildsemi.com 74LVTH162374 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A (Preliminary) www.fairchildsemi.com 6 74LVTH162374 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 7 www.fairchildsemi.com 74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8