MICREL MICRF007

MICRF007
Micrel
MICRF007
QwikRadio™ Low-Power UHF Receiver
Preliminary Information
General Description
Features
The MICRF007 is a single chip ASK/OOK (ON-OFF Keyed)
Receiver IC for remote wireless applications, employing
Micrel’s latest QwikRadiotm technology. This device is a true
“antenna-in to data-out” monolithic device. All RF and IF
tuning is accomplished automatically within the IC which
eliminates manual tuning, and reduces production costs.
The result is a highly reliable yet extremely low cost solution.
The MICRF007 is an enhanced version of the MICRF002 and
MICRF011.
The MICRF007 is a conventional superhetrodyne receiver,
with an (internal) Local oscillator fixed at a single frequency
based on an external reference crystal or clock. As with any
conventional superhetrodyne reciever, the transmit frequency
must be accurately controlled, generally with a crystal or
SAW (Surface Acoustic Wave) resonator.
The MICRF007 provides two feature enhancements over the
MICRF001/011, (1) a Shutdown Mode, which may be used
for duty-cycle operation. (2) Reduced current consumption.
The MICRF007 requires a mere 1.7mA at 315MHz (3.0mA at
433.92MHz).These features make the MICRF007 ideal for
low and ultra-low power applications, such as RKE and RFID.
All post-detection (demodulator) data filtering is provided on
the MICRF007, so no external baseband filters are required.
The demodulator filter bandwidth is set to 2.1kHz. Data rates
up to 2kbps may be used
•
•
•
•
•
•
•
•
•
Complete UHF receiver on a monolithic chip
300MHz
Data Rates up to 2.1kbps
Automatic tuning, no manual adjustment
Low Power Consumption
315MHz:
1.7 mA fully operational
0.5µA shutdown
170µA polled
433.92MHz:
3.0mA fully operational
0.5µA shutdown
300µA in 10:1 polled operation
Very low RF re-radiation at the antenna
CMOS logic interface to standard decoder and microprocessor ICs
Extremely low external part count
No filters or inductors required
Applications
•
•
•
•
Automotive Remote Keyless Entry (RKE)
Long Range RF Identification
Remote fan and light control
Garage door and gate openers
Typical Application
MICRF007
VSS
SEL0
REFOSC
ANT
CAGC
VDDRF
SHUT
4.7µF
+5V
CTH
Data
Output
DO
0.047µF
315MHz 1200b/s On-Off Keyed Receiver
QwikRadio is a trademark of Micrel, Inc.
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com
December 2000
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MICRF007
MICRF007
Micrel
Ordering Information
Part Number
Demodulator
Bandwidth
Package
MICRF007BM
2100Hz
8-Pin SOIC
Other voltages available. Contact Micrel for details.
Pin Configuration
MICRF007BM
VSS 1
8
REFOSC
ANT 2
7
CAGC
VDD 3
6
SHUT
CTH 4
5
DO
8-Pin SOP (M) Package
MICRF007
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MICRF007
Micrel
Pin Description
Pin Number
Pin Name
1
VSS
Ground Return (Input): Ground return to the power supply. See “Application
Information” for bypass capacitor details.
2
ANT
Antenna (Input): High-impedance, internally ac coupled receiver input.
Connect this pin to the receive antenna. This FET gate input has approximately 2pF of shunt (parasitic) capacitance. See “Applications Information”
for optional band-pass filter information.
3
VDD
Power Supply (Input): Positive supply input for the RF IC. Connect a low
ESL, low ESR decoupling capacitor from this pin to VSS, lead lengths
should be as short as possible.
4
CTH
[Data Slicing] Threshold Capacitor (External Component): Capacitor
extracts the dc average value from the demodulated waveform which
becomes the reference for the internal data slicing comparator. See “Applications Information” for selection.
5
DO
Digital Output (Output): CMOS-level compatible data output signal.
6
SHUT
Shutdown (Input): Shutdown-mode logic-level control input. Pull low to
enable the receiver. This input has an internal pulled-up to VDD.
7
CAGC
AGC Capacitor (External Component): Integrating capacitor for on-chip
AGC (automatic gain control). The decay/attack time-constant (t) ratio is
nominally 10:1. See “Applications Information” for capacitor selection.
8
REFOSC
December 2000
Pin Function
Reference Oscillator (External Component or Input): Timing reference for
on-chip tuning and alignment. Connect a crystal between this pin and VSS,
or drive the input with an ac-coupled 0.5Vpp input clock.
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Absolute Maximum Ratings (Note 1)
Operating Ratings (Note 2)
Supply Voltage (VDDRF, VDDBB) .................................... +7V
Input/Output Voltage (VI/O) ................. VSS–0.3 to VDD+0.3
Junction Temperature (TJ) ...................................... +150°C
Storage Temperature Range (TS) ............ –65°C to +150°C
Lead Temperature (soldering, 10 sec.) ................... +260°C
ESD Rating, Note 3
Supply Voltage (VDD, VDDBB) .................... +4.75V to +5.5V
Ambient Temperature (TA) ......................... –40°C to +85°C
Package Thermal Resistance (θJA)
16-pin DIP (θJA) ................................................... 90°C/W
16-pin SOIC (θJA) .............................................. 120°C/W
Electrical Characteristics
VDDRF = VDDBB = VDD where +4.75V ≤ VDD ≤ 5.5V, VSS = 0V; CAGC = 4.7µF, CTH = 0.047µF; fREFOSC = 4.90MHz; TA = 25°C, bold
values indicate –40°C ≤ TA ≤ +85°C; current flow into device pins is positive; unless noted.
Symbol
Parameter
Condition
Min
IOP
Operating Current
continuous operation
Typ
Max
Units
3
5.5
mA
10:1 duty cycle
300
µA
VSHUT = VDD
0.5
µA
Receiver Sensitivity
Notes 4, 6
–96
fIF
IF Center Frequency
Note 7
0.86
MHz
fBW
IF 3dB Bandwidth
Notes 6, 7
0.43
kHz
fANT
RF Input Range
300
440
MHz
Receive Modulation Duty-Cycle
20
80
%
–20
dBm
ISTBY
Standby Current
RF Section, IF Section
400
Maximum Receiver Input
RSC = 50Ω
Spurious Reverse Isolation
ANT pin, RSC = 50Ω, Note 5
AGC Attack to Decay Ratio
tATTACK ÷ tDECAY
0.1
AGC Leakage Current
TA = +85°C
100
to 1% of final value
2.5
–90
dBm
µVrms
1
nA
Reference Oscillator
Reference Oscillator
Stabilization Time
ZREFOSC
Reference Oscillator
Input Impedance
3.1
290
Reference Oscillator Input Range
0.1
Reference Oscillator Source Current
4.5
2.8
ms
kΩ
1.5
VP-P
5.2
µA
110
kΩ
Demodulator
ZCTH
CTH Source Impedance
∆ZCTH
CTH Source Impedance Variation
IZCTH(leak)
CTH Leakage Current
TA = +85°C
±100
nA
Demodulator Filter Bandwidth
VSEL0 = VSEL1 = VSWEN = VDD, Notes 7, 9
4160
Hz
Demodulator Filter Bandwidth
VSEL0 = VSEL1 = VDD, VSWEN = VSS,
Notes 5, 7, 9
8320
Hz
MICRF007
Note 8
–15
4
+15
%
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MICRF007
Symbol
Micrel
Parameter
Condition
Min
Typ
Max
Units
Digital/Control Section
IIN(pu)
Input Pull-Up Current
SEL0, SEL1, SWEN, VSHUT = VSS
VIN(high)
Input-High Voltage
SEL0, SEL1, SWEN
VIN(low)
Input-Low Voltage
SEL0, SEL1, SWEN
IOUT
Output Current
DO, WAKEB pins, push-pull
VOUT(high)
Output High Voltage
DO, WAKEB pins, IOUT = –1µA
VOUT(low)
Output Low Voltage
DO, WAKEB pins, IOUT = +1µA
tR, tF
Output Rise and Fall Times
DO, WAKEB pins, CLOAD = 15pF
µA
8
0.8VDD
0.2VDD
V
V
µA
10
0.9VDD
V
0.1VDD
V
10
µs
Note 1.
Exceeding the absolute maximum rating may damage the device.
Note 2.
The device is not guaranteed to function outside its operating rating.
Note 3.
Devices are ESD sensitive. Use appropriate ESD precautions. Meets class 1 ESD test requirements, (human body model HBM), in accordance with MIL-STD-883C, method 3015. Do not operate or store near strong electrostatic fields.
Note 4:
Sensitivity is defined as the average signal level measured at the input necessary to achieve 10-2 BER (bit error rate). The input signal is
defined as a return-to-zero (RZ) waveform with 50% average duty cycle (Manchester encoded data) at a data rate of 300b/s. The RF input is
assumed to be matched into 50Ω.
Note 5:
Spurious reverse isolation represents the spurious components which appear on the RF input pin (ANT) measured into 50Ω with an input RF
matching network.
Note 6:
Sensitivity, a commonly specified receiver parameter, provides an indication of the receiver’s input referred noise, generally input thermal
noise. However, it is possible for a more sensitive receiver to exhibit range performance no better than that of a less sensitive receiver if the
background noise is appreciably higher than the thermal noise. Background noise refers to other interfering signals, such as FM radio
stations, pagers, etc.
A better indicator of achievable receiver range performance is usually given by its selectivity, often stated as intermediate frequency (IF) or
radio frequency (RF) bandwidth, depending on receiver topology. Selectivity is a measure of the rejection by the receiver of “ether” noise.
More selective receivers will almost invariably provide better range. Only when the receiver selectivity is so high that most of the noise on the
receiver input is actually thermal will the receiver demonstrate sensitivity-limited performance.
Note 7:
Parameter scales linearly with reference oscillator frequency fT. For any reference oscillator frequency other than 4.90MHz, compute new
parameter value as the ratio:
fREFOSCMHz
× (parameter value at 4.90MHz)
4.90
Example: For reference oscillator freqency fT = 6.00MHz:
6.00
(parameter value at 6.00MHz) =
× (paramter value at 4.90MHz)
4.90
Note 8:
Parameter scales inversely with reference oscillator frequency fT. For any reference oscillator frequency other than 4.90MHz, compute new
parameter value as the ratio:
4.90
× (parmeter value at 4.90MHz)
fREFOSCMHz
Example: For reference oscillator frequency fT = 6.00MHz:
4.90
(parmeter value at 6.00MHz) =
× (parmeter value at 4.90MHz)
6.00
Note 9:
Demodulator filter bandwidths are related in a binary manner, so any of the (lower) nominal filter values may be derived simply by dividing this
parameter value by 2, 4, or 8 as desired.
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Typical Characteristics
Supply Current
vs. Frequency
Supply Current
vs. Temperature
3.5
6.0
CURRENT (mA)
CURRENT (mA)
TA = 25°C
VDD = 5V
4.5
3.0
Sweep Mode,
Continuous Operation
3.0
2.5
2.0
1.5
-40 -20
1.5
300 325 350 375 400 425 450
FREQUENCY (MHz)
MICRF007
f = 315MHz
VDD = 5V
Sweep Mode,
Continuous Operation
0
20
40
60
80 100
TEMPERATURE (°C)
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MICRF007
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Functional Diagram
CAGC
AGC
Control
CAGC
ANT
2nd Order
Programmable
Low-Pass Filter
5th Order
Band-Pass Filter
RF
Amp
f RX
fIF
IF
Amp
IF
Amp
SwitchedCapacitor
Resistor
Peak
Detector
RSC
fLO
430kHz
Comparator
VDD
VSS
DO
CTH
Programmable
Synthesizer
UHF Downconverter
OOK Demodulator
CTH
Control
Logic
SHUT
fT
REFOSC
Cystal
or
Ceramic
MICRF002
Resonator
Reference
Oscillator
Reference and Control
MICRF007 Block Diagram
Data Slicing Level
Extraction of the dc value of the demodulated signal for
purposes of logic-level data slicing is accomplished using the
external threshold capacitor CTH and the on-chip switchedcapacitor “resistor” RSC, shown in the block diagram. The
effective resistance of RSC is 118kΩ.
Slicing level time constant values vary somewhat with decoder type, data pattern, and data rate, but typically values
range from 5ms to 50ms. Optimization of the value of CTH is
required to maximize range.
Automatic Gain Control
The signal path has AGC (automatic gain control) to increase
input dynamic range. An external capacitor, CAGC, must be
connected to the CAGC pin of the device. The ratio of decayto-attack time-constant is fixed at 10:1 (that is, the attack time
constant is 1/10th of the decay time constant), and this ratio
cannot be changed by the user. However, the attack time
constant is set externally by choosing a value for CAGC.
The AGC control voltage is carefully managed on-chip to
allow duty-cycle operation of the MICRF007 in excess of
100:1. When the device is placed into shutdown mode (SHUT
pin pulled high), the AGC capacitor floats, to retain the
voltage. When operation is resumed, only the voltage droop
on the capacitor due to leakage must be replenished, therefore a relatively low-leakage capacitor is recommended for
duty-cycled operation. The actual tolerable leakage will be
application dependent. Clearly, leakage performance is less
critical when the device off-time is low (milliseconds) and
more critical when the off-time is high (seconds).
To further enhance duty-cycled operation of the IC, the AGC
push and pull currents are increased for a fixed time immediately after the device is taken out of shutdown mode (turnedon). This compensates for AGC capacitor voltage droop
while the IC is in shutdown mode, reduces the time to restore
the correct AGC voltage, and therefore extends maximum
Functional Description
Refer to “MICRF007 Block Diagram”. Identified in the block
diagram are the three sections of the IC: UHF Downconverter,
OOK Demodulator and Reference and Control, and Wakeup.
Also shown in the figure are two capacitors (CTH, CAGC) and
one timing component (Y1), usually a crystal. With the
exception of a supply decoupling capacitor, these are the only
external components needed by the MICRF007 to assemble
a complete UHF receiver. There is one control input, the
SHUT pin. The SHUT function is used to enable the reciever.
These inputs are CMOS compatible, and are pulled-up on the
IC.
Receiver Operation
The MICRF007 is a standard superheterodyne receiver with
a narrow RF bandwidth IF. The narrow bandwidth receiver is
less susceptible to interfering RF signals. The MICRF007 is
capable of data rates up to 2.1kbps. Typically a crystal is
used for the reference oscillator frequency. The MICRF007
RF center frequency is controlled by a completely integrated
PLL / VCO frequency synthesizer which is referenced to the
crystal frequency.
Since the MICRF007 bandwidth is 430kHz, a tight tolerance
transmitter must be used for the system. Typically SAW or
crystal based transmitters are used in application designs.
IF Bandpass Filter
Rolloff response of the IF Filter is 5th order, while the
demodulator data filter exhibits a 2nd order response.
Baseband Demodulator Filter Bandwidth
The MICRF007 has a fully intergrated baseband demodulator filter. The filter has a fixed 2.1kHz bandwidth. This filter
limits the reciever raw data rate to 2kbps.
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MICRF007
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achievable duty ratios. Push-pull currents are increased by
45 times their nominal values. The fixed time period is based
on the reference oscillator frequency fT, 10.9ms for fT =
6.00MHz, and varies inversely as fT varies.
Reference Oscillator
All timing and tuning operations on the MICRF007 are derived from the internal Colpitts reference oscillator. Timing
and tuning is controlled through the REFOSC pin in one of two
ways:
1. Connect a crystal
2. Drive this pin with an external timing signal
The multiplication factor between the reference oscillator
frequency fT and the internal local oscillator (LO) is 64.5×. For
fT = fLO = 6.00MHz × 64.5 = 387MHz.
MICRF007
The second approach is attractive for lowering system cost
further if an accurate reference signal exists elsewhere in the
system, for example, a reference clock from a crystal-controlled microprocessor. An externally applied signal should
be ac-coupled and resistively-attenuated, or otherwise limited, to approximately 0.5Vpp. The specific reference frequency required is related to the system transmit frequency.
Shutdown Function
The shutdown function is controlled by a logic state applied
to the SHUT pin. When VSHUT is high, the device goes into
low-power standby mode, consuming less than 1µA. This pin
is pulled high internally. It must be externally pulled low to
enable the receiver.
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Figure 3 illustrates the CAGC pin interface circuit. The AGC
control voltage is developed as an integrated current into a
capacitor CAGC. The attack current is nominally 15µA, while
the decay current is a 1/10th scaling of this, nominally 1.5µA,
making the attack/decay timeconstant ratio a fixed 10:1.
Signal gain of the RF/IF strip inside the IC diminishes as the
voltage at CAGC decreases. Modification of the attack/decay
ratio is possible by adding resistance from the CAGC pin to
VDD.
Both the push and pull current sources are disabled during
shutdown, which maintains the voltage across CAGC, and
improves recovery time in duty-cycled applications. To further improve duty-cycle recovery, both push and pull currents
are increased by 45 times for approximately 10ms after
release of the SHUT pin. This allows rapid recovery of any
voltage droop on CAGC while in shutdown.
DO Pin
I/O Pin Interface Circuitry
Interface circuitry for the various I/O pins of the MICRF007
are diagrammed in Figures 1 through 6. The ESD protection
diodes at all input and output pins are not shown.
ANT Pin
Active
Load
ANT
50
3pF
6k
Active
Bias
Figure 1a. ANT Pin
The ANT pin is internally AC-coupled via a 3pF capacitor, to
an RF N-channel MOSFET, as shown in Figure 1. Impedance
on this pin to VSS is quite high at low frequencies, and
decreases as frequency increases. In the UHF frequency
range, the device input can be modeled as 6.3kΩ in parallel
with 2pF (pin capacitance) shunt to VSS0RF.
VDDBB
10µA
Comparator
CTH Pin
DO
VDDBB
PHI2B
Demodulator
Signal
2.85Vdc
PHI1B
10µA
VSSBB
CTH
VSSBB
PHI2
Figure 4. DO Pin
6.9pF
PHI1
VSSBB
The output stage for DO (digital output) is shown in Figure 4.
The output is a 10µA push and 10µA pull switched-current
stage. This output stage is capable of driving CMOS loads.
An external buffer-driver is recommended for driving highcapacitance loads.
REFOSC Pin
Figure 2. CTH Pin
Figure 2 illustrates the CTH-pin interface circuit. The CTH pin
is driven from a P-channel MOSFET source-follower with
approximately 10µA of bias. Transmission gates TG1 and
TG2 isolate the 6.9pF capacitor. Internal control signals
PHI1/PHI2 are related in a manner such that the impedance
across the transmission gates looks like a “resistance” of
approximately 100kΩ. The dc potential at the CTH pin is
approximately 1.6V
CAGC Pin
VDDBB
Active
Bias
200k
REFOSC
30pF
250Ω
30pF
VDDBB
30µA
VSSBB
1.5µA
VSSBB
67.5µA
Figure 5. REFOSC Pin
Comparator
The REFOSC input circuit is shown in Figure 5. Input impedance is high (200kΩ). This is a Colpitts oscillator with internal
30pF capacitors. This input is intended to work with standard
ceramic resonators connected from this pin to the VSS pin,
although a crystal may be used when greater frequency
accuracy is required. The nominal dc bias voltage on this pin
is 1.4V.
CAGC
Timout
15µA
675µA
VSSBB
Figure 3. CAGC Pin
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MICRF007
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VDDBB
Q1
Q2
to Internal
Circuits
VSSBB
SHUT
Q3
VSSBB
Figure 6. SHUT
Control input circuitry is shown in Figure 6. The standard input
is a logic inverter constructed with minimum geometry
MOSFETs (Q2, Q3). P-channel MOSFET Q1 is a large
channel length device which functions essentially as a “weak”
pullup to VDD. Typical pullup current is 5µA, leading to an
impedance to the VDD supply of typically 1MΩ.
J2
C5
REF.OSC.
GND
(Not Placed)
Y1
6.7458MHz
J1
RF INPUT
Z1
Z3
Z2
R1
Z4
VSS
REFOSC
ANT
CAGC
VDDRF
SHUT
CTH
Squelch
Resistor
C3(CTH)
0.047µF
J3
C1
4.7µF
J5
SHUT
GND
R2
10k
J4
(Not Placed)
+5V
GND
DO
C4
4.7µF
DO
GND
C2
0.1µF
Figure 1. Test Circuit
MICRF007
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PCB Layout Information
The MICRF007 evaluation board was designed and characterized using two sided 0.031 inch thick FR4 material with 1
ounce copper clad. If another type of printed circuit board
material were to be substituted, impedance matching and
characterization data stated in this document may not be
valid.
PCB Silk Screen
PCB Component Side Layout
December 2000
PCB Solder Side Layout
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MICRF007
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Micrel
and “low-side mixing,” and there is generally no preference of
one over the other.
After choosing one of the two acceptable values of fLO, use
Equation 2 to compute the reference oscillator frequency fT:
Application Information
Transmitter Compatibility
Generally, best performance and range will be realized when
the MICRF007 is operated in a system using a SAW or crystal
based transmitter. The receiver reference oscillator requires
the use of a crystal.
Bypass Capacitors
The power supply bypass capacitors connected to VDD
should have the shortest possible lead lengths. For best
performance, connect directly to VSS
Optional BandPass Filter
For applications located in high ambient noise environments,
a fixed value band-pass network may be connected between
the ANT pin and VSS to provide additional receive selectivity
and input overload protection. A typical filter is included in
Figure 7a.
Data Squelching
During quiet periods (no signal) the data output (DO pin)
transitions randomly with noise, presenting problems for
some decoders. A simple solution is to introduce a small
offset, or squelch voltage, on the CTH pin so that noise does
not trigger the internal comparator. Usually 20mV to 30mV is
sufficient, and may be introduced by connecting a severalmegohm resistor from the CTH pin to either VSS or VDD,
depending on the desired offset polarity. Since the MICRF007
has receiver AGC, noise at the internal comparator input is
always the same, set by the AGC. The squelch offset requirement does not change as the local noise strength changes
from installation to installation. Introducing squelch will reduce range modestly. Only introduce an amount of offset
sufficient to quiet the output.
AGC Configuration
By adding resistance from the CAGC pin to VDDBB or
VSSBB in parallel with the AGC capacitor, the ratio of decayto-attack time constant may be varied, although the value of
such adjustments must be studied on a per-application basis.
Generally the design value of 10:1 is adequate for the vast
majority of applications.
To maximize system range, it is important to keep the AGC
control voltage ripple low, preferably under 10mVpp once the
control voltage has attained its quiescent value. For this
reason capacitor values of at least 0.47µF are recommended.
Crystal Selection
Selecting Reference Oscillator Frequency fT
As with any superheterodyne receiver, the difference between the internal LO (local oscillator) frequency fLO and the
incoming transmit frequency fTX ideally must equal the IF
center frequency. Equation 1 may be used to compute the
appropriate fLO for a given fTX:
(1)
f
fT = LO
64.5
Frequency fT is in MHz. Connect a crystal of frequency fT to
REFOSC on the MICRF007. Four-decimal-place accuracy
on the frequency is generally adequate. The following table
identifies fT for some common transmit frequencies.
(2)
Reference Oscillator
Frequency
fT
315MHz
4.8970MHz
390MHz
6.0630MHz
418MHz
6.4983MHz
433.92MHz
6.7458MHz
Table 2. Common Transmitter Frequencies
External Timing Signals
Externally applied signals should be ac-coupled and the
amplitude must be limited to approximately 0.5Vpp.
Frequency and Capacitor Selection
Selection of the slicing level capacitor (CTH), and AGC
capacitor (CAGC) are briefly summarized in this section.
Selecting Capacitor CTH
The first step in the process is selection of a data-slicing-level
time constant. This selection is strongly dependent on system issues including system decode response time and data
code structure (that is, existence of data preamble, etc.). This
issue is covered in more detail in Application Note 22.
Source impedance of the CTH pin is given by equation (4),
where fT is in MHz:
(4)
RSC = 118kΩ
4.90
fT
Assuming that a slicing level time constant τ has been
established, capacitor CTH may be computed using equation
(5)
C TH =
τ
RSC
A standard ±20% X7R ceramic capacitor is generally sufficient.
Selecting CAGC Capacitor in Continuous Mode
Selection of CAGC is dictated by minimizing the ripple on the
AGC control voltage by using a sufficiently large capacitor.
Factory experience suggests that CAGC should be in the
vicinity of 0.47µF to 4.7µF. Large capacitor values should be
carefully considered as this determines the time required for
the AGC control voltage to settle from a completely discharged condition. AGC settling time from a completely
discharged (zero-volt) state is given approximately by Equation 6:
f 

fLO = fTX ± 1.064 TX 

390 
Frequencies fTX and fLO are in MHz. Note that two values of
fLO exist for any given fTX, distinguished as “high-side mixing”
MICRF007
Transmit
Frequency
fTX
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MICRF007
(6)
Micrel
∆t = 1.333C AGC − 0.44
1/10th magnitude of the pulldown current. The downward
droop is replenished according to the Equation 7:
where:
CAGC is in µF, and ∆t is in seconds.
Selecting CAGC Capacitor in Duty-Cycle Mode
Generally, droop of the AGC control voltage during shutdown
should be replenished as quickly as possible after the IC is
“turned-on”. As described in the functional description, for
about 10ms after the IC is turned on, the AGC push-pull
currents are increased to 45 times their normal values.
Consideration should be given to selecting a value for CAGC
and a shutdown time period such that the droop can be
replenished within this 10ms period.
Polarity of the droop is unknown, meaning the AGC voltage
could droop up or down. Worst-case from a recovery standpoint is downward droop, since the AGC pullup current is
December 2000
I
(7)
C AGC
=
∆V
∆t
where:
I = AGC pullup current for the initial 10ms (67.5µA)
CAGC = AGC capacitor value
∆t = droop recovery time
∆V = droop voltage
For example, if user desires ∆t = 10ms and chooses a 4.7µF
CAGC, then the allowable droop is about 144mV. Using the
same equation with 200nA worst case pin leakage and
assuming 1µA of capacitor leakage in the same direction, the
maximum allowable ∆t (shutdown time) is about 0.56s for
droop recovery in 10ms.
13
MICRF007
MICRF007
Micrel
315.0MHz Receiver/Decoder Application
Figure 7a illustrates a typical application for the MICRF007
UHF Receiver IC. This receiver operates continuously (not
duty cycled), and features 6-bit address decoding and two
output code bits.
Operation in this example is at 315.5MHz, and may be
customized by selection of the appropriate frequency reference (Y1), and adjustment of the antenna length. The value
of C4 would also change if the optional input filter is used.
Changes from the 1kb/s data rate may require a change in the
value of R1. A bill of materials accompanies the schematic.
0.4 monopole
antenna (11.6in)
+5V
Supply
Input
Optional Filter
8.2pF, 16.6nH
pcb foil inductor
1in of 30mil trace
C4
SEL0
VSSRF
6-bit
address
4.8970MHz
Y1
U1 MICRF002
REFOSC
L1
ANT
CAGC
4.7µF
VDD
C1
4.7µF
CTH
C2
2.2µF
SHUT
DO
U2 HT-12D
A0
VDD
A1
VT
A2
OSC1
A3
OSC2
A4
DIN
A5
D11
Code Bit 0
A6
D10
Code Bit 1
A7
D9
VSS
D8
R2
1k
R1
68k
RF Baseband
(Analog) (Digital)
Ground Ground
Figure 7a. 315MHz, 1kb/s On-Off Keyed Receiver/Decoder
Item
Part Number
Manufacturer
Description
U1
MICRF002
Micrel
UHF receiver
U2
HT-12D
Holtek
logic decoder
CSA6.00MG
Murata
6.00MHz ceramic resonator
SSF-LX100LID
Lumex
red LED
CR1
D1
R1
68k 1/4W 5%
R2
Vishay
1k 1/4W 5%
C1
Vishay
4.7µF dipped tantalum capacitor
C3
Vishay
4.7µF dipped tantalum capacitor
C2
Vishay
2.2µF dipped tantalum capacitor
C4
Vishay
8.2pF COG ceramic capacitor
Figure 7b. Bill of Material
Vendor
Telephone
Vishay
(203) 268-6261
FAX
—
Holtek
(408) 894-9046
(408) 894-0838
Lumex
(800) 278-5666
(847) 359-8904
Murata
(800) 241-6574
(770) 436-3030
Figure 7c. Component Vendors
MICRF007
14
December 2000
MICRF007
Micrel
Package Information
0.026 (0.65)
MAX)
PIN 1
0.157 (3.99)
0.150 (3.81)
DIMENSIONS:
INCHES (MM)
0.050 (1.27)
TYP
0.064 (1.63)
0.045 (1.14)
0.197 (5.0)
0.189 (4.8)
0.020 (0.51)
0.013 (0.33)
0.0098 (0.249)
0.0040 (0.102)
0°–8°
SEATING
PLANE
45°
0.010 (0.25)
0.007 (0.18)
0.050 (1.27)
0.016 (0.40)
0.244 (6.20)
0.228 (5.79)
8-Lead SOP (M)
December 2000
15
MICRF007
MICRF007
Micrel
MICREL INC.
TEL
1849 FORTUNE DRIVE SAN JOSE, CA 95131
+ 1 (408) 944-0800
FAX
+ 1 (408) 944-0970
WEB
USA
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 1999 Micrel Incorporated
MICRF007
16
December 2000